nvmm_x86_svm.c revision 1.8
1 /* $NetBSD: nvmm_x86_svm.c,v 1.8 2019/01/02 12:18:08 maxv Exp $ */ 2 3 /* 4 * Copyright (c) 2018 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Maxime Villard. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: nvmm_x86_svm.c,v 1.8 2019/01/02 12:18:08 maxv Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/kmem.h> 39 #include <sys/cpu.h> 40 #include <sys/xcall.h> 41 42 #include <uvm/uvm.h> 43 #include <uvm/uvm_page.h> 44 45 #include <x86/cputypes.h> 46 #include <x86/specialreg.h> 47 #include <x86/pmap.h> 48 #include <x86/dbregs.h> 49 #include <machine/cpuvar.h> 50 51 #include <dev/nvmm/nvmm.h> 52 #include <dev/nvmm/nvmm_internal.h> 53 #include <dev/nvmm/x86/nvmm_x86.h> 54 55 int svm_vmrun(paddr_t, uint64_t *); 56 57 #define MSR_VM_HSAVE_PA 0xC0010117 58 59 /* -------------------------------------------------------------------------- */ 60 61 #define VMCB_EXITCODE_CR0_READ 0x0000 62 #define VMCB_EXITCODE_CR1_READ 0x0001 63 #define VMCB_EXITCODE_CR2_READ 0x0002 64 #define VMCB_EXITCODE_CR3_READ 0x0003 65 #define VMCB_EXITCODE_CR4_READ 0x0004 66 #define VMCB_EXITCODE_CR5_READ 0x0005 67 #define VMCB_EXITCODE_CR6_READ 0x0006 68 #define VMCB_EXITCODE_CR7_READ 0x0007 69 #define VMCB_EXITCODE_CR8_READ 0x0008 70 #define VMCB_EXITCODE_CR9_READ 0x0009 71 #define VMCB_EXITCODE_CR10_READ 0x000A 72 #define VMCB_EXITCODE_CR11_READ 0x000B 73 #define VMCB_EXITCODE_CR12_READ 0x000C 74 #define VMCB_EXITCODE_CR13_READ 0x000D 75 #define VMCB_EXITCODE_CR14_READ 0x000E 76 #define VMCB_EXITCODE_CR15_READ 0x000F 77 #define VMCB_EXITCODE_CR0_WRITE 0x0010 78 #define VMCB_EXITCODE_CR1_WRITE 0x0011 79 #define VMCB_EXITCODE_CR2_WRITE 0x0012 80 #define VMCB_EXITCODE_CR3_WRITE 0x0013 81 #define VMCB_EXITCODE_CR4_WRITE 0x0014 82 #define VMCB_EXITCODE_CR5_WRITE 0x0015 83 #define VMCB_EXITCODE_CR6_WRITE 0x0016 84 #define VMCB_EXITCODE_CR7_WRITE 0x0017 85 #define VMCB_EXITCODE_CR8_WRITE 0x0018 86 #define VMCB_EXITCODE_CR9_WRITE 0x0019 87 #define VMCB_EXITCODE_CR10_WRITE 0x001A 88 #define VMCB_EXITCODE_CR11_WRITE 0x001B 89 #define VMCB_EXITCODE_CR12_WRITE 0x001C 90 #define VMCB_EXITCODE_CR13_WRITE 0x001D 91 #define VMCB_EXITCODE_CR14_WRITE 0x001E 92 #define VMCB_EXITCODE_CR15_WRITE 0x001F 93 #define VMCB_EXITCODE_DR0_READ 0x0020 94 #define VMCB_EXITCODE_DR1_READ 0x0021 95 #define VMCB_EXITCODE_DR2_READ 0x0022 96 #define VMCB_EXITCODE_DR3_READ 0x0023 97 #define VMCB_EXITCODE_DR4_READ 0x0024 98 #define VMCB_EXITCODE_DR5_READ 0x0025 99 #define VMCB_EXITCODE_DR6_READ 0x0026 100 #define VMCB_EXITCODE_DR7_READ 0x0027 101 #define VMCB_EXITCODE_DR8_READ 0x0028 102 #define VMCB_EXITCODE_DR9_READ 0x0029 103 #define VMCB_EXITCODE_DR10_READ 0x002A 104 #define VMCB_EXITCODE_DR11_READ 0x002B 105 #define VMCB_EXITCODE_DR12_READ 0x002C 106 #define VMCB_EXITCODE_DR13_READ 0x002D 107 #define VMCB_EXITCODE_DR14_READ 0x002E 108 #define VMCB_EXITCODE_DR15_READ 0x002F 109 #define VMCB_EXITCODE_DR0_WRITE 0x0030 110 #define VMCB_EXITCODE_DR1_WRITE 0x0031 111 #define VMCB_EXITCODE_DR2_WRITE 0x0032 112 #define VMCB_EXITCODE_DR3_WRITE 0x0033 113 #define VMCB_EXITCODE_DR4_WRITE 0x0034 114 #define VMCB_EXITCODE_DR5_WRITE 0x0035 115 #define VMCB_EXITCODE_DR6_WRITE 0x0036 116 #define VMCB_EXITCODE_DR7_WRITE 0x0037 117 #define VMCB_EXITCODE_DR8_WRITE 0x0038 118 #define VMCB_EXITCODE_DR9_WRITE 0x0039 119 #define VMCB_EXITCODE_DR10_WRITE 0x003A 120 #define VMCB_EXITCODE_DR11_WRITE 0x003B 121 #define VMCB_EXITCODE_DR12_WRITE 0x003C 122 #define VMCB_EXITCODE_DR13_WRITE 0x003D 123 #define VMCB_EXITCODE_DR14_WRITE 0x003E 124 #define VMCB_EXITCODE_DR15_WRITE 0x003F 125 #define VMCB_EXITCODE_EXCP0 0x0040 126 #define VMCB_EXITCODE_EXCP1 0x0041 127 #define VMCB_EXITCODE_EXCP2 0x0042 128 #define VMCB_EXITCODE_EXCP3 0x0043 129 #define VMCB_EXITCODE_EXCP4 0x0044 130 #define VMCB_EXITCODE_EXCP5 0x0045 131 #define VMCB_EXITCODE_EXCP6 0x0046 132 #define VMCB_EXITCODE_EXCP7 0x0047 133 #define VMCB_EXITCODE_EXCP8 0x0048 134 #define VMCB_EXITCODE_EXCP9 0x0049 135 #define VMCB_EXITCODE_EXCP10 0x004A 136 #define VMCB_EXITCODE_EXCP11 0x004B 137 #define VMCB_EXITCODE_EXCP12 0x004C 138 #define VMCB_EXITCODE_EXCP13 0x004D 139 #define VMCB_EXITCODE_EXCP14 0x004E 140 #define VMCB_EXITCODE_EXCP15 0x004F 141 #define VMCB_EXITCODE_EXCP16 0x0050 142 #define VMCB_EXITCODE_EXCP17 0x0051 143 #define VMCB_EXITCODE_EXCP18 0x0052 144 #define VMCB_EXITCODE_EXCP19 0x0053 145 #define VMCB_EXITCODE_EXCP20 0x0054 146 #define VMCB_EXITCODE_EXCP21 0x0055 147 #define VMCB_EXITCODE_EXCP22 0x0056 148 #define VMCB_EXITCODE_EXCP23 0x0057 149 #define VMCB_EXITCODE_EXCP24 0x0058 150 #define VMCB_EXITCODE_EXCP25 0x0059 151 #define VMCB_EXITCODE_EXCP26 0x005A 152 #define VMCB_EXITCODE_EXCP27 0x005B 153 #define VMCB_EXITCODE_EXCP28 0x005C 154 #define VMCB_EXITCODE_EXCP29 0x005D 155 #define VMCB_EXITCODE_EXCP30 0x005E 156 #define VMCB_EXITCODE_EXCP31 0x005F 157 #define VMCB_EXITCODE_INTR 0x0060 158 #define VMCB_EXITCODE_NMI 0x0061 159 #define VMCB_EXITCODE_SMI 0x0062 160 #define VMCB_EXITCODE_INIT 0x0063 161 #define VMCB_EXITCODE_VINTR 0x0064 162 #define VMCB_EXITCODE_CR0_SEL_WRITE 0x0065 163 #define VMCB_EXITCODE_IDTR_READ 0x0066 164 #define VMCB_EXITCODE_GDTR_READ 0x0067 165 #define VMCB_EXITCODE_LDTR_READ 0x0068 166 #define VMCB_EXITCODE_TR_READ 0x0069 167 #define VMCB_EXITCODE_IDTR_WRITE 0x006A 168 #define VMCB_EXITCODE_GDTR_WRITE 0x006B 169 #define VMCB_EXITCODE_LDTR_WRITE 0x006C 170 #define VMCB_EXITCODE_TR_WRITE 0x006D 171 #define VMCB_EXITCODE_RDTSC 0x006E 172 #define VMCB_EXITCODE_RDPMC 0x006F 173 #define VMCB_EXITCODE_PUSHF 0x0070 174 #define VMCB_EXITCODE_POPF 0x0071 175 #define VMCB_EXITCODE_CPUID 0x0072 176 #define VMCB_EXITCODE_RSM 0x0073 177 #define VMCB_EXITCODE_IRET 0x0074 178 #define VMCB_EXITCODE_SWINT 0x0075 179 #define VMCB_EXITCODE_INVD 0x0076 180 #define VMCB_EXITCODE_PAUSE 0x0077 181 #define VMCB_EXITCODE_HLT 0x0078 182 #define VMCB_EXITCODE_INVLPG 0x0079 183 #define VMCB_EXITCODE_INVLPGA 0x007A 184 #define VMCB_EXITCODE_IOIO 0x007B 185 #define VMCB_EXITCODE_MSR 0x007C 186 #define VMCB_EXITCODE_TASK_SWITCH 0x007D 187 #define VMCB_EXITCODE_FERR_FREEZE 0x007E 188 #define VMCB_EXITCODE_SHUTDOWN 0x007F 189 #define VMCB_EXITCODE_VMRUN 0x0080 190 #define VMCB_EXITCODE_VMMCALL 0x0081 191 #define VMCB_EXITCODE_VMLOAD 0x0082 192 #define VMCB_EXITCODE_VMSAVE 0x0083 193 #define VMCB_EXITCODE_STGI 0x0084 194 #define VMCB_EXITCODE_CLGI 0x0085 195 #define VMCB_EXITCODE_SKINIT 0x0086 196 #define VMCB_EXITCODE_RDTSCP 0x0087 197 #define VMCB_EXITCODE_ICEBP 0x0088 198 #define VMCB_EXITCODE_WBINVD 0x0089 199 #define VMCB_EXITCODE_MONITOR 0x008A 200 #define VMCB_EXITCODE_MWAIT 0x008B 201 #define VMCB_EXITCODE_MWAIT_CONDITIONAL 0x008C 202 #define VMCB_EXITCODE_XSETBV 0x008D 203 #define VMCB_EXITCODE_EFER_WRITE_TRAP 0x008F 204 #define VMCB_EXITCODE_CR0_WRITE_TRAP 0x0090 205 #define VMCB_EXITCODE_CR1_WRITE_TRAP 0x0091 206 #define VMCB_EXITCODE_CR2_WRITE_TRAP 0x0092 207 #define VMCB_EXITCODE_CR3_WRITE_TRAP 0x0093 208 #define VMCB_EXITCODE_CR4_WRITE_TRAP 0x0094 209 #define VMCB_EXITCODE_CR5_WRITE_TRAP 0x0095 210 #define VMCB_EXITCODE_CR6_WRITE_TRAP 0x0096 211 #define VMCB_EXITCODE_CR7_WRITE_TRAP 0x0097 212 #define VMCB_EXITCODE_CR8_WRITE_TRAP 0x0098 213 #define VMCB_EXITCODE_CR9_WRITE_TRAP 0x0099 214 #define VMCB_EXITCODE_CR10_WRITE_TRAP 0x009A 215 #define VMCB_EXITCODE_CR11_WRITE_TRAP 0x009B 216 #define VMCB_EXITCODE_CR12_WRITE_TRAP 0x009C 217 #define VMCB_EXITCODE_CR13_WRITE_TRAP 0x009D 218 #define VMCB_EXITCODE_CR14_WRITE_TRAP 0x009E 219 #define VMCB_EXITCODE_CR15_WRITE_TRAP 0x009F 220 #define VMCB_EXITCODE_NPF 0x0400 221 #define VMCB_EXITCODE_AVIC_INCOMP_IPI 0x0401 222 #define VMCB_EXITCODE_AVIC_NOACCEL 0x0402 223 #define VMCB_EXITCODE_VMGEXIT 0x0403 224 #define VMCB_EXITCODE_INVALID -1 225 226 /* -------------------------------------------------------------------------- */ 227 228 struct vmcb_ctrl { 229 uint32_t intercept_cr; 230 #define VMCB_CTRL_INTERCEPT_RCR(x) __BIT( 0 + x) 231 #define VMCB_CTRL_INTERCEPT_WCR(x) __BIT(16 + x) 232 233 uint32_t intercept_dr; 234 #define VMCB_CTRL_INTERCEPT_RDR(x) __BIT( 0 + x) 235 #define VMCB_CTRL_INTERCEPT_WDR(x) __BIT(16 + x) 236 237 uint32_t intercept_vec; 238 #define VMCB_CTRL_INTERCEPT_VEC(x) __BIT(x) 239 240 uint32_t intercept_misc1; 241 #define VMCB_CTRL_INTERCEPT_INTR __BIT(0) 242 #define VMCB_CTRL_INTERCEPT_NMI __BIT(1) 243 #define VMCB_CTRL_INTERCEPT_SMI __BIT(2) 244 #define VMCB_CTRL_INTERCEPT_INIT __BIT(3) 245 #define VMCB_CTRL_INTERCEPT_VINTR __BIT(4) 246 #define VMCB_CTRL_INTERCEPT_CR0_SPEC __BIT(5) 247 #define VMCB_CTRL_INTERCEPT_RIDTR __BIT(6) 248 #define VMCB_CTRL_INTERCEPT_RGDTR __BIT(7) 249 #define VMCB_CTRL_INTERCEPT_RLDTR __BIT(8) 250 #define VMCB_CTRL_INTERCEPT_RTR __BIT(9) 251 #define VMCB_CTRL_INTERCEPT_WIDTR __BIT(10) 252 #define VMCB_CTRL_INTERCEPT_WGDTR __BIT(11) 253 #define VMCB_CTRL_INTERCEPT_WLDTR __BIT(12) 254 #define VMCB_CTRL_INTERCEPT_WTR __BIT(13) 255 #define VMCB_CTRL_INTERCEPT_RDTSC __BIT(14) 256 #define VMCB_CTRL_INTERCEPT_RDPMC __BIT(15) 257 #define VMCB_CTRL_INTERCEPT_PUSHF __BIT(16) 258 #define VMCB_CTRL_INTERCEPT_POPF __BIT(17) 259 #define VMCB_CTRL_INTERCEPT_CPUID __BIT(18) 260 #define VMCB_CTRL_INTERCEPT_RSM __BIT(19) 261 #define VMCB_CTRL_INTERCEPT_IRET __BIT(20) 262 #define VMCB_CTRL_INTERCEPT_INTN __BIT(21) 263 #define VMCB_CTRL_INTERCEPT_INVD __BIT(22) 264 #define VMCB_CTRL_INTERCEPT_PAUSE __BIT(23) 265 #define VMCB_CTRL_INTERCEPT_HLT __BIT(24) 266 #define VMCB_CTRL_INTERCEPT_INVLPG __BIT(25) 267 #define VMCB_CTRL_INTERCEPT_INVLPGA __BIT(26) 268 #define VMCB_CTRL_INTERCEPT_IOIO_PROT __BIT(27) 269 #define VMCB_CTRL_INTERCEPT_MSR_PROT __BIT(28) 270 #define VMCB_CTRL_INTERCEPT_TASKSW __BIT(29) 271 #define VMCB_CTRL_INTERCEPT_FERR_FREEZE __BIT(30) 272 #define VMCB_CTRL_INTERCEPT_SHUTDOWN __BIT(31) 273 274 uint32_t intercept_misc2; 275 #define VMCB_CTRL_INTERCEPT_VMRUN __BIT(0) 276 #define VMCB_CTRL_INTERCEPT_VMMCALL __BIT(1) 277 #define VMCB_CTRL_INTERCEPT_VMLOAD __BIT(2) 278 #define VMCB_CTRL_INTERCEPT_VMSAVE __BIT(3) 279 #define VMCB_CTRL_INTERCEPT_STGI __BIT(4) 280 #define VMCB_CTRL_INTERCEPT_CLGI __BIT(5) 281 #define VMCB_CTRL_INTERCEPT_SKINIT __BIT(6) 282 #define VMCB_CTRL_INTERCEPT_RDTSCP __BIT(7) 283 #define VMCB_CTRL_INTERCEPT_ICEBP __BIT(8) 284 #define VMCB_CTRL_INTERCEPT_WBINVD __BIT(9) 285 #define VMCB_CTRL_INTERCEPT_MONITOR __BIT(10) 286 #define VMCB_CTRL_INTERCEPT_MWAIT __BIT(12) 287 #define VMCB_CTRL_INTERCEPT_XSETBV __BIT(13) 288 #define VMCB_CTRL_INTERCEPT_EFER_SPEC __BIT(15) 289 #define VMCB_CTRL_INTERCEPT_WCR_SPEC(x) __BIT(16 + x) 290 291 uint8_t rsvd1[40]; 292 uint16_t pause_filt_thresh; 293 uint16_t pause_filt_cnt; 294 uint64_t iopm_base_pa; 295 uint64_t msrpm_base_pa; 296 uint64_t tsc_offset; 297 uint32_t guest_asid; 298 299 uint32_t tlb_ctrl; 300 #define VMCB_CTRL_TLB_CTRL_FLUSH_ALL 0x01 301 #define VMCB_CTRL_TLB_CTRL_FLUSH_GUEST 0x03 302 #define VMCB_CTRL_TLB_CTRL_FLUSH_GUEST_NONGLOBAL 0x07 303 304 uint64_t v; 305 #define VMCB_CTRL_V_TPR __BITS(7,0) 306 #define VMCB_CTRL_V_IRQ __BIT(8) 307 #define VMCB_CTRL_V_VGIF __BIT(9) 308 #define VMCB_CTRL_V_INTR_PRIO __BITS(19,16) 309 #define VMCB_CTRL_V_IGN_TPR __BIT(20) 310 #define VMCB_CTRL_V_INTR_MASKING __BIT(24) 311 #define VMCB_CTRL_V_GUEST_VGIF __BIT(25) 312 #define VMCB_CTRL_V_AVIC_EN __BIT(31) 313 #define VMCB_CTRL_V_INTR_VECTOR __BITS(39,32) 314 315 uint64_t intr; 316 #define VMCB_CTRL_INTR_SHADOW __BIT(0) 317 #define VMCB_CTRL_GUEST_INTR_MASK __BIT(1) 318 319 uint64_t exitcode; 320 uint64_t exitinfo1; 321 uint64_t exitinfo2; 322 323 uint64_t exitintinfo; 324 #define VMCB_CTRL_EXITINTINFO_VECTOR __BITS(7,0) 325 #define VMCB_CTRL_EXITINTINFO_TYPE __BITS(10,8) 326 #define VMCB_CTRL_EXITINTINFO_EV __BIT(11) 327 #define VMCB_CTRL_EXITINTINFO_V __BIT(31) 328 #define VMCB_CTRL_EXITINTINFO_ERRORCODE __BITS(63,32) 329 330 uint64_t enable1; 331 #define VMCB_CTRL_ENABLE_NP __BIT(0) 332 #define VMCB_CTRL_ENABLE_SEV __BIT(1) 333 #define VMCB_CTRL_ENABLE_ES_SEV __BIT(2) 334 335 uint64_t avic; 336 #define VMCB_CTRL_AVIC_APIC_BAR __BITS(51,0) 337 338 uint64_t ghcb; 339 340 uint64_t eventinj; 341 #define VMCB_CTRL_EVENTINJ_VECTOR __BITS(7,0) 342 #define VMCB_CTRL_EVENTINJ_TYPE __BITS(10,8) 343 #define VMCB_CTRL_EVENTINJ_EV __BIT(11) 344 #define VMCB_CTRL_EVENTINJ_V __BIT(31) 345 #define VMCB_CTRL_EVENTINJ_ERRORCODE __BITS(63,32) 346 347 uint64_t n_cr3; 348 349 uint64_t enable2; 350 #define VMCB_CTRL_ENABLE_LBR __BIT(0) 351 #define VMCB_CTRL_ENABLE_VVMSAVE __BIT(1) 352 353 uint32_t vmcb_clean; 354 #define VMCB_CTRL_VMCB_CLEAN_I __BIT(0) 355 #define VMCB_CTRL_VMCB_CLEAN_IOPM __BIT(1) 356 #define VMCB_CTRL_VMCB_CLEAN_ASID __BIT(2) 357 #define VMCB_CTRL_VMCB_CLEAN_TPR __BIT(3) 358 #define VMCB_CTRL_VMCB_CLEAN_NP __BIT(4) 359 #define VMCB_CTRL_VMCB_CLEAN_CR __BIT(5) 360 #define VMCB_CTRL_VMCB_CLEAN_DR __BIT(6) 361 #define VMCB_CTRL_VMCB_CLEAN_DT __BIT(7) 362 #define VMCB_CTRL_VMCB_CLEAN_SEG __BIT(8) 363 #define VMCB_CTRL_VMCB_CLEAN_CR2 __BIT(9) 364 #define VMCB_CTRL_VMCB_CLEAN_LBR __BIT(10) 365 #define VMCB_CTRL_VMCB_CLEAN_AVIC __BIT(11) 366 367 uint32_t rsvd2; 368 uint64_t nrip; 369 uint8_t inst_len; 370 uint8_t inst_bytes[15]; 371 uint8_t pad[800]; 372 } __packed; 373 374 CTASSERT(sizeof(struct vmcb_ctrl) == 1024); 375 376 struct vmcb_segment { 377 uint16_t selector; 378 uint16_t attrib; /* hidden */ 379 uint32_t limit; /* hidden */ 380 uint64_t base; /* hidden */ 381 } __packed; 382 383 CTASSERT(sizeof(struct vmcb_segment) == 16); 384 385 struct vmcb_state { 386 struct vmcb_segment es; 387 struct vmcb_segment cs; 388 struct vmcb_segment ss; 389 struct vmcb_segment ds; 390 struct vmcb_segment fs; 391 struct vmcb_segment gs; 392 struct vmcb_segment gdt; 393 struct vmcb_segment ldt; 394 struct vmcb_segment idt; 395 struct vmcb_segment tr; 396 uint8_t rsvd1[43]; 397 uint8_t cpl; 398 uint8_t rsvd2[4]; 399 uint64_t efer; 400 uint8_t rsvd3[112]; 401 uint64_t cr4; 402 uint64_t cr3; 403 uint64_t cr0; 404 uint64_t dr7; 405 uint64_t dr6; 406 uint64_t rflags; 407 uint64_t rip; 408 uint8_t rsvd4[88]; 409 uint64_t rsp; 410 uint8_t rsvd5[24]; 411 uint64_t rax; 412 uint64_t star; 413 uint64_t lstar; 414 uint64_t cstar; 415 uint64_t sfmask; 416 uint64_t kernelgsbase; 417 uint64_t sysenter_cs; 418 uint64_t sysenter_esp; 419 uint64_t sysenter_eip; 420 uint64_t cr2; 421 uint8_t rsvd6[32]; 422 uint64_t g_pat; 423 uint64_t dbgctl; 424 uint64_t br_from; 425 uint64_t br_to; 426 uint64_t int_from; 427 uint64_t int_to; 428 uint8_t pad[2408]; 429 } __packed; 430 431 CTASSERT(sizeof(struct vmcb_state) == 0xC00); 432 433 struct vmcb { 434 struct vmcb_ctrl ctrl; 435 struct vmcb_state state; 436 } __packed; 437 438 CTASSERT(sizeof(struct vmcb) == PAGE_SIZE); 439 CTASSERT(offsetof(struct vmcb, state) == 0x400); 440 441 /* -------------------------------------------------------------------------- */ 442 443 struct svm_hsave { 444 paddr_t pa; 445 }; 446 447 static struct svm_hsave hsave[MAXCPUS]; 448 449 static uint8_t *svm_asidmap __read_mostly; 450 static uint32_t svm_maxasid __read_mostly; 451 static kmutex_t svm_asidlock __cacheline_aligned; 452 453 static bool svm_decode_assist __read_mostly; 454 static uint32_t svm_ctrl_tlb_flush __read_mostly; 455 456 #define SVM_XCR0_MASK_DEFAULT (XCR0_X87|XCR0_SSE) 457 static uint64_t svm_xcr0_mask __read_mostly; 458 459 #define SVM_NCPUIDS 32 460 461 #define VMCB_NPAGES 1 462 463 #define MSRBM_NPAGES 2 464 #define MSRBM_SIZE (MSRBM_NPAGES * PAGE_SIZE) 465 466 #define IOBM_NPAGES 3 467 #define IOBM_SIZE (IOBM_NPAGES * PAGE_SIZE) 468 469 /* Does not include EFER_LMSLE. */ 470 #define EFER_VALID \ 471 (EFER_SCE|EFER_LME|EFER_LMA|EFER_NXE|EFER_SVME|EFER_FFXSR|EFER_TCE) 472 473 #define EFER_TLB_FLUSH \ 474 (EFER_NXE|EFER_LMA|EFER_LME) 475 #define CR0_TLB_FLUSH \ 476 (CR0_PG|CR0_WP|CR0_CD|CR0_NW) 477 #define CR4_TLB_FLUSH \ 478 (CR4_PGE|CR4_PAE|CR4_PSE) 479 480 /* -------------------------------------------------------------------------- */ 481 482 struct svm_machdata { 483 bool cpuidpresent[SVM_NCPUIDS]; 484 struct nvmm_x86_conf_cpuid cpuid[SVM_NCPUIDS]; 485 }; 486 487 static const size_t svm_conf_sizes[NVMM_X86_NCONF] = { 488 [NVMM_X86_CONF_CPUID] = sizeof(struct nvmm_x86_conf_cpuid) 489 }; 490 491 struct svm_cpudata { 492 /* x64-specific */ 493 struct nvmm_x64_state state; 494 495 /* General */ 496 bool shared_asid; 497 bool tlb_want_flush; 498 499 /* VMCB */ 500 struct vmcb *vmcb; 501 paddr_t vmcb_pa; 502 503 /* I/O bitmap */ 504 uint8_t *iobm; 505 paddr_t iobm_pa; 506 507 /* MSR bitmap */ 508 uint8_t *msrbm; 509 paddr_t msrbm_pa; 510 511 /* Host state */ 512 uint64_t xcr0; 513 uint64_t star; 514 uint64_t lstar; 515 uint64_t cstar; 516 uint64_t sfmask; 517 uint64_t cr2; 518 bool ts_set; 519 struct xsave_header hfpu __aligned(16); 520 521 /* Guest state */ 522 bool in_nmi; 523 uint64_t tsc_offset; 524 struct xsave_header gfpu __aligned(16); 525 }; 526 527 #define SVM_EVENT_TYPE_HW_INT 0 528 #define SVM_EVENT_TYPE_NMI 2 529 #define SVM_EVENT_TYPE_EXC 3 530 #define SVM_EVENT_TYPE_SW_INT 4 531 532 static void 533 svm_event_waitexit_enable(struct vmcb *vmcb, bool nmi) 534 { 535 if (nmi) { 536 vmcb->ctrl.intercept_misc1 |= VMCB_CTRL_INTERCEPT_IRET; 537 } else { 538 vmcb->ctrl.intercept_misc1 |= VMCB_CTRL_INTERCEPT_VINTR; 539 vmcb->ctrl.v |= (VMCB_CTRL_V_IRQ | 540 __SHIFTIN(0, VMCB_CTRL_V_INTR_VECTOR)); 541 } 542 } 543 544 static void 545 svm_event_waitexit_disable(struct vmcb *vmcb, bool nmi) 546 { 547 if (nmi) { 548 vmcb->ctrl.intercept_misc1 &= ~VMCB_CTRL_INTERCEPT_IRET; 549 } else { 550 vmcb->ctrl.intercept_misc1 &= ~VMCB_CTRL_INTERCEPT_VINTR; 551 vmcb->ctrl.v &= ~(VMCB_CTRL_V_IRQ | 552 __SHIFTIN(0, VMCB_CTRL_V_INTR_VECTOR)); 553 } 554 } 555 556 static inline int 557 svm_event_has_error(uint64_t vector) 558 { 559 switch (vector) { 560 case 8: /* #DF */ 561 case 10: /* #TS */ 562 case 11: /* #NP */ 563 case 12: /* #SS */ 564 case 13: /* #GP */ 565 case 14: /* #PF */ 566 case 17: /* #AC */ 567 case 30: /* #SX */ 568 return 1; 569 default: 570 return 0; 571 } 572 } 573 574 static int 575 svm_vcpu_inject(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 576 struct nvmm_event *event) 577 { 578 struct svm_cpudata *cpudata = vcpu->cpudata; 579 struct vmcb *vmcb = cpudata->vmcb; 580 uint64_t rflags = vmcb->state.rflags; 581 int type = 0, err = 0; 582 uint64_t tpr; 583 584 if (event->vector >= 256) { 585 return EINVAL; 586 } 587 588 switch (event->type) { 589 case NVMM_EVENT_INTERRUPT_HW: 590 type = SVM_EVENT_TYPE_HW_INT; 591 if (event->vector == 2) { 592 type = SVM_EVENT_TYPE_NMI; 593 } 594 if (type == SVM_EVENT_TYPE_NMI) { 595 if (cpudata->in_nmi) { 596 svm_event_waitexit_enable(vmcb, true); 597 return EAGAIN; 598 } 599 cpudata->in_nmi = true; 600 } else { 601 tpr = __SHIFTOUT(vmcb->ctrl.v, VMCB_CTRL_V_TPR); 602 if ((rflags & PSL_I) == 0 || event->u.prio <= tpr) { 603 svm_event_waitexit_enable(vmcb, false); 604 return EAGAIN; 605 } 606 } 607 err = 0; 608 break; 609 case NVMM_EVENT_INTERRUPT_SW: 610 type = SVM_EVENT_TYPE_SW_INT; 611 err = 0; 612 break; 613 case NVMM_EVENT_EXCEPTION: 614 type = SVM_EVENT_TYPE_EXC; 615 if (event->vector == 2 || event->vector >= 32) 616 return EINVAL; 617 err = svm_event_has_error(event->vector); 618 break; 619 default: 620 return EINVAL; 621 } 622 623 vmcb->ctrl.eventinj = 624 __SHIFTIN(event->vector, VMCB_CTRL_EVENTINJ_VECTOR) | 625 __SHIFTIN(type, VMCB_CTRL_EVENTINJ_TYPE) | 626 __SHIFTIN(err, VMCB_CTRL_EVENTINJ_EV) | 627 __SHIFTIN(1, VMCB_CTRL_EVENTINJ_V) | 628 __SHIFTIN(event->u.error, VMCB_CTRL_EVENTINJ_ERRORCODE); 629 630 return 0; 631 } 632 633 static void 634 svm_inject_ud(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 635 { 636 struct nvmm_event event; 637 int ret __diagused; 638 639 event.type = NVMM_EVENT_EXCEPTION; 640 event.vector = 6; 641 event.u.error = 0; 642 643 ret = svm_vcpu_inject(mach, vcpu, &event); 644 KASSERT(ret == 0); 645 } 646 647 static void 648 svm_inject_db(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 649 { 650 struct nvmm_event event; 651 int ret __diagused; 652 653 event.type = NVMM_EVENT_EXCEPTION; 654 event.vector = 1; 655 event.u.error = 0; 656 657 ret = svm_vcpu_inject(mach, vcpu, &event); 658 KASSERT(ret == 0); 659 } 660 661 static void 662 svm_inject_gp(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 663 { 664 struct nvmm_event event; 665 int ret __diagused; 666 667 event.type = NVMM_EVENT_EXCEPTION; 668 event.vector = 13; 669 event.u.error = 0; 670 671 ret = svm_vcpu_inject(mach, vcpu, &event); 672 KASSERT(ret == 0); 673 } 674 675 static void 676 svm_inkernel_handle_cpuid(struct nvmm_cpu *vcpu, uint64_t eax, uint64_t ecx) 677 { 678 struct svm_cpudata *cpudata = vcpu->cpudata; 679 struct nvmm_x64_state *state = &cpudata->state; 680 681 switch (eax) { 682 case 0x00000001: /* APIC number in RBX. The rest is tunable. */ 683 state->gprs[NVMM_X64_GPR_RBX] &= ~CPUID_LOCAL_APIC_ID; 684 state->gprs[NVMM_X64_GPR_RBX] |= __SHIFTIN(vcpu->cpuid, 685 CPUID_LOCAL_APIC_ID); 686 break; 687 case 0x0000000D: /* FPU description. Not tunable. */ 688 if (ecx != 0 || svm_xcr0_mask == 0) { 689 break; 690 } 691 cpudata->vmcb->state.rax = svm_xcr0_mask & 0xFFFFFFFF; 692 if (state->crs[NVMM_X64_CR_XCR0] & XCR0_SSE) { 693 state->gprs[NVMM_X64_GPR_RBX] = sizeof(struct fxsave); 694 } else { 695 state->gprs[NVMM_X64_GPR_RBX] = sizeof(struct save87); 696 } 697 state->gprs[NVMM_X64_GPR_RBX] += 64; /* XSAVE header */ 698 state->gprs[NVMM_X64_GPR_RCX] = sizeof(struct fxsave); 699 state->gprs[NVMM_X64_GPR_RDX] = svm_xcr0_mask >> 32; 700 break; 701 default: 702 break; 703 } 704 } 705 706 static void 707 svm_exit_cpuid(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 708 struct nvmm_exit *exit) 709 { 710 struct svm_machdata *machdata = mach->machdata; 711 struct svm_cpudata *cpudata = vcpu->cpudata; 712 struct nvmm_x64_state *state = &cpudata->state; 713 struct nvmm_x86_conf_cpuid *cpuid; 714 uint64_t eax, ecx; 715 u_int descs[4]; 716 size_t i; 717 718 eax = cpudata->vmcb->state.rax; 719 ecx = state->gprs[NVMM_X64_GPR_RCX]; 720 x86_cpuid2(eax, ecx, descs); 721 722 cpudata->vmcb->state.rax = descs[0]; 723 state->gprs[NVMM_X64_GPR_RBX] = descs[1]; 724 state->gprs[NVMM_X64_GPR_RCX] = descs[2]; 725 state->gprs[NVMM_X64_GPR_RDX] = descs[3]; 726 727 for (i = 0; i < SVM_NCPUIDS; i++) { 728 cpuid = &machdata->cpuid[i]; 729 if (!machdata->cpuidpresent[i]) { 730 continue; 731 } 732 if (cpuid->leaf != eax) { 733 continue; 734 } 735 736 /* del */ 737 cpudata->vmcb->state.rax &= ~cpuid->del.eax; 738 state->gprs[NVMM_X64_GPR_RBX] &= ~cpuid->del.ebx; 739 state->gprs[NVMM_X64_GPR_RCX] &= ~cpuid->del.ecx; 740 state->gprs[NVMM_X64_GPR_RDX] &= ~cpuid->del.edx; 741 742 /* set */ 743 cpudata->vmcb->state.rax |= cpuid->set.eax; 744 state->gprs[NVMM_X64_GPR_RBX] |= cpuid->set.ebx; 745 state->gprs[NVMM_X64_GPR_RCX] |= cpuid->set.ecx; 746 state->gprs[NVMM_X64_GPR_RDX] |= cpuid->set.edx; 747 748 break; 749 } 750 751 /* Overwrite non-tunable leaves. */ 752 svm_inkernel_handle_cpuid(vcpu, eax, ecx); 753 754 /* For now we omit DBREGS. */ 755 if (__predict_false(cpudata->vmcb->state.rflags & PSL_T)) { 756 svm_inject_db(mach, vcpu); 757 } 758 759 cpudata->vmcb->state.rip = cpudata->vmcb->ctrl.nrip; 760 exit->reason = NVMM_EXIT_NONE; 761 } 762 763 #define SVM_EXIT_IO_PORT __BITS(31,16) 764 #define SVM_EXIT_IO_SEG __BITS(12,10) 765 #define SVM_EXIT_IO_A64 __BIT(9) 766 #define SVM_EXIT_IO_A32 __BIT(8) 767 #define SVM_EXIT_IO_A16 __BIT(7) 768 #define SVM_EXIT_IO_SZ32 __BIT(6) 769 #define SVM_EXIT_IO_SZ16 __BIT(5) 770 #define SVM_EXIT_IO_SZ8 __BIT(4) 771 #define SVM_EXIT_IO_REP __BIT(3) 772 #define SVM_EXIT_IO_STR __BIT(2) 773 #define SVM_EXIT_IO_IN __BIT(0) 774 775 static const int seg_to_nvmm[] = { 776 [0] = NVMM_X64_SEG_ES, 777 [1] = NVMM_X64_SEG_CS, 778 [2] = NVMM_X64_SEG_SS, 779 [3] = NVMM_X64_SEG_DS, 780 [4] = NVMM_X64_SEG_FS, 781 [5] = NVMM_X64_SEG_GS 782 }; 783 784 static void 785 svm_exit_io(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 786 struct nvmm_exit *exit) 787 { 788 struct svm_cpudata *cpudata = vcpu->cpudata; 789 uint64_t info = cpudata->vmcb->ctrl.exitinfo1; 790 uint64_t nextpc = cpudata->vmcb->ctrl.exitinfo2; 791 792 exit->reason = NVMM_EXIT_IO; 793 794 if (info & SVM_EXIT_IO_IN) { 795 exit->u.io.type = NVMM_EXIT_IO_IN; 796 } else { 797 exit->u.io.type = NVMM_EXIT_IO_OUT; 798 } 799 800 exit->u.io.port = __SHIFTOUT(info, SVM_EXIT_IO_PORT); 801 802 if (svm_decode_assist) { 803 KASSERT(__SHIFTOUT(info, SVM_EXIT_IO_SEG) < 6); 804 exit->u.io.seg = seg_to_nvmm[__SHIFTOUT(info, SVM_EXIT_IO_SEG)]; 805 } else { 806 exit->u.io.seg = -1; 807 } 808 809 if (info & SVM_EXIT_IO_A64) { 810 exit->u.io.address_size = 8; 811 } else if (info & SVM_EXIT_IO_A32) { 812 exit->u.io.address_size = 4; 813 } else if (info & SVM_EXIT_IO_A16) { 814 exit->u.io.address_size = 2; 815 } 816 817 if (info & SVM_EXIT_IO_SZ32) { 818 exit->u.io.operand_size = 4; 819 } else if (info & SVM_EXIT_IO_SZ16) { 820 exit->u.io.operand_size = 2; 821 } else if (info & SVM_EXIT_IO_SZ8) { 822 exit->u.io.operand_size = 1; 823 } 824 825 exit->u.io.rep = (info & SVM_EXIT_IO_REP) != 0; 826 exit->u.io.str = (info & SVM_EXIT_IO_STR) != 0; 827 exit->u.io.npc = nextpc; 828 } 829 830 static bool 831 svm_inkernel_handle_msr(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 832 struct nvmm_exit *exit) 833 { 834 struct svm_cpudata *cpudata = vcpu->cpudata; 835 struct nvmm_x64_state *state = &cpudata->state; 836 uint64_t pat; 837 838 switch (exit->u.msr.type) { 839 case NVMM_EXIT_MSR_RDMSR: 840 if (exit->u.msr.msr == MSR_CR_PAT) { 841 pat = cpudata->vmcb->state.g_pat; 842 cpudata->vmcb->state.rax = (pat & 0xFFFFFFFF); 843 state->gprs[NVMM_X64_GPR_RDX] = (pat >> 32); 844 goto handled; 845 } 846 break; 847 case NVMM_EXIT_MSR_WRMSR: 848 if (exit->u.msr.msr == MSR_EFER) { 849 if (__predict_false(exit->u.msr.val & ~EFER_VALID)) { 850 svm_inject_gp(mach, vcpu); 851 goto handled; 852 } 853 if ((cpudata->vmcb->state.efer ^ exit->u.msr.val) & 854 EFER_TLB_FLUSH) { 855 cpudata->tlb_want_flush = true; 856 } 857 cpudata->vmcb->state.efer = exit->u.msr.val | EFER_SVME; 858 goto handled; 859 } 860 if (exit->u.msr.msr == MSR_CR_PAT) { 861 cpudata->vmcb->state.g_pat = exit->u.msr.val; 862 goto handled; 863 } 864 break; 865 } 866 867 return false; 868 869 handled: 870 cpudata->vmcb->state.rip = cpudata->vmcb->ctrl.nrip; 871 return true; 872 } 873 874 static void 875 svm_exit_msr(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 876 struct nvmm_exit *exit) 877 { 878 struct svm_cpudata *cpudata = vcpu->cpudata; 879 struct nvmm_x64_state *state = &cpudata->state; 880 uint64_t info = cpudata->vmcb->ctrl.exitinfo1; 881 882 if (info == 0) { 883 exit->u.msr.type = NVMM_EXIT_MSR_RDMSR; 884 } else { 885 exit->u.msr.type = NVMM_EXIT_MSR_WRMSR; 886 } 887 888 exit->u.msr.msr = state->gprs[NVMM_X64_GPR_RCX]; 889 890 if (info == 1) { 891 uint64_t rdx, rax; 892 rdx = state->gprs[NVMM_X64_GPR_RDX]; 893 rax = cpudata->vmcb->state.rax; 894 exit->u.msr.val = (rdx << 32) | (rax & 0xFFFFFFFF); 895 } else { 896 exit->u.msr.val = 0; 897 } 898 899 if (svm_inkernel_handle_msr(mach, vcpu, exit)) { 900 exit->reason = NVMM_EXIT_NONE; 901 return; 902 } 903 904 exit->reason = NVMM_EXIT_MSR; 905 exit->u.msr.npc = cpudata->vmcb->ctrl.nrip; 906 } 907 908 static void 909 svm_exit_npf(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 910 struct nvmm_exit *exit) 911 { 912 struct svm_cpudata *cpudata = vcpu->cpudata; 913 gpaddr_t gpa = cpudata->vmcb->ctrl.exitinfo2; 914 int error; 915 916 error = uvm_fault(&mach->vm->vm_map, gpa, VM_PROT_ALL); 917 918 if (error) { 919 exit->reason = NVMM_EXIT_MEMORY; 920 if (cpudata->vmcb->ctrl.exitinfo1 & PGEX_W) 921 exit->u.mem.perm = NVMM_EXIT_MEMORY_WRITE; 922 else if (cpudata->vmcb->ctrl.exitinfo1 & PGEX_X) 923 exit->u.mem.perm = NVMM_EXIT_MEMORY_EXEC; 924 else 925 exit->u.mem.perm = NVMM_EXIT_MEMORY_READ; 926 exit->u.mem.gpa = gpa; 927 exit->u.mem.inst_len = cpudata->vmcb->ctrl.inst_len; 928 memcpy(exit->u.mem.inst_bytes, cpudata->vmcb->ctrl.inst_bytes, 929 sizeof(exit->u.mem.inst_bytes)); 930 exit->u.mem.npc = cpudata->vmcb->ctrl.nrip; 931 } else { 932 exit->reason = NVMM_EXIT_NONE; 933 } 934 } 935 936 static void 937 svm_exit_xsetbv(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 938 struct nvmm_exit *exit) 939 { 940 struct svm_cpudata *cpudata = vcpu->cpudata; 941 struct nvmm_x64_state *state = &cpudata->state; 942 struct vmcb *vmcb = cpudata->vmcb; 943 uint64_t val; 944 945 exit->reason = NVMM_EXIT_NONE; 946 947 val = (state->gprs[NVMM_X64_GPR_RDX] << 32) | 948 (vmcb->state.rax & 0xFFFFFFFF); 949 950 if (__predict_false(state->gprs[NVMM_X64_GPR_RCX] != 0)) { 951 goto error; 952 } else if (__predict_false(vmcb->state.cpl != 0)) { 953 goto error; 954 } else if (__predict_false((val & ~svm_xcr0_mask) != 0)) { 955 goto error; 956 } else if (__predict_false((val & XCR0_X87) == 0)) { 957 goto error; 958 } 959 960 state->crs[NVMM_X64_CR_XCR0] = val; 961 962 cpudata->vmcb->state.rip = cpudata->vmcb->ctrl.nrip; 963 return; 964 965 error: 966 svm_inject_gp(mach, vcpu); 967 } 968 969 static void 970 svm_vmcb_cache_default(struct vmcb *vmcb) 971 { 972 vmcb->ctrl.vmcb_clean = 973 VMCB_CTRL_VMCB_CLEAN_I | 974 VMCB_CTRL_VMCB_CLEAN_IOPM | 975 VMCB_CTRL_VMCB_CLEAN_ASID | 976 VMCB_CTRL_VMCB_CLEAN_LBR | 977 VMCB_CTRL_VMCB_CLEAN_AVIC; 978 } 979 980 static void 981 svm_vmcb_cache_flush(struct vmcb *vmcb) 982 { 983 vmcb->ctrl.vmcb_clean = 0; 984 } 985 986 static void 987 svm_vcpu_guest_fpu_enter(struct nvmm_cpu *vcpu) 988 { 989 struct svm_cpudata *cpudata = vcpu->cpudata; 990 991 if (x86_xsave_features != 0) { 992 cpudata->xcr0 = rdxcr(0); 993 wrxcr(0, cpudata->state.crs[NVMM_X64_CR_XCR0]); 994 } 995 996 cpudata->ts_set = (rcr0() & CR0_TS) != 0; 997 998 fpu_area_save(&cpudata->hfpu); 999 fpu_area_restore(&cpudata->gfpu); 1000 } 1001 1002 static void 1003 svm_vcpu_guest_fpu_leave(struct nvmm_cpu *vcpu) 1004 { 1005 struct svm_cpudata *cpudata = vcpu->cpudata; 1006 1007 fpu_area_save(&cpudata->gfpu); 1008 fpu_area_restore(&cpudata->hfpu); 1009 1010 if (cpudata->ts_set) { 1011 stts(); 1012 } 1013 1014 if (x86_xsave_features != 0) { 1015 cpudata->state.crs[NVMM_X64_CR_XCR0] = rdxcr(0); 1016 wrxcr(0, cpudata->xcr0); 1017 } 1018 } 1019 1020 static void 1021 svm_vcpu_guest_dbregs_enter(struct nvmm_cpu *vcpu) 1022 { 1023 struct svm_cpudata *cpudata = vcpu->cpudata; 1024 struct nvmm_x64_state *state = &cpudata->state; 1025 1026 x86_dbregs_save(curlwp); 1027 1028 ldr0(state->drs[NVMM_X64_DR_DR0]); 1029 ldr1(state->drs[NVMM_X64_DR_DR1]); 1030 ldr2(state->drs[NVMM_X64_DR_DR2]); 1031 ldr3(state->drs[NVMM_X64_DR_DR3]); 1032 } 1033 1034 static void 1035 svm_vcpu_guest_dbregs_leave(struct nvmm_cpu *vcpu) 1036 { 1037 struct svm_cpudata *cpudata = vcpu->cpudata; 1038 struct nvmm_x64_state *state = &cpudata->state; 1039 1040 state->drs[NVMM_X64_DR_DR0] = rdr0(); 1041 state->drs[NVMM_X64_DR_DR1] = rdr1(); 1042 state->drs[NVMM_X64_DR_DR2] = rdr2(); 1043 state->drs[NVMM_X64_DR_DR3] = rdr3(); 1044 1045 x86_dbregs_restore(curlwp); 1046 } 1047 1048 static void 1049 svm_vcpu_guest_misc_enter(struct nvmm_cpu *vcpu) 1050 { 1051 struct svm_cpudata *cpudata = vcpu->cpudata; 1052 1053 /* Save the fixed Host MSRs. */ 1054 cpudata->star = rdmsr(MSR_STAR); 1055 cpudata->lstar = rdmsr(MSR_LSTAR); 1056 cpudata->cstar = rdmsr(MSR_CSTAR); 1057 cpudata->sfmask = rdmsr(MSR_SFMASK); 1058 1059 /* Save the Host CR2. */ 1060 cpudata->cr2 = rcr2(); 1061 } 1062 1063 static void 1064 svm_vcpu_guest_misc_leave(struct nvmm_cpu *vcpu) 1065 { 1066 struct svm_cpudata *cpudata = vcpu->cpudata; 1067 1068 /* Restore the fixed Host MSRs. */ 1069 wrmsr(MSR_STAR, cpudata->star); 1070 wrmsr(MSR_LSTAR, cpudata->lstar); 1071 wrmsr(MSR_CSTAR, cpudata->cstar); 1072 wrmsr(MSR_SFMASK, cpudata->sfmask); 1073 1074 /* Restore the Host CR2. */ 1075 lcr2(cpudata->cr2); 1076 } 1077 1078 static int 1079 svm_vcpu_run(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1080 struct nvmm_exit *exit) 1081 { 1082 struct svm_cpudata *cpudata = vcpu->cpudata; 1083 struct vmcb *vmcb = cpudata->vmcb; 1084 bool tlb_need_flush = false; 1085 int hcpu, s; 1086 1087 kpreempt_disable(); 1088 hcpu = cpu_number(); 1089 1090 if (vcpu->hcpu_last != hcpu || cpudata->shared_asid) { 1091 tlb_need_flush = true; 1092 } 1093 1094 if (cpudata->tlb_want_flush || tlb_need_flush) { 1095 vmcb->ctrl.tlb_ctrl = svm_ctrl_tlb_flush; 1096 } else { 1097 vmcb->ctrl.tlb_ctrl = 0; 1098 } 1099 1100 if (vcpu->hcpu_last != hcpu) { 1101 vmcb->ctrl.tsc_offset = cpudata->tsc_offset + 1102 curcpu()->ci_data.cpu_cc_skew; 1103 svm_vmcb_cache_flush(vmcb); 1104 } 1105 1106 svm_vcpu_guest_dbregs_enter(vcpu); 1107 svm_vcpu_guest_misc_enter(vcpu); 1108 1109 while (1) { 1110 s = splhigh(); 1111 svm_vcpu_guest_fpu_enter(vcpu); 1112 svm_vmrun(cpudata->vmcb_pa, cpudata->state.gprs); 1113 svm_vcpu_guest_fpu_leave(vcpu); 1114 splx(s); 1115 1116 svm_vmcb_cache_default(vmcb); 1117 1118 if (vmcb->ctrl.exitcode != VMCB_EXITCODE_INVALID) { 1119 if (cpudata->tlb_want_flush) { 1120 cpudata->tlb_want_flush = false; 1121 } 1122 vcpu->hcpu_last = hcpu; 1123 } 1124 1125 switch (vmcb->ctrl.exitcode) { 1126 case VMCB_EXITCODE_INTR: 1127 case VMCB_EXITCODE_NMI: 1128 exit->reason = NVMM_EXIT_NONE; 1129 break; 1130 case VMCB_EXITCODE_VINTR: 1131 svm_event_waitexit_disable(vmcb, false); 1132 exit->reason = NVMM_EXIT_INT_READY; 1133 break; 1134 case VMCB_EXITCODE_IRET: 1135 svm_event_waitexit_disable(vmcb, true); 1136 cpudata->in_nmi = false; 1137 exit->reason = NVMM_EXIT_NMI_READY; 1138 break; 1139 case VMCB_EXITCODE_CPUID: 1140 svm_exit_cpuid(mach, vcpu, exit); 1141 break; 1142 case VMCB_EXITCODE_HLT: 1143 exit->reason = NVMM_EXIT_HLT; 1144 break; 1145 case VMCB_EXITCODE_IOIO: 1146 svm_exit_io(mach, vcpu, exit); 1147 break; 1148 case VMCB_EXITCODE_MSR: 1149 svm_exit_msr(mach, vcpu, exit); 1150 break; 1151 case VMCB_EXITCODE_SHUTDOWN: 1152 exit->reason = NVMM_EXIT_SHUTDOWN; 1153 break; 1154 case VMCB_EXITCODE_RDPMC: 1155 case VMCB_EXITCODE_RSM: 1156 case VMCB_EXITCODE_INVLPGA: 1157 case VMCB_EXITCODE_VMRUN: 1158 case VMCB_EXITCODE_VMMCALL: 1159 case VMCB_EXITCODE_VMLOAD: 1160 case VMCB_EXITCODE_VMSAVE: 1161 case VMCB_EXITCODE_STGI: 1162 case VMCB_EXITCODE_CLGI: 1163 case VMCB_EXITCODE_SKINIT: 1164 case VMCB_EXITCODE_RDTSCP: 1165 svm_inject_ud(mach, vcpu); 1166 exit->reason = NVMM_EXIT_NONE; 1167 break; 1168 case VMCB_EXITCODE_MONITOR: 1169 exit->reason = NVMM_EXIT_MONITOR; 1170 break; 1171 case VMCB_EXITCODE_MWAIT: 1172 exit->reason = NVMM_EXIT_MWAIT; 1173 break; 1174 case VMCB_EXITCODE_MWAIT_CONDITIONAL: 1175 exit->reason = NVMM_EXIT_MWAIT_COND; 1176 break; 1177 case VMCB_EXITCODE_XSETBV: 1178 svm_exit_xsetbv(mach, vcpu, exit); 1179 break; 1180 case VMCB_EXITCODE_NPF: 1181 svm_exit_npf(mach, vcpu, exit); 1182 break; 1183 case VMCB_EXITCODE_FERR_FREEZE: /* ? */ 1184 default: 1185 exit->reason = NVMM_EXIT_INVALID; 1186 break; 1187 } 1188 1189 /* If no reason to return to userland, keep rolling. */ 1190 if (curcpu()->ci_schedstate.spc_flags & SPCF_SHOULDYIELD) { 1191 break; 1192 } 1193 if (exit->reason != NVMM_EXIT_NONE) { 1194 break; 1195 } 1196 } 1197 1198 svm_vcpu_guest_misc_leave(vcpu); 1199 svm_vcpu_guest_dbregs_leave(vcpu); 1200 1201 kpreempt_enable(); 1202 1203 exit->exitstate[NVMM_X64_EXITSTATE_CR8] = __SHIFTOUT(vmcb->ctrl.v, 1204 VMCB_CTRL_V_TPR); 1205 exit->exitstate[NVMM_X64_EXITSTATE_RFLAGS] = vmcb->state.rflags; 1206 1207 return 0; 1208 } 1209 1210 /* -------------------------------------------------------------------------- */ 1211 1212 static int 1213 svm_memalloc(paddr_t *pa, vaddr_t *va, size_t npages) 1214 { 1215 struct pglist pglist; 1216 paddr_t _pa; 1217 vaddr_t _va; 1218 size_t i; 1219 int ret; 1220 1221 ret = uvm_pglistalloc(npages * PAGE_SIZE, 0, ~0UL, PAGE_SIZE, 0, 1222 &pglist, 1, 0); 1223 if (ret != 0) 1224 return ENOMEM; 1225 _pa = TAILQ_FIRST(&pglist)->phys_addr; 1226 _va = uvm_km_alloc(kernel_map, npages * PAGE_SIZE, 0, 1227 UVM_KMF_VAONLY | UVM_KMF_NOWAIT); 1228 if (_va == 0) 1229 goto error; 1230 1231 for (i = 0; i < npages; i++) { 1232 pmap_kenter_pa(_va + i * PAGE_SIZE, _pa + i * PAGE_SIZE, 1233 VM_PROT_READ | VM_PROT_WRITE, PMAP_WRITE_BACK); 1234 } 1235 pmap_update(pmap_kernel()); 1236 1237 memset((void *)_va, 0, npages * PAGE_SIZE); 1238 1239 *pa = _pa; 1240 *va = _va; 1241 return 0; 1242 1243 error: 1244 for (i = 0; i < npages; i++) { 1245 uvm_pagefree(PHYS_TO_VM_PAGE(_pa + i * PAGE_SIZE)); 1246 } 1247 return ENOMEM; 1248 } 1249 1250 static void 1251 svm_memfree(paddr_t pa, vaddr_t va, size_t npages) 1252 { 1253 size_t i; 1254 1255 pmap_kremove(va, npages * PAGE_SIZE); 1256 pmap_update(pmap_kernel()); 1257 uvm_km_free(kernel_map, va, npages * PAGE_SIZE, UVM_KMF_VAONLY); 1258 for (i = 0; i < npages; i++) { 1259 uvm_pagefree(PHYS_TO_VM_PAGE(pa + i * PAGE_SIZE)); 1260 } 1261 } 1262 1263 /* -------------------------------------------------------------------------- */ 1264 1265 #define SVM_MSRBM_READ __BIT(0) 1266 #define SVM_MSRBM_WRITE __BIT(1) 1267 1268 static void 1269 svm_vcpu_msr_allow(uint8_t *bitmap, uint64_t msr, bool read, bool write) 1270 { 1271 uint64_t byte; 1272 uint8_t bitoff; 1273 1274 if (msr < 0x00002000) { 1275 /* Range 1 */ 1276 byte = ((msr - 0x00000000) >> 2UL) + 0x0000; 1277 } else if (msr >= 0xC0000000 && msr < 0xC0002000) { 1278 /* Range 2 */ 1279 byte = ((msr - 0xC0000000) >> 2UL) + 0x0800; 1280 } else if (msr >= 0xC0010000 && msr < 0xC0012000) { 1281 /* Range 3 */ 1282 byte = ((msr - 0xC0010000) >> 2UL) + 0x1000; 1283 } else { 1284 panic("%s: wrong range", __func__); 1285 } 1286 1287 bitoff = (msr & 0x3) << 1; 1288 1289 if (read) { 1290 bitmap[byte] &= ~(SVM_MSRBM_READ << bitoff); 1291 } 1292 if (write) { 1293 bitmap[byte] &= ~(SVM_MSRBM_WRITE << bitoff); 1294 } 1295 } 1296 1297 static void 1298 svm_asid_alloc(struct nvmm_cpu *vcpu) 1299 { 1300 struct svm_cpudata *cpudata = vcpu->cpudata; 1301 struct vmcb *vmcb = cpudata->vmcb; 1302 size_t i, oct, bit; 1303 1304 mutex_enter(&svm_asidlock); 1305 1306 for (i = 0; i < svm_maxasid; i++) { 1307 oct = i / 8; 1308 bit = i % 8; 1309 1310 if (svm_asidmap[oct] & __BIT(bit)) { 1311 continue; 1312 } 1313 1314 svm_asidmap[oct] |= __BIT(bit); 1315 vmcb->ctrl.guest_asid = i; 1316 mutex_exit(&svm_asidlock); 1317 return; 1318 } 1319 1320 /* 1321 * No free ASID. Use the last one, which is shared and requires 1322 * special TLB handling. 1323 */ 1324 cpudata->shared_asid = true; 1325 vmcb->ctrl.guest_asid = svm_maxasid - 1; 1326 mutex_exit(&svm_asidlock); 1327 } 1328 1329 static void 1330 svm_asid_free(struct nvmm_cpu *vcpu) 1331 { 1332 struct svm_cpudata *cpudata = vcpu->cpudata; 1333 struct vmcb *vmcb = cpudata->vmcb; 1334 size_t oct, bit; 1335 1336 if (cpudata->shared_asid) { 1337 return; 1338 } 1339 1340 oct = vmcb->ctrl.guest_asid / 8; 1341 bit = vmcb->ctrl.guest_asid % 8; 1342 1343 mutex_enter(&svm_asidlock); 1344 svm_asidmap[oct] &= ~__BIT(bit); 1345 mutex_exit(&svm_asidlock); 1346 } 1347 1348 static void 1349 svm_vcpu_init(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 1350 { 1351 struct svm_cpudata *cpudata = vcpu->cpudata; 1352 struct vmcb *vmcb = cpudata->vmcb; 1353 1354 /* Allow reads/writes of Control Registers. */ 1355 vmcb->ctrl.intercept_cr = 0; 1356 1357 /* Allow reads/writes of Debug Registers. */ 1358 vmcb->ctrl.intercept_dr = 0; 1359 1360 /* Allow exceptions 0 to 31. */ 1361 vmcb->ctrl.intercept_vec = 0; 1362 1363 /* 1364 * Allow: 1365 * - SMI [smm interrupts] 1366 * - VINTR [virtual interrupts] 1367 * - CR0_SPEC [CR0 writes changing other fields than CR0.TS or CR0.MP] 1368 * - RIDTR [reads of IDTR] 1369 * - RGDTR [reads of GDTR] 1370 * - RLDTR [reads of LDTR] 1371 * - RTR [reads of TR] 1372 * - WIDTR [writes of IDTR] 1373 * - WGDTR [writes of GDTR] 1374 * - WLDTR [writes of LDTR] 1375 * - WTR [writes of TR] 1376 * - RDTSC [rdtsc instruction] 1377 * - PUSHF [pushf instruction] 1378 * - POPF [popf instruction] 1379 * - IRET [iret instruction] 1380 * - INTN [int $n instructions] 1381 * - INVD [invd instruction] 1382 * - PAUSE [pause instruction] 1383 * - INVLPG [invplg instruction] 1384 * - TASKSW [task switches] 1385 * 1386 * Intercept the rest below. 1387 */ 1388 vmcb->ctrl.intercept_misc1 = 1389 VMCB_CTRL_INTERCEPT_INTR | 1390 VMCB_CTRL_INTERCEPT_NMI | 1391 VMCB_CTRL_INTERCEPT_INIT | 1392 VMCB_CTRL_INTERCEPT_RDPMC | 1393 VMCB_CTRL_INTERCEPT_CPUID | 1394 VMCB_CTRL_INTERCEPT_RSM | 1395 VMCB_CTRL_INTERCEPT_HLT | 1396 VMCB_CTRL_INTERCEPT_INVLPGA | 1397 VMCB_CTRL_INTERCEPT_IOIO_PROT | 1398 VMCB_CTRL_INTERCEPT_MSR_PROT | 1399 VMCB_CTRL_INTERCEPT_FERR_FREEZE | 1400 VMCB_CTRL_INTERCEPT_SHUTDOWN; 1401 1402 /* 1403 * Allow: 1404 * - ICEBP [icebp instruction] 1405 * - WBINVD [wbinvd instruction] 1406 * - WCR_SPEC(0..15) [writes of CR0-15, received after instruction] 1407 * 1408 * Intercept the rest below. 1409 */ 1410 vmcb->ctrl.intercept_misc2 = 1411 VMCB_CTRL_INTERCEPT_VMRUN | 1412 VMCB_CTRL_INTERCEPT_VMMCALL | 1413 VMCB_CTRL_INTERCEPT_VMLOAD | 1414 VMCB_CTRL_INTERCEPT_VMSAVE | 1415 VMCB_CTRL_INTERCEPT_STGI | 1416 VMCB_CTRL_INTERCEPT_CLGI | 1417 VMCB_CTRL_INTERCEPT_SKINIT | 1418 VMCB_CTRL_INTERCEPT_RDTSCP | 1419 VMCB_CTRL_INTERCEPT_MONITOR | 1420 VMCB_CTRL_INTERCEPT_MWAIT | 1421 VMCB_CTRL_INTERCEPT_XSETBV; 1422 1423 /* Intercept all I/O accesses. */ 1424 memset(cpudata->iobm, 0xFF, IOBM_SIZE); 1425 vmcb->ctrl.iopm_base_pa = cpudata->iobm_pa; 1426 1427 /* 1428 * Allow: 1429 * - EFER [read] 1430 * - STAR [read, write] 1431 * - LSTAR [read, write] 1432 * - CSTAR [read, write] 1433 * - SFMASK [read, write] 1434 * - KERNELGSBASE [read, write] 1435 * - SYSENTER_CS [read, write] 1436 * - SYSENTER_ESP [read, write] 1437 * - SYSENTER_EIP [read, write] 1438 * - FSBASE [read, write] 1439 * - GSBASE [read, write] 1440 * 1441 * Intercept the rest. 1442 */ 1443 memset(cpudata->msrbm, 0xFF, MSRBM_SIZE); 1444 svm_vcpu_msr_allow(cpudata->msrbm, MSR_EFER, true, false); 1445 svm_vcpu_msr_allow(cpudata->msrbm, MSR_STAR, true, true); 1446 svm_vcpu_msr_allow(cpudata->msrbm, MSR_LSTAR, true, true); 1447 svm_vcpu_msr_allow(cpudata->msrbm, MSR_CSTAR, true, true); 1448 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SFMASK, true, true); 1449 svm_vcpu_msr_allow(cpudata->msrbm, MSR_KERNELGSBASE, true, true); 1450 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_CS, true, true); 1451 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_ESP, true, true); 1452 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_EIP, true, true); 1453 svm_vcpu_msr_allow(cpudata->msrbm, MSR_FSBASE, true, true); 1454 svm_vcpu_msr_allow(cpudata->msrbm, MSR_GSBASE, true, true); 1455 vmcb->ctrl.msrpm_base_pa = cpudata->msrbm_pa; 1456 1457 /* Generate ASID. */ 1458 svm_asid_alloc(vcpu); 1459 1460 /* Virtual TPR. */ 1461 vmcb->ctrl.v = VMCB_CTRL_V_INTR_MASKING; 1462 1463 /* Enable Nested Paging. */ 1464 vmcb->ctrl.enable1 = VMCB_CTRL_ENABLE_NP; 1465 vmcb->ctrl.n_cr3 = mach->vm->vm_map.pmap->pm_pdirpa[0]; 1466 1467 /* Must always be set. */ 1468 vmcb->state.efer = EFER_SVME; 1469 1470 /* Init XSAVE header. */ 1471 cpudata->gfpu.xsh_xstate_bv = svm_xcr0_mask; 1472 cpudata->gfpu.xsh_xcomp_bv = 0; 1473 1474 /* Bluntly hide the host TSC. */ 1475 cpudata->tsc_offset = rdtsc(); 1476 } 1477 1478 static int 1479 svm_vcpu_create(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 1480 { 1481 struct svm_cpudata *cpudata; 1482 int error; 1483 1484 /* Allocate the SVM cpudata. */ 1485 cpudata = (struct svm_cpudata *)uvm_km_alloc(kernel_map, 1486 roundup(sizeof(*cpudata), PAGE_SIZE), 0, 1487 UVM_KMF_WIRED|UVM_KMF_ZERO); 1488 vcpu->cpudata = cpudata; 1489 1490 /* VMCB */ 1491 error = svm_memalloc(&cpudata->vmcb_pa, (vaddr_t *)&cpudata->vmcb, 1492 VMCB_NPAGES); 1493 if (error) 1494 goto error; 1495 1496 /* I/O Bitmap */ 1497 error = svm_memalloc(&cpudata->iobm_pa, (vaddr_t *)&cpudata->iobm, 1498 IOBM_NPAGES); 1499 if (error) 1500 goto error; 1501 1502 /* MSR Bitmap */ 1503 error = svm_memalloc(&cpudata->msrbm_pa, (vaddr_t *)&cpudata->msrbm, 1504 MSRBM_NPAGES); 1505 if (error) 1506 goto error; 1507 1508 /* Init the VCPU info. */ 1509 svm_vcpu_init(mach, vcpu); 1510 1511 return 0; 1512 1513 error: 1514 if (cpudata->vmcb_pa) { 1515 svm_memfree(cpudata->vmcb_pa, (vaddr_t)cpudata->vmcb, 1516 VMCB_NPAGES); 1517 } 1518 if (cpudata->iobm_pa) { 1519 svm_memfree(cpudata->iobm_pa, (vaddr_t)cpudata->iobm, 1520 IOBM_NPAGES); 1521 } 1522 if (cpudata->msrbm_pa) { 1523 svm_memfree(cpudata->msrbm_pa, (vaddr_t)cpudata->msrbm, 1524 MSRBM_NPAGES); 1525 } 1526 uvm_km_free(kernel_map, (vaddr_t)cpudata, 1527 roundup(sizeof(*cpudata), PAGE_SIZE), UVM_KMF_WIRED); 1528 return error; 1529 } 1530 1531 static void 1532 svm_vcpu_destroy(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 1533 { 1534 struct svm_cpudata *cpudata = vcpu->cpudata; 1535 1536 svm_asid_free(vcpu); 1537 1538 svm_memfree(cpudata->vmcb_pa, (vaddr_t)cpudata->vmcb, VMCB_NPAGES); 1539 svm_memfree(cpudata->iobm_pa, (vaddr_t)cpudata->iobm, IOBM_NPAGES); 1540 svm_memfree(cpudata->msrbm_pa, (vaddr_t)cpudata->msrbm, MSRBM_NPAGES); 1541 1542 uvm_km_free(kernel_map, (vaddr_t)cpudata, 1543 roundup(sizeof(*cpudata), PAGE_SIZE), UVM_KMF_WIRED); 1544 } 1545 1546 #define SVM_SEG_ATTRIB_TYPE __BITS(4,0) 1547 #define SVM_SEG_ATTRIB_DPL __BITS(6,5) 1548 #define SVM_SEG_ATTRIB_P __BIT(7) 1549 #define SVM_SEG_ATTRIB_AVL __BIT(8) 1550 #define SVM_SEG_ATTRIB_LONG __BIT(9) 1551 #define SVM_SEG_ATTRIB_DEF32 __BIT(10) 1552 #define SVM_SEG_ATTRIB_GRAN __BIT(11) 1553 1554 static void 1555 svm_vcpu_setstate_seg(struct nvmm_x64_state_seg *seg, struct vmcb_segment *vseg) 1556 { 1557 vseg->selector = seg->selector; 1558 vseg->attrib = 1559 __SHIFTIN(seg->attrib.type, SVM_SEG_ATTRIB_TYPE) | 1560 __SHIFTIN(seg->attrib.dpl, SVM_SEG_ATTRIB_DPL) | 1561 __SHIFTIN(seg->attrib.p, SVM_SEG_ATTRIB_P) | 1562 __SHIFTIN(seg->attrib.avl, SVM_SEG_ATTRIB_AVL) | 1563 __SHIFTIN(seg->attrib.lng, SVM_SEG_ATTRIB_LONG) | 1564 __SHIFTIN(seg->attrib.def32, SVM_SEG_ATTRIB_DEF32) | 1565 __SHIFTIN(seg->attrib.gran, SVM_SEG_ATTRIB_GRAN); 1566 vseg->limit = seg->limit; 1567 vseg->base = seg->base; 1568 } 1569 1570 static void 1571 svm_vcpu_getstate_seg(struct nvmm_x64_state_seg *seg, struct vmcb_segment *vseg) 1572 { 1573 seg->selector = vseg->selector; 1574 seg->attrib.type = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_TYPE); 1575 seg->attrib.dpl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DPL); 1576 seg->attrib.p = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_P); 1577 seg->attrib.avl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_AVL); 1578 seg->attrib.lng = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_LONG); 1579 seg->attrib.def32 = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DEF32); 1580 seg->attrib.gran = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_GRAN); 1581 seg->limit = vseg->limit; 1582 seg->base = vseg->base; 1583 } 1584 1585 static bool 1586 svm_state_tlb_flush(struct nvmm_x64_state *cstate, 1587 struct nvmm_x64_state *nstate, uint64_t flags) 1588 { 1589 if (flags & NVMM_X64_STATE_CRS) { 1590 if ((cstate->crs[NVMM_X64_CR_CR0] ^ 1591 nstate->crs[NVMM_X64_CR_CR0]) & CR0_TLB_FLUSH) { 1592 return true; 1593 } 1594 if (cstate->crs[NVMM_X64_CR_CR3] != 1595 nstate->crs[NVMM_X64_CR_CR3]) { 1596 return true; 1597 } 1598 if ((cstate->crs[NVMM_X64_CR_CR4] ^ 1599 nstate->crs[NVMM_X64_CR_CR4]) & CR4_TLB_FLUSH) { 1600 return true; 1601 } 1602 } 1603 1604 if (flags & NVMM_X64_STATE_MSRS) { 1605 if ((cstate->msrs[NVMM_X64_MSR_EFER] ^ 1606 nstate->msrs[NVMM_X64_MSR_EFER]) & EFER_TLB_FLUSH) { 1607 return true; 1608 } 1609 } 1610 1611 return false; 1612 } 1613 1614 static void 1615 svm_vcpu_setstate(struct nvmm_cpu *vcpu, void *data, uint64_t flags) 1616 { 1617 struct svm_cpudata *cpudata = vcpu->cpudata; 1618 struct nvmm_x64_state *cstate = &cpudata->state; 1619 struct nvmm_x64_state *nstate = (struct nvmm_x64_state *)data; 1620 struct vmcb *vmcb = cpudata->vmcb; 1621 struct fxsave *fpustate; 1622 1623 if (svm_state_tlb_flush(cstate, nstate, flags)) { 1624 cpudata->tlb_want_flush = true; 1625 } 1626 1627 if (flags & NVMM_X64_STATE_SEGS) { 1628 memcpy(cstate->segs, nstate->segs, sizeof(nstate->segs)); 1629 1630 svm_vcpu_setstate_seg(&cstate->segs[NVMM_X64_SEG_CS], 1631 &vmcb->state.cs); 1632 svm_vcpu_setstate_seg(&cstate->segs[NVMM_X64_SEG_DS], 1633 &vmcb->state.ds); 1634 svm_vcpu_setstate_seg(&cstate->segs[NVMM_X64_SEG_ES], 1635 &vmcb->state.es); 1636 svm_vcpu_setstate_seg(&cstate->segs[NVMM_X64_SEG_FS], 1637 &vmcb->state.fs); 1638 svm_vcpu_setstate_seg(&cstate->segs[NVMM_X64_SEG_GS], 1639 &vmcb->state.gs); 1640 svm_vcpu_setstate_seg(&cstate->segs[NVMM_X64_SEG_SS], 1641 &vmcb->state.ss); 1642 svm_vcpu_setstate_seg(&cstate->segs[NVMM_X64_SEG_GDT], 1643 &vmcb->state.gdt); 1644 svm_vcpu_setstate_seg(&cstate->segs[NVMM_X64_SEG_IDT], 1645 &vmcb->state.idt); 1646 svm_vcpu_setstate_seg(&cstate->segs[NVMM_X64_SEG_LDT], 1647 &vmcb->state.ldt); 1648 svm_vcpu_setstate_seg(&cstate->segs[NVMM_X64_SEG_TR], 1649 &vmcb->state.tr); 1650 } 1651 1652 if (flags & NVMM_X64_STATE_GPRS) { 1653 memcpy(cstate->gprs, nstate->gprs, sizeof(nstate->gprs)); 1654 1655 vmcb->state.rip = cstate->gprs[NVMM_X64_GPR_RIP]; 1656 vmcb->state.rsp = cstate->gprs[NVMM_X64_GPR_RSP]; 1657 vmcb->state.rax = cstate->gprs[NVMM_X64_GPR_RAX]; 1658 vmcb->state.rflags = cstate->gprs[NVMM_X64_GPR_RFLAGS]; 1659 } 1660 1661 if (flags & NVMM_X64_STATE_CRS) { 1662 memcpy(cstate->crs, nstate->crs, sizeof(nstate->crs)); 1663 1664 vmcb->state.cr0 = cstate->crs[NVMM_X64_CR_CR0]; 1665 vmcb->state.cr2 = cstate->crs[NVMM_X64_CR_CR2]; 1666 vmcb->state.cr3 = cstate->crs[NVMM_X64_CR_CR3]; 1667 vmcb->state.cr4 = cstate->crs[NVMM_X64_CR_CR4]; 1668 1669 vmcb->ctrl.v &= ~VMCB_CTRL_V_TPR; 1670 vmcb->ctrl.v |= __SHIFTIN(cstate->crs[NVMM_X64_CR_CR8], 1671 VMCB_CTRL_V_TPR); 1672 1673 /* Clear unsupported XCR0 bits, set mandatory X87 bit. */ 1674 if (svm_xcr0_mask != 0) { 1675 cstate->crs[NVMM_X64_CR_XCR0] &= svm_xcr0_mask; 1676 cstate->crs[NVMM_X64_CR_XCR0] |= XCR0_X87; 1677 } else { 1678 cstate->crs[NVMM_X64_CR_XCR0] = 0; 1679 } 1680 } 1681 1682 if (flags & NVMM_X64_STATE_DRS) { 1683 memcpy(cstate->drs, nstate->drs, sizeof(nstate->drs)); 1684 1685 vmcb->state.dr6 = cstate->drs[NVMM_X64_DR_DR6]; 1686 vmcb->state.dr7 = cstate->drs[NVMM_X64_DR_DR7]; 1687 } 1688 1689 if (flags & NVMM_X64_STATE_MSRS) { 1690 memcpy(cstate->msrs, nstate->msrs, sizeof(nstate->msrs)); 1691 1692 /* Bit EFER_SVME is mandatory. */ 1693 cstate->msrs[NVMM_X64_MSR_EFER] |= EFER_SVME; 1694 1695 vmcb->state.efer = cstate->msrs[NVMM_X64_MSR_EFER]; 1696 vmcb->state.star = cstate->msrs[NVMM_X64_MSR_STAR]; 1697 vmcb->state.lstar = cstate->msrs[NVMM_X64_MSR_LSTAR]; 1698 vmcb->state.cstar = cstate->msrs[NVMM_X64_MSR_CSTAR]; 1699 vmcb->state.sfmask = cstate->msrs[NVMM_X64_MSR_SFMASK]; 1700 vmcb->state.kernelgsbase = 1701 cstate->msrs[NVMM_X64_MSR_KERNELGSBASE]; 1702 vmcb->state.sysenter_cs = 1703 cstate->msrs[NVMM_X64_MSR_SYSENTER_CS]; 1704 vmcb->state.sysenter_esp = 1705 cstate->msrs[NVMM_X64_MSR_SYSENTER_ESP]; 1706 vmcb->state.sysenter_eip = 1707 cstate->msrs[NVMM_X64_MSR_SYSENTER_EIP]; 1708 vmcb->state.g_pat = cstate->msrs[NVMM_X64_MSR_PAT]; 1709 } 1710 1711 if (flags & NVMM_X64_STATE_MISC) { 1712 memcpy(cstate->misc, nstate->misc, sizeof(nstate->misc)); 1713 1714 vmcb->state.cpl = cstate->misc[NVMM_X64_MISC_CPL]; 1715 } 1716 1717 CTASSERT(sizeof(cpudata->gfpu.xsh_fxsave) == sizeof(cstate->fpu)); 1718 if (flags & NVMM_X64_STATE_FPU) { 1719 memcpy(&cstate->fpu, &nstate->fpu, sizeof(nstate->fpu)); 1720 1721 memcpy(cpudata->gfpu.xsh_fxsave, &cstate->fpu, 1722 sizeof(cstate->fpu)); 1723 1724 fpustate = (struct fxsave *)cpudata->gfpu.xsh_fxsave; 1725 fpustate->fx_mxcsr_mask &= x86_fpu_mxcsr_mask; 1726 fpustate->fx_mxcsr &= fpustate->fx_mxcsr_mask; 1727 } 1728 } 1729 1730 static void 1731 svm_vcpu_getstate(struct nvmm_cpu *vcpu, void *data, uint64_t flags) 1732 { 1733 struct svm_cpudata *cpudata = vcpu->cpudata; 1734 struct nvmm_x64_state *cstate = &cpudata->state; 1735 struct nvmm_x64_state *nstate = (struct nvmm_x64_state *)data; 1736 struct vmcb *vmcb = cpudata->vmcb; 1737 1738 if (flags & NVMM_X64_STATE_SEGS) { 1739 svm_vcpu_getstate_seg(&cstate->segs[NVMM_X64_SEG_CS], 1740 &vmcb->state.cs); 1741 svm_vcpu_getstate_seg(&cstate->segs[NVMM_X64_SEG_DS], 1742 &vmcb->state.ds); 1743 svm_vcpu_getstate_seg(&cstate->segs[NVMM_X64_SEG_ES], 1744 &vmcb->state.es); 1745 svm_vcpu_getstate_seg(&cstate->segs[NVMM_X64_SEG_FS], 1746 &vmcb->state.fs); 1747 svm_vcpu_getstate_seg(&cstate->segs[NVMM_X64_SEG_GS], 1748 &vmcb->state.gs); 1749 svm_vcpu_getstate_seg(&cstate->segs[NVMM_X64_SEG_SS], 1750 &vmcb->state.ss); 1751 svm_vcpu_getstate_seg(&cstate->segs[NVMM_X64_SEG_GDT], 1752 &vmcb->state.gdt); 1753 svm_vcpu_getstate_seg(&cstate->segs[NVMM_X64_SEG_IDT], 1754 &vmcb->state.idt); 1755 svm_vcpu_getstate_seg(&cstate->segs[NVMM_X64_SEG_LDT], 1756 &vmcb->state.ldt); 1757 svm_vcpu_getstate_seg(&cstate->segs[NVMM_X64_SEG_TR], 1758 &vmcb->state.tr); 1759 1760 memcpy(nstate->segs, cstate->segs, sizeof(cstate->segs)); 1761 } 1762 1763 if (flags & NVMM_X64_STATE_GPRS) { 1764 cstate->gprs[NVMM_X64_GPR_RIP] = vmcb->state.rip; 1765 cstate->gprs[NVMM_X64_GPR_RSP] = vmcb->state.rsp; 1766 cstate->gprs[NVMM_X64_GPR_RAX] = vmcb->state.rax; 1767 cstate->gprs[NVMM_X64_GPR_RFLAGS] = vmcb->state.rflags; 1768 1769 memcpy(nstate->gprs, cstate->gprs, sizeof(cstate->gprs)); 1770 } 1771 1772 if (flags & NVMM_X64_STATE_CRS) { 1773 cstate->crs[NVMM_X64_CR_CR0] = vmcb->state.cr0; 1774 cstate->crs[NVMM_X64_CR_CR2] = vmcb->state.cr2; 1775 cstate->crs[NVMM_X64_CR_CR3] = vmcb->state.cr3; 1776 cstate->crs[NVMM_X64_CR_CR4] = vmcb->state.cr4; 1777 cstate->crs[NVMM_X64_CR_CR8] = __SHIFTOUT(vmcb->ctrl.v, 1778 VMCB_CTRL_V_TPR); 1779 1780 memcpy(nstate->crs, cstate->crs, sizeof(cstate->crs)); 1781 } 1782 1783 if (flags & NVMM_X64_STATE_DRS) { 1784 cstate->drs[NVMM_X64_DR_DR6] = vmcb->state.dr6; 1785 cstate->drs[NVMM_X64_DR_DR7] = vmcb->state.dr7; 1786 1787 memcpy(nstate->drs, cstate->drs, sizeof(cstate->drs)); 1788 } 1789 1790 if (flags & NVMM_X64_STATE_MSRS) { 1791 cstate->msrs[NVMM_X64_MSR_EFER] = vmcb->state.efer; 1792 cstate->msrs[NVMM_X64_MSR_STAR] = vmcb->state.star; 1793 cstate->msrs[NVMM_X64_MSR_LSTAR] = vmcb->state.lstar; 1794 cstate->msrs[NVMM_X64_MSR_CSTAR] = vmcb->state.cstar; 1795 cstate->msrs[NVMM_X64_MSR_SFMASK] = vmcb->state.sfmask; 1796 cstate->msrs[NVMM_X64_MSR_KERNELGSBASE] = 1797 vmcb->state.kernelgsbase; 1798 cstate->msrs[NVMM_X64_MSR_SYSENTER_CS] = 1799 vmcb->state.sysenter_cs; 1800 cstate->msrs[NVMM_X64_MSR_SYSENTER_ESP] = 1801 vmcb->state.sysenter_esp; 1802 cstate->msrs[NVMM_X64_MSR_SYSENTER_EIP] = 1803 vmcb->state.sysenter_eip; 1804 cstate->msrs[NVMM_X64_MSR_PAT] = vmcb->state.g_pat; 1805 1806 memcpy(nstate->msrs, cstate->msrs, sizeof(cstate->msrs)); 1807 1808 /* Hide SVME. */ 1809 nstate->msrs[NVMM_X64_MSR_EFER] &= ~EFER_SVME; 1810 } 1811 1812 if (flags & NVMM_X64_STATE_MISC) { 1813 cstate->misc[NVMM_X64_MISC_CPL] = vmcb->state.cpl; 1814 1815 memcpy(nstate->misc, cstate->misc, sizeof(cstate->misc)); 1816 } 1817 1818 CTASSERT(sizeof(cpudata->gfpu.xsh_fxsave) == sizeof(cstate->fpu)); 1819 if (flags & NVMM_X64_STATE_FPU) { 1820 memcpy(&cstate->fpu, cpudata->gfpu.xsh_fxsave, 1821 sizeof(cstate->fpu)); 1822 1823 memcpy(&cstate->fpu, &nstate->fpu, sizeof(cstate->fpu)); 1824 } 1825 } 1826 1827 /* -------------------------------------------------------------------------- */ 1828 1829 static void 1830 svm_tlb_flush(struct pmap *pm) 1831 { 1832 struct nvmm_machine *mach = pm->pm_data; 1833 struct svm_cpudata *cpudata; 1834 struct nvmm_cpu *vcpu; 1835 int error; 1836 size_t i; 1837 1838 /* Request TLB flushes. */ 1839 for (i = 0; i < NVMM_MAX_VCPUS; i++) { 1840 error = nvmm_vcpu_get(mach, i, &vcpu); 1841 if (error) 1842 continue; 1843 cpudata = vcpu->cpudata; 1844 cpudata->tlb_want_flush = true; 1845 nvmm_vcpu_put(vcpu); 1846 } 1847 } 1848 1849 static void 1850 svm_machine_create(struct nvmm_machine *mach) 1851 { 1852 /* Fill in pmap info. */ 1853 mach->vm->vm_map.pmap->pm_data = (void *)mach; 1854 mach->vm->vm_map.pmap->pm_tlb_flush = svm_tlb_flush; 1855 1856 mach->machdata = kmem_zalloc(sizeof(struct svm_machdata), KM_SLEEP); 1857 } 1858 1859 static void 1860 svm_machine_destroy(struct nvmm_machine *mach) 1861 { 1862 kmem_free(mach->machdata, sizeof(struct svm_machdata)); 1863 } 1864 1865 static int 1866 svm_machine_configure(struct nvmm_machine *mach, uint64_t op, void *data) 1867 { 1868 struct nvmm_x86_conf_cpuid *cpuid = data; 1869 struct svm_machdata *machdata = (struct svm_machdata *)mach->machdata; 1870 size_t i; 1871 1872 if (__predict_false(op != NVMM_X86_CONF_CPUID)) { 1873 return EINVAL; 1874 } 1875 1876 if (__predict_false((cpuid->set.eax & cpuid->del.eax) || 1877 (cpuid->set.ebx & cpuid->del.ebx) || 1878 (cpuid->set.ecx & cpuid->del.ecx) || 1879 (cpuid->set.edx & cpuid->del.edx))) { 1880 return EINVAL; 1881 } 1882 1883 /* If already here, replace. */ 1884 for (i = 0; i < SVM_NCPUIDS; i++) { 1885 if (!machdata->cpuidpresent[i]) { 1886 continue; 1887 } 1888 if (machdata->cpuid[i].leaf == cpuid->leaf) { 1889 memcpy(&machdata->cpuid[i], cpuid, 1890 sizeof(struct nvmm_x86_conf_cpuid)); 1891 return 0; 1892 } 1893 } 1894 1895 /* Not here, insert. */ 1896 for (i = 0; i < SVM_NCPUIDS; i++) { 1897 if (!machdata->cpuidpresent[i]) { 1898 machdata->cpuidpresent[i] = true; 1899 memcpy(&machdata->cpuid[i], cpuid, 1900 sizeof(struct nvmm_x86_conf_cpuid)); 1901 return 0; 1902 } 1903 } 1904 1905 return ENOBUFS; 1906 } 1907 1908 /* -------------------------------------------------------------------------- */ 1909 1910 static bool 1911 svm_ident(void) 1912 { 1913 u_int descs[4]; 1914 uint64_t msr; 1915 1916 if (cpu_vendor != CPUVENDOR_AMD) { 1917 return false; 1918 } 1919 if (!(cpu_feature[3] & CPUID_SVM)) { 1920 return false; 1921 } 1922 1923 if (curcpu()->ci_max_ext_cpuid < 0x8000000a) { 1924 return false; 1925 } 1926 x86_cpuid(0x8000000a, descs); 1927 1928 /* Want Nested Paging. */ 1929 if (!(descs[3] & CPUID_AMD_SVM_NP)) { 1930 return false; 1931 } 1932 1933 /* Want nRIP. */ 1934 if (!(descs[3] & CPUID_AMD_SVM_NRIPS)) { 1935 return false; 1936 } 1937 1938 svm_decode_assist = (descs[3] & CPUID_AMD_SVM_DecodeAssist) != 0; 1939 1940 msr = rdmsr(MSR_VMCR); 1941 if ((msr & VMCR_SVMED) && (msr & VMCR_LOCK)) { 1942 return false; 1943 } 1944 1945 return true; 1946 } 1947 1948 static void 1949 svm_init_asid(uint32_t maxasid) 1950 { 1951 size_t i, j, allocsz; 1952 1953 mutex_init(&svm_asidlock, MUTEX_DEFAULT, IPL_NONE); 1954 1955 /* Arbitrarily limit. */ 1956 maxasid = uimin(maxasid, 8192); 1957 1958 svm_maxasid = maxasid; 1959 allocsz = roundup(maxasid, 8) / 8; 1960 svm_asidmap = kmem_zalloc(allocsz, KM_SLEEP); 1961 1962 /* ASID 0 is reserved for the host. */ 1963 svm_asidmap[0] |= __BIT(0); 1964 1965 /* ASID n-1 is special, we share it. */ 1966 i = (maxasid - 1) / 8; 1967 j = (maxasid - 1) % 8; 1968 svm_asidmap[i] |= __BIT(j); 1969 } 1970 1971 static void 1972 svm_change_cpu(void *arg1, void *arg2) 1973 { 1974 bool enable = (bool)arg1; 1975 uint64_t msr; 1976 1977 msr = rdmsr(MSR_VMCR); 1978 if (msr & VMCR_SVMED) { 1979 wrmsr(MSR_VMCR, msr & ~VMCR_SVMED); 1980 } 1981 1982 if (!enable) { 1983 wrmsr(MSR_VM_HSAVE_PA, 0); 1984 } 1985 1986 msr = rdmsr(MSR_EFER); 1987 if (enable) { 1988 msr |= EFER_SVME; 1989 } else { 1990 msr &= ~EFER_SVME; 1991 } 1992 wrmsr(MSR_EFER, msr); 1993 1994 if (enable) { 1995 wrmsr(MSR_VM_HSAVE_PA, hsave[cpu_index(curcpu())].pa); 1996 } 1997 } 1998 1999 static void 2000 svm_init(void) 2001 { 2002 CPU_INFO_ITERATOR cii; 2003 struct cpu_info *ci; 2004 struct vm_page *pg; 2005 u_int descs[4]; 2006 uint64_t xc; 2007 2008 x86_cpuid(0x8000000a, descs); 2009 2010 /* The guest TLB flush command. */ 2011 if (descs[3] & CPUID_AMD_SVM_FlushByASID) { 2012 svm_ctrl_tlb_flush = VMCB_CTRL_TLB_CTRL_FLUSH_GUEST; 2013 } else { 2014 svm_ctrl_tlb_flush = VMCB_CTRL_TLB_CTRL_FLUSH_ALL; 2015 } 2016 2017 /* Init the ASID. */ 2018 svm_init_asid(descs[1]); 2019 2020 /* Init the XCR0 mask. */ 2021 svm_xcr0_mask = SVM_XCR0_MASK_DEFAULT & x86_xsave_features; 2022 2023 memset(hsave, 0, sizeof(hsave)); 2024 for (CPU_INFO_FOREACH(cii, ci)) { 2025 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 2026 hsave[cpu_index(ci)].pa = VM_PAGE_TO_PHYS(pg); 2027 } 2028 2029 xc = xc_broadcast(0, svm_change_cpu, (void *)true, NULL); 2030 xc_wait(xc); 2031 } 2032 2033 static void 2034 svm_fini_asid(void) 2035 { 2036 size_t allocsz; 2037 2038 allocsz = roundup(svm_maxasid, 8) / 8; 2039 kmem_free(svm_asidmap, allocsz); 2040 2041 mutex_destroy(&svm_asidlock); 2042 } 2043 2044 static void 2045 svm_fini(void) 2046 { 2047 uint64_t xc; 2048 size_t i; 2049 2050 xc = xc_broadcast(0, svm_change_cpu, (void *)false, NULL); 2051 xc_wait(xc); 2052 2053 for (i = 0; i < MAXCPUS; i++) { 2054 if (hsave[i].pa != 0) 2055 uvm_pagefree(PHYS_TO_VM_PAGE(hsave[i].pa)); 2056 } 2057 2058 svm_fini_asid(); 2059 } 2060 2061 static void 2062 svm_capability(struct nvmm_capability *cap) 2063 { 2064 cap->u.x86.xcr0_mask = svm_xcr0_mask; 2065 cap->u.x86.mxcsr_mask = x86_fpu_mxcsr_mask; 2066 cap->u.x86.conf_cpuid_maxops = SVM_NCPUIDS; 2067 } 2068 2069 const struct nvmm_impl nvmm_x86_svm = { 2070 .ident = svm_ident, 2071 .init = svm_init, 2072 .fini = svm_fini, 2073 .capability = svm_capability, 2074 .conf_max = NVMM_X86_NCONF, 2075 .conf_sizes = svm_conf_sizes, 2076 .state_size = sizeof(struct nvmm_x64_state), 2077 .machine_create = svm_machine_create, 2078 .machine_destroy = svm_machine_destroy, 2079 .machine_configure = svm_machine_configure, 2080 .vcpu_create = svm_vcpu_create, 2081 .vcpu_destroy = svm_vcpu_destroy, 2082 .vcpu_setstate = svm_vcpu_setstate, 2083 .vcpu_getstate = svm_vcpu_getstate, 2084 .vcpu_inject = svm_vcpu_inject, 2085 .vcpu_run = svm_vcpu_run 2086 }; 2087
Indexes created Tue Sep 30 20:09:53 GMT 2025