onewire.c revision 1.13 1 1.13 dyoung /* $NetBSD: onewire.c,v 1.13 2009/12/06 22:49:48 dyoung Exp $ */
2 1.1 riz /* $OpenBSD: onewire.c,v 1.1 2006/03/04 16:27:03 grange Exp $ */
3 1.1 riz
4 1.1 riz /*
5 1.1 riz * Copyright (c) 2006 Alexander Yurchenko <grange (at) openbsd.org>
6 1.1 riz *
7 1.1 riz * Permission to use, copy, modify, and distribute this software for any
8 1.1 riz * purpose with or without fee is hereby granted, provided that the above
9 1.1 riz * copyright notice and this permission notice appear in all copies.
10 1.1 riz *
11 1.1 riz * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 1.1 riz * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 1.1 riz * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 1.1 riz * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 1.1 riz * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 1.1 riz * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 1.1 riz * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 1.1 riz */
19 1.1 riz
20 1.1 riz #include <sys/cdefs.h>
21 1.13 dyoung __KERNEL_RCSID(0, "$NetBSD: onewire.c,v 1.13 2009/12/06 22:49:48 dyoung Exp $");
22 1.1 riz
23 1.1 riz /*
24 1.1 riz * 1-Wire bus driver.
25 1.1 riz */
26 1.1 riz
27 1.1 riz #include <sys/param.h>
28 1.1 riz #include <sys/systm.h>
29 1.1 riz #include <sys/conf.h>
30 1.1 riz #include <sys/device.h>
31 1.1 riz #include <sys/kernel.h>
32 1.1 riz #include <sys/kthread.h>
33 1.6 xtraeme #include <sys/rwlock.h>
34 1.1 riz #include <sys/malloc.h>
35 1.1 riz #include <sys/proc.h>
36 1.1 riz #include <sys/queue.h>
37 1.1 riz
38 1.1 riz #include <dev/onewire/onewirereg.h>
39 1.1 riz #include <dev/onewire/onewirevar.h>
40 1.1 riz
41 1.1 riz #ifdef ONEWIRE_DEBUG
42 1.1 riz #define DPRINTF(x) printf x
43 1.1 riz #else
44 1.1 riz #define DPRINTF(x)
45 1.1 riz #endif
46 1.1 riz
47 1.1 riz //#define ONEWIRE_MAXDEVS 256
48 1.1 riz #define ONEWIRE_MAXDEVS 8
49 1.1 riz #define ONEWIRE_SCANTIME 3
50 1.1 riz
51 1.1 riz struct onewire_softc {
52 1.9 xtraeme device_t sc_dev;
53 1.1 riz
54 1.1 riz struct onewire_bus * sc_bus;
55 1.6 xtraeme krwlock_t sc_rwlock;
56 1.5 ad struct lwp * sc_thread;
57 1.1 riz TAILQ_HEAD(, onewire_device) sc_devs;
58 1.1 riz
59 1.1 riz int sc_dying;
60 1.1 riz };
61 1.1 riz
62 1.1 riz struct onewire_device {
63 1.1 riz TAILQ_ENTRY(onewire_device) d_list;
64 1.9 xtraeme device_t d_dev;
65 1.1 riz u_int64_t d_rom;
66 1.1 riz int d_present;
67 1.1 riz };
68 1.1 riz
69 1.9 xtraeme static int onewire_match(device_t, cfdata_t, void *);
70 1.9 xtraeme static void onewire_attach(device_t, device_t, void *);
71 1.9 xtraeme static int onewire_detach(device_t, int);
72 1.9 xtraeme static int onewire_activate(device_t, enum devact);
73 1.9 xtraeme int onewire_print(void *, const char *);
74 1.1 riz
75 1.9 xtraeme static void onewire_thread(void *);
76 1.9 xtraeme static void onewire_scan(struct onewire_softc *);
77 1.1 riz
78 1.9 xtraeme CFATTACH_DECL_NEW(onewire, sizeof(struct onewire_softc),
79 1.1 riz onewire_match, onewire_attach, onewire_detach, onewire_activate);
80 1.1 riz
81 1.1 riz const struct cdevsw onewire_cdevsw = {
82 1.1 riz noopen, noclose, noread, nowrite, noioctl, nostop, notty,
83 1.2 christos nopoll, nommap, nokqfilter, D_OTHER,
84 1.1 riz };
85 1.1 riz
86 1.1 riz extern struct cfdriver onewire_cd;
87 1.1 riz
88 1.9 xtraeme static int
89 1.9 xtraeme onewire_match(device_t parent, cfdata_t cf, void *aux)
90 1.1 riz {
91 1.1 riz return 1;
92 1.1 riz }
93 1.1 riz
94 1.9 xtraeme static void
95 1.9 xtraeme onewire_attach(device_t parent, device_t self, void *aux)
96 1.1 riz {
97 1.1 riz struct onewire_softc *sc = device_private(self);
98 1.1 riz struct onewirebus_attach_args *oba = aux;
99 1.1 riz
100 1.9 xtraeme sc->sc_dev = self;
101 1.1 riz sc->sc_bus = oba->oba_bus;
102 1.6 xtraeme rw_init(&sc->sc_rwlock);
103 1.1 riz TAILQ_INIT(&sc->sc_devs);
104 1.1 riz
105 1.6 xtraeme aprint_naive("\n");
106 1.6 xtraeme aprint_normal("\n");
107 1.1 riz
108 1.5 ad if (kthread_create(PRI_NONE, 0, NULL, onewire_thread, sc,
109 1.9 xtraeme &sc->sc_thread, "%s", device_xname(self)) != 0)
110 1.9 xtraeme aprint_error_dev(self, "can't create kernel thread\n");
111 1.1 riz }
112 1.1 riz
113 1.9 xtraeme static int
114 1.9 xtraeme onewire_detach(device_t self, int flags)
115 1.1 riz {
116 1.1 riz struct onewire_softc *sc = device_private(self);
117 1.1 riz int rv;
118 1.1 riz
119 1.1 riz sc->sc_dying = 1;
120 1.1 riz if (sc->sc_thread != NULL) {
121 1.1 riz wakeup(sc->sc_thread);
122 1.1 riz tsleep(&sc->sc_dying, PWAIT, "owdt", 0);
123 1.1 riz }
124 1.1 riz
125 1.7 xtraeme onewire_lock(sc);
126 1.1 riz //rv = config_detach_children(self, flags);
127 1.1 riz rv = 0; /* XXX riz */
128 1.1 riz onewire_unlock(sc);
129 1.6 xtraeme rw_destroy(&sc->sc_rwlock);
130 1.1 riz
131 1.6 xtraeme return rv;
132 1.1 riz }
133 1.1 riz
134 1.9 xtraeme static int
135 1.9 xtraeme onewire_activate(device_t self, enum devact act)
136 1.1 riz {
137 1.1 riz struct onewire_softc *sc = device_private(self);
138 1.1 riz
139 1.1 riz switch (act) {
140 1.1 riz case DVACT_DEACTIVATE:
141 1.1 riz sc->sc_dying = 1;
142 1.13 dyoung return 0;
143 1.13 dyoung default:
144 1.13 dyoung return EOPNOTSUPP;
145 1.1 riz }
146 1.1 riz }
147 1.1 riz
148 1.1 riz int
149 1.1 riz onewire_print(void *aux, const char *pnp)
150 1.1 riz {
151 1.1 riz struct onewire_attach_args *oa = aux;
152 1.1 riz const char *famname;
153 1.1 riz
154 1.1 riz if (pnp == NULL)
155 1.6 xtraeme aprint_normal(" ");
156 1.1 riz
157 1.1 riz famname = onewire_famname(ONEWIRE_ROM_FAMILY_TYPE(oa->oa_rom));
158 1.1 riz if (famname == NULL)
159 1.6 xtraeme aprint_normal("family 0x%02x",
160 1.6 xtraeme (uint)ONEWIRE_ROM_FAMILY_TYPE(oa->oa_rom));
161 1.1 riz else
162 1.6 xtraeme aprint_normal("\"%s\"", famname);
163 1.6 xtraeme aprint_normal(" sn %012llx", ONEWIRE_ROM_SN(oa->oa_rom));
164 1.1 riz
165 1.1 riz if (pnp != NULL)
166 1.6 xtraeme aprint_normal(" at %s", pnp);
167 1.1 riz
168 1.6 xtraeme return UNCONF;
169 1.1 riz }
170 1.1 riz
171 1.1 riz int
172 1.4 christos onewirebus_print(void *aux, const char *pnp)
173 1.1 riz {
174 1.1 riz if (pnp != NULL)
175 1.6 xtraeme aprint_normal("onewire at %s", pnp);
176 1.1 riz
177 1.6 xtraeme return UNCONF;
178 1.1 riz }
179 1.1 riz
180 1.7 xtraeme void
181 1.7 xtraeme onewire_lock(void *arg)
182 1.1 riz {
183 1.1 riz struct onewire_softc *sc = arg;
184 1.1 riz
185 1.6 xtraeme rw_enter(&sc->sc_rwlock, RW_WRITER);
186 1.1 riz }
187 1.1 riz
188 1.1 riz void
189 1.1 riz onewire_unlock(void *arg)
190 1.1 riz {
191 1.1 riz struct onewire_softc *sc = arg;
192 1.1 riz
193 1.6 xtraeme rw_exit(&sc->sc_rwlock);
194 1.1 riz }
195 1.1 riz
196 1.1 riz int
197 1.1 riz onewire_reset(void *arg)
198 1.1 riz {
199 1.1 riz struct onewire_softc *sc = arg;
200 1.1 riz struct onewire_bus *bus = sc->sc_bus;
201 1.1 riz
202 1.6 xtraeme return bus->bus_reset(bus->bus_cookie);
203 1.1 riz }
204 1.1 riz
205 1.1 riz int
206 1.1 riz onewire_bit(void *arg, int value)
207 1.1 riz {
208 1.1 riz struct onewire_softc *sc = arg;
209 1.1 riz struct onewire_bus *bus = sc->sc_bus;
210 1.1 riz
211 1.6 xtraeme return bus->bus_bit(bus->bus_cookie, value);
212 1.1 riz }
213 1.1 riz
214 1.1 riz int
215 1.1 riz onewire_read_byte(void *arg)
216 1.1 riz {
217 1.1 riz struct onewire_softc *sc = arg;
218 1.1 riz struct onewire_bus *bus = sc->sc_bus;
219 1.6 xtraeme uint8_t value = 0;
220 1.1 riz int i;
221 1.1 riz
222 1.1 riz if (bus->bus_read_byte != NULL)
223 1.6 xtraeme return bus->bus_read_byte(bus->bus_cookie);
224 1.1 riz
225 1.1 riz for (i = 0; i < 8; i++)
226 1.1 riz value |= (bus->bus_bit(bus->bus_cookie, 1) << i);
227 1.1 riz
228 1.6 xtraeme return value;
229 1.1 riz }
230 1.1 riz
231 1.1 riz void
232 1.1 riz onewire_write_byte(void *arg, int value)
233 1.1 riz {
234 1.1 riz struct onewire_softc *sc = arg;
235 1.1 riz struct onewire_bus *bus = sc->sc_bus;
236 1.1 riz int i;
237 1.1 riz
238 1.1 riz if (bus->bus_write_byte != NULL)
239 1.6 xtraeme return bus->bus_write_byte(bus->bus_cookie, value);
240 1.1 riz
241 1.1 riz for (i = 0; i < 8; i++)
242 1.1 riz bus->bus_bit(bus->bus_cookie, (value >> i) & 0x1);
243 1.1 riz }
244 1.1 riz
245 1.1 riz int
246 1.1 riz onewire_triplet(void *arg, int dir)
247 1.1 riz {
248 1.1 riz struct onewire_softc *sc = arg;
249 1.1 riz struct onewire_bus *bus = sc->sc_bus;
250 1.1 riz int rv;
251 1.1 riz
252 1.1 riz if (bus->bus_triplet != NULL)
253 1.6 xtraeme return bus->bus_triplet(bus->bus_cookie, dir);
254 1.1 riz
255 1.1 riz rv = bus->bus_bit(bus->bus_cookie, 1);
256 1.1 riz rv <<= 1;
257 1.1 riz rv |= bus->bus_bit(bus->bus_cookie, 1);
258 1.1 riz
259 1.1 riz switch (rv) {
260 1.1 riz case 0x0:
261 1.1 riz bus->bus_bit(bus->bus_cookie, dir);
262 1.1 riz break;
263 1.1 riz case 0x1:
264 1.1 riz bus->bus_bit(bus->bus_cookie, 0);
265 1.1 riz break;
266 1.1 riz default:
267 1.1 riz bus->bus_bit(bus->bus_cookie, 1);
268 1.1 riz }
269 1.1 riz
270 1.6 xtraeme return rv;
271 1.1 riz }
272 1.1 riz
273 1.1 riz void
274 1.1 riz onewire_read_block(void *arg, void *buf, int len)
275 1.1 riz {
276 1.6 xtraeme uint8_t *p = buf;
277 1.1 riz
278 1.1 riz while (len--)
279 1.1 riz *p++ = onewire_read_byte(arg);
280 1.1 riz }
281 1.1 riz
282 1.1 riz void
283 1.1 riz onewire_write_block(void *arg, const void *buf, int len)
284 1.1 riz {
285 1.6 xtraeme const uint8_t *p = buf;
286 1.1 riz
287 1.1 riz while (len--)
288 1.1 riz onewire_write_byte(arg, *p++);
289 1.1 riz }
290 1.1 riz
291 1.1 riz void
292 1.1 riz onewire_matchrom(void *arg, u_int64_t rom)
293 1.1 riz {
294 1.1 riz int i;
295 1.1 riz
296 1.1 riz onewire_write_byte(arg, ONEWIRE_CMD_MATCH_ROM);
297 1.1 riz for (i = 0; i < 8; i++)
298 1.1 riz onewire_write_byte(arg, (rom >> (i * 8)) & 0xff);
299 1.1 riz }
300 1.1 riz
301 1.9 xtraeme static void
302 1.1 riz onewire_thread(void *arg)
303 1.1 riz {
304 1.1 riz struct onewire_softc *sc = arg;
305 1.1 riz
306 1.1 riz while (!sc->sc_dying) {
307 1.1 riz onewire_scan(sc);
308 1.1 riz tsleep(sc->sc_thread, PWAIT, "owidle", ONEWIRE_SCANTIME * hz);
309 1.1 riz }
310 1.1 riz
311 1.1 riz sc->sc_thread = NULL;
312 1.1 riz wakeup(&sc->sc_dying);
313 1.1 riz kthread_exit(0);
314 1.1 riz }
315 1.9 xtraeme
316 1.9 xtraeme static void
317 1.1 riz onewire_scan(struct onewire_softc *sc)
318 1.1 riz {
319 1.1 riz struct onewire_device *d, *next, *nd;
320 1.1 riz struct onewire_attach_args oa;
321 1.12 cegger device_t dev;
322 1.1 riz int search = 1, count = 0, present;
323 1.1 riz int dir, rv;
324 1.6 xtraeme uint64_t mask, rom = 0, lastrom;
325 1.6 xtraeme uint8_t data[8];
326 1.1 riz int i, i0 = -1, lastd = -1;
327 1.1 riz
328 1.1 riz TAILQ_FOREACH(d, &sc->sc_devs, d_list)
329 1.1 riz d->d_present = 0;
330 1.1 riz
331 1.1 riz while (search && count++ < ONEWIRE_MAXDEVS) {
332 1.1 riz /* XXX: yield processor */
333 1.1 riz tsleep(sc, PWAIT, "owscan", hz / 10);
334 1.1 riz
335 1.1 riz /*
336 1.1 riz * Reset the bus. If there's no presence pulse
337 1.1 riz * don't search for any devices.
338 1.1 riz */
339 1.7 xtraeme onewire_lock(sc);
340 1.1 riz if (onewire_reset(sc) != 0) {
341 1.1 riz DPRINTF(("%s: scan: no presence pulse\n",
342 1.9 xtraeme device_xname(sc->sc_dev)));
343 1.1 riz onewire_unlock(sc);
344 1.1 riz break;
345 1.1 riz }
346 1.1 riz
347 1.1 riz /*
348 1.1 riz * Start new search. Go through the previous path to
349 1.1 riz * the point we made a decision last time and make an
350 1.1 riz * opposite decision. If we didn't make any decision
351 1.1 riz * stop searching.
352 1.1 riz */
353 1.1 riz search = 0;
354 1.1 riz lastrom = rom;
355 1.1 riz rom = 0;
356 1.1 riz onewire_write_byte(sc, ONEWIRE_CMD_SEARCH_ROM);
357 1.1 riz for (i = 0,i0 = -1; i < 64; i++) {
358 1.1 riz dir = (lastrom >> i) & 0x1;
359 1.1 riz if (i == lastd)
360 1.1 riz dir = 1;
361 1.1 riz else if (i > lastd)
362 1.1 riz dir = 0;
363 1.1 riz rv = onewire_triplet(sc, dir);
364 1.1 riz switch (rv) {
365 1.1 riz case 0x0:
366 1.1 riz if (i != lastd) {
367 1.1 riz if (dir == 0)
368 1.1 riz i0 = i;
369 1.1 riz search = 1;
370 1.1 riz }
371 1.1 riz mask = dir;
372 1.1 riz break;
373 1.1 riz case 0x1:
374 1.1 riz mask = 0;
375 1.1 riz break;
376 1.1 riz case 0x2:
377 1.1 riz mask = 1;
378 1.1 riz break;
379 1.1 riz default:
380 1.1 riz DPRINTF(("%s: scan: triplet error 0x%x, "
381 1.1 riz "step %d\n",
382 1.9 xtraeme device_xname(sc->sc_dev), rv, i));
383 1.1 riz onewire_unlock(sc);
384 1.1 riz return;
385 1.1 riz }
386 1.1 riz rom |= (mask << i);
387 1.1 riz }
388 1.1 riz lastd = i0;
389 1.1 riz onewire_unlock(sc);
390 1.1 riz
391 1.1 riz if (rom == 0)
392 1.1 riz continue;
393 1.1 riz
394 1.1 riz /*
395 1.1 riz * The last byte of the ROM code contains a CRC calculated
396 1.1 riz * from the first 7 bytes. Re-calculate it to make sure
397 1.1 riz * we found a valid device.
398 1.1 riz */
399 1.1 riz for (i = 0; i < 8; i++)
400 1.1 riz data[i] = (rom >> (i * 8)) & 0xff;
401 1.1 riz if (onewire_crc(data, 7) != data[7])
402 1.1 riz continue;
403 1.1 riz
404 1.1 riz /*
405 1.1 riz * Go through the list of attached devices to see if we
406 1.1 riz * found a new one.
407 1.1 riz */
408 1.1 riz present = 0;
409 1.1 riz TAILQ_FOREACH(d, &sc->sc_devs, d_list) {
410 1.1 riz if (d->d_rom == rom) {
411 1.1 riz d->d_present = 1;
412 1.1 riz present = 1;
413 1.1 riz break;
414 1.1 riz }
415 1.1 riz }
416 1.1 riz if (!present) {
417 1.11 cegger memset(&oa, 0, sizeof(oa));
418 1.1 riz oa.oa_onewire = sc;
419 1.1 riz oa.oa_rom = rom;
420 1.9 xtraeme if ((dev = config_found(sc->sc_dev, &oa,
421 1.1 riz onewire_print)) == NULL)
422 1.1 riz continue;
423 1.1 riz
424 1.10 cegger nd = malloc(sizeof(struct onewire_device),
425 1.10 cegger M_DEVBUF, M_NOWAIT);
426 1.1 riz if (nd == NULL)
427 1.1 riz continue;
428 1.1 riz nd->d_dev = dev;
429 1.1 riz nd->d_rom = rom;
430 1.1 riz nd->d_present = 1;
431 1.1 riz TAILQ_INSERT_TAIL(&sc->sc_devs, nd, d_list);
432 1.1 riz }
433 1.1 riz }
434 1.1 riz
435 1.1 riz /* Detach disappeared devices */
436 1.7 xtraeme onewire_lock(sc);
437 1.1 riz for (d = TAILQ_FIRST(&sc->sc_devs);
438 1.1 riz d != NULL; d = next) {
439 1.1 riz next = TAILQ_NEXT(d, d_list);
440 1.1 riz if (!d->d_present) {
441 1.1 riz config_detach(d->d_dev, DETACH_FORCE);
442 1.1 riz TAILQ_REMOVE(&sc->sc_devs, d, d_list);
443 1.10 cegger free(d, M_DEVBUF);
444 1.1 riz }
445 1.1 riz }
446 1.1 riz onewire_unlock(sc);
447 1.1 riz }
448