aac_pci.c revision 1.23.4.4
1 /* $NetBSD: aac_pci.c,v 1.23.4.4 2010/03/11 15:03:42 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 2000 Michael Smith 34 * Copyright (c) 2000 BSDi 35 * Copyright (c) 2000 Niklas Hallqvist 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 48 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 49 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 50 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 51 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 52 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 53 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 55 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 56 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 57 * SUCH DAMAGE. 58 * 59 * from FreeBSD: aac_pci.c,v 1.1 2000/09/13 03:20:34 msmith Exp 60 * via OpenBSD: aac_pci.c,v 1.7 2002/03/14 01:26:58 millert Exp 61 */ 62 63 /* 64 * PCI front-end for the `aac' driver. 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: aac_pci.c,v 1.23.4.4 2010/03/11 15:03:42 yamt Exp $"); 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/device.h> 73 #include <sys/kernel.h> 74 #include <sys/malloc.h> 75 #include <sys/queue.h> 76 77 #include <sys/bus.h> 78 #include <machine/endian.h> 79 #include <sys/intr.h> 80 81 #include <dev/pci/pcidevs.h> 82 #include <dev/pci/pcireg.h> 83 #include <dev/pci/pcivar.h> 84 85 #include <dev/ic/aacreg.h> 86 #include <dev/ic/aacvar.h> 87 88 struct aac_pci_softc { 89 struct aac_softc sc_aac; 90 pci_chipset_tag_t sc_pc; 91 pci_intr_handle_t sc_ih; 92 }; 93 94 /* i960Rx interface */ 95 static int aac_rx_get_fwstatus(struct aac_softc *); 96 static void aac_rx_qnotify(struct aac_softc *, int); 97 static int aac_rx_get_istatus(struct aac_softc *); 98 static void aac_rx_clear_istatus(struct aac_softc *, int); 99 static void aac_rx_set_mailbox(struct aac_softc *, u_int32_t, u_int32_t, 100 u_int32_t, u_int32_t, u_int32_t); 101 static uint32_t aac_rx_get_mailbox(struct aac_softc *, int); 102 static void aac_rx_set_interrupts(struct aac_softc *, int); 103 static int aac_rx_send_command(struct aac_softc *, struct aac_ccb *); 104 static int aac_rx_get_outb_queue(struct aac_softc *); 105 static void aac_rx_set_outb_queue(struct aac_softc *, int); 106 107 /* StrongARM interface */ 108 static int aac_sa_get_fwstatus(struct aac_softc *); 109 static void aac_sa_qnotify(struct aac_softc *, int); 110 static int aac_sa_get_istatus(struct aac_softc *); 111 static void aac_sa_clear_istatus(struct aac_softc *, int); 112 static void aac_sa_set_mailbox(struct aac_softc *, u_int32_t, u_int32_t, 113 u_int32_t, u_int32_t, u_int32_t); 114 static uint32_t aac_sa_get_mailbox(struct aac_softc *, int); 115 static void aac_sa_set_interrupts(struct aac_softc *, int); 116 117 /* Rocket/MIPS interface */ 118 static int aac_rkt_get_fwstatus(struct aac_softc *); 119 static void aac_rkt_qnotify(struct aac_softc *, int); 120 static int aac_rkt_get_istatus(struct aac_softc *); 121 static void aac_rkt_clear_istatus(struct aac_softc *, int); 122 static void aac_rkt_set_mailbox(struct aac_softc *, u_int32_t, u_int32_t, 123 u_int32_t, u_int32_t, u_int32_t); 124 static uint32_t aac_rkt_get_mailbox(struct aac_softc *, int); 125 static void aac_rkt_set_interrupts(struct aac_softc *, int); 126 static int aac_rkt_send_command(struct aac_softc *, struct aac_ccb *); 127 static int aac_rkt_get_outb_queue(struct aac_softc *); 128 static void aac_rkt_set_outb_queue(struct aac_softc *, int); 129 130 static const struct aac_interface aac_rx_interface = { 131 aac_rx_get_fwstatus, 132 aac_rx_qnotify, 133 aac_rx_get_istatus, 134 aac_rx_clear_istatus, 135 aac_rx_set_mailbox, 136 aac_rx_get_mailbox, 137 aac_rx_set_interrupts, 138 aac_rx_send_command, 139 aac_rx_get_outb_queue, 140 aac_rx_set_outb_queue 141 }; 142 143 static const struct aac_interface aac_sa_interface = { 144 aac_sa_get_fwstatus, 145 aac_sa_qnotify, 146 aac_sa_get_istatus, 147 aac_sa_clear_istatus, 148 aac_sa_set_mailbox, 149 aac_sa_get_mailbox, 150 aac_sa_set_interrupts, 151 NULL, NULL, NULL 152 }; 153 154 static const struct aac_interface aac_rkt_interface = { 155 aac_rkt_get_fwstatus, 156 aac_rkt_qnotify, 157 aac_rkt_get_istatus, 158 aac_rkt_clear_istatus, 159 aac_rkt_set_mailbox, 160 aac_rkt_get_mailbox, 161 aac_rkt_set_interrupts, 162 aac_rkt_send_command, 163 aac_rkt_get_outb_queue, 164 aac_rkt_set_outb_queue 165 }; 166 167 static struct aac_ident { 168 u_short vendor; 169 u_short device; 170 u_short subvendor; 171 u_short subdevice; 172 u_short hwif; 173 u_short quirks; 174 const char *prodstr; 175 } const aac_ident[] = { 176 { 177 PCI_VENDOR_DELL, 178 PCI_PRODUCT_DELL_PERC_2SI, 179 PCI_VENDOR_DELL, 180 PCI_PRODUCT_DELL_PERC_2SI, 181 AAC_HWIF_I960RX, 182 0, 183 "Dell PERC 2/Si" 184 }, 185 { 186 PCI_VENDOR_DELL, 187 PCI_PRODUCT_DELL_PERC_3DI, 188 PCI_VENDOR_DELL, 189 PCI_PRODUCT_DELL_PERC_3DI, 190 AAC_HWIF_I960RX, 191 0, 192 "Dell PERC 3/Di" 193 }, 194 { 195 PCI_VENDOR_DELL, 196 PCI_PRODUCT_DELL_PERC_3DI, 197 PCI_VENDOR_DELL, 198 PCI_PRODUCT_DELL_PERC_3DI_SUB2, 199 AAC_HWIF_I960RX, 200 0, 201 "Dell PERC 3/Di" 202 }, 203 { 204 PCI_VENDOR_DELL, 205 PCI_PRODUCT_DELL_PERC_3DI, 206 PCI_VENDOR_DELL, 207 PCI_PRODUCT_DELL_PERC_3DI_SUB3, 208 AAC_HWIF_I960RX, 209 0, 210 "Dell PERC 3/Di" 211 }, 212 { 213 PCI_VENDOR_DELL, 214 PCI_PRODUCT_DELL_PERC_3DI_2, 215 PCI_VENDOR_DELL, 216 PCI_PRODUCT_DELL_PERC_3DI_2_SUB, 217 AAC_HWIF_I960RX, 218 0, 219 "Dell PERC 3/Di" 220 }, 221 { 222 PCI_VENDOR_DELL, 223 PCI_PRODUCT_DELL_PERC_3DI_3, 224 PCI_VENDOR_DELL, 225 PCI_PRODUCT_DELL_PERC_3DI_3_SUB, 226 AAC_HWIF_I960RX, 227 0, 228 "Dell PERC 3/Di" 229 }, 230 { 231 PCI_VENDOR_DELL, 232 PCI_PRODUCT_DELL_PERC_3DI_3, 233 PCI_VENDOR_DELL, 234 PCI_PRODUCT_DELL_PERC_3DI_3_SUB2, 235 AAC_HWIF_I960RX, 236 0, 237 "Dell PERC 3/Di" 238 }, 239 { 240 PCI_VENDOR_DELL, 241 PCI_PRODUCT_DELL_PERC_3DI_3, 242 PCI_VENDOR_DELL, 243 PCI_PRODUCT_DELL_PERC_3DI_3_SUB3, 244 AAC_HWIF_I960RX, 245 0, 246 "Dell PERC 3/Di" 247 }, 248 { 249 PCI_VENDOR_DELL, 250 PCI_PRODUCT_DELL_PERC_3SI, 251 PCI_VENDOR_DELL, 252 PCI_PRODUCT_DELL_PERC_3SI, 253 AAC_HWIF_I960RX, 254 0, 255 "Dell PERC 3/Si" 256 }, 257 { 258 PCI_VENDOR_DELL, 259 PCI_PRODUCT_DELL_PERC_3SI_2, 260 PCI_VENDOR_DELL, 261 PCI_PRODUCT_DELL_PERC_3SI_2_SUB, 262 AAC_HWIF_I960RX, 263 0, 264 "Dell PERC 3/Si" 265 }, 266 { 267 PCI_VENDOR_ADP2, 268 PCI_PRODUCT_ADP2_ASR2200S, 269 PCI_VENDOR_DELL, 270 PCI_PRODUCT_DELL_CERC_1_5, 271 AAC_HWIF_I960RX, 272 AAC_QUIRK_NO4GB, 273 "Dell CERC SATA RAID 1.5/6ch" 274 }, 275 { 276 PCI_VENDOR_ADP2, 277 PCI_PRODUCT_ADP2_AAC2622, 278 PCI_VENDOR_ADP2, 279 PCI_PRODUCT_ADP2_AAC2622, 280 AAC_HWIF_I960RX, 281 0, 282 "Adaptec ADP-2622" 283 }, 284 { 285 PCI_VENDOR_ADP2, 286 PCI_PRODUCT_ADP2_ASR2200S, 287 PCI_VENDOR_ADP2, 288 PCI_PRODUCT_ADP2_ASR2200S_SUB2M, 289 AAC_HWIF_I960RX, 290 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 291 "Adaptec ASR-2200S" 292 }, 293 { 294 PCI_VENDOR_ADP2, 295 PCI_PRODUCT_ADP2_ASR2200S, 296 PCI_VENDOR_DELL, 297 PCI_PRODUCT_ADP2_ASR2200S_SUB2M, 298 AAC_HWIF_I960RX, 299 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 300 "Dell PERC 320/DC" 301 }, 302 { 303 PCI_VENDOR_ADP2, 304 PCI_PRODUCT_ADP2_ASR2200S, 305 PCI_VENDOR_ADP2, 306 PCI_PRODUCT_ADP2_ASR2200S, 307 AAC_HWIF_I960RX, 308 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 309 "Adaptec ASR-2200S" 310 }, 311 { 312 PCI_VENDOR_ADP2, 313 PCI_PRODUCT_ADP2_ASR2200S, 314 PCI_VENDOR_ADP2, 315 PCI_PRODUCT_ADP2_AAR2810SA, 316 AAC_HWIF_I960RX, 317 AAC_QUIRK_NO4GB, 318 "Adaptec AAR-2810SA" 319 }, 320 { 321 PCI_VENDOR_ADP2, 322 PCI_PRODUCT_ADP2_ASR2200S, 323 PCI_VENDOR_ADP2, 324 PCI_PRODUCT_ADP2_ASR2120S, 325 AAC_HWIF_I960RX, 326 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 327 "Adaptec ASR-2120S" 328 }, 329 { 330 PCI_VENDOR_ADP2, 331 PCI_PRODUCT_ADP2_ASR2200S, 332 PCI_VENDOR_ADP2, 333 PCI_PRODUCT_ADP2_ASR2410SA, 334 AAC_HWIF_I960RX, 335 AAC_QUIRK_NO4GB, 336 "Adaptec ASR-2410SA" 337 }, 338 { 339 PCI_VENDOR_ADP2, 340 PCI_PRODUCT_ADP2_ASR2200S, 341 PCI_VENDOR_HP, 342 PCI_PRODUCT_ADP2_HP_M110_G2, 343 AAC_HWIF_I960RX, 344 AAC_QUIRK_NO4GB, 345 "HP ML110 G2 (Adaptec ASR-2610SA)" 346 }, 347 { 348 PCI_VENDOR_ADP2, 349 PCI_PRODUCT_ADP2_ASR2120S, 350 PCI_VENDOR_IBM, 351 PCI_PRODUCT_IBM_SERVERAID8K, 352 AAC_HWIF_RKT, 353 0, 354 "IBM ServeRAID 8k" 355 }, 356 { 357 PCI_VENDOR_DEC, 358 PCI_PRODUCT_DEC_21554, 359 PCI_VENDOR_ADP2, 360 PCI_PRODUCT_ADP2_AAC364, 361 AAC_HWIF_STRONGARM, 362 0, 363 "Adaptec AAC-364" 364 }, 365 { 366 PCI_VENDOR_DEC, 367 PCI_PRODUCT_DEC_21554, 368 PCI_VENDOR_ADP2, 369 PCI_PRODUCT_ADP2_ASR5400S, 370 AAC_HWIF_STRONGARM, 371 AAC_QUIRK_BROKEN_MMAP, 372 "Adaptec ASR-5400S" 373 }, 374 { 375 PCI_VENDOR_DEC, 376 PCI_PRODUCT_DEC_21554, 377 PCI_VENDOR_ADP2, 378 PCI_PRODUCT_ADP2_PERC_2QC, 379 AAC_HWIF_STRONGARM, 380 AAC_QUIRK_PERC2QC, 381 "Dell PERC 2/QC" 382 }, 383 { 384 PCI_VENDOR_DEC, 385 PCI_PRODUCT_DEC_21554, 386 PCI_VENDOR_ADP2, 387 PCI_PRODUCT_ADP2_PERC_3QC, 388 AAC_HWIF_STRONGARM, 389 0, 390 "Dell PERC 3/QC" 391 }, 392 { 393 PCI_VENDOR_DEC, 394 PCI_PRODUCT_DEC_21554, 395 PCI_VENDOR_HP, 396 PCI_PRODUCT_HP_NETRAID_4M, 397 AAC_HWIF_STRONGARM, 398 0, 399 "HP NetRAID-4M" 400 }, 401 }; 402 403 static const struct aac_ident * 404 aac_find_ident(struct pci_attach_args *pa) 405 { 406 const struct aac_ident *m, *mm; 407 u_int32_t subsysid; 408 409 m = aac_ident; 410 mm = aac_ident + (sizeof(aac_ident) / sizeof(aac_ident[0])); 411 412 while (m < mm) { 413 if (m->vendor == PCI_VENDOR(pa->pa_id) && 414 m->device == PCI_PRODUCT(pa->pa_id)) { 415 subsysid = pci_conf_read(pa->pa_pc, pa->pa_tag, 416 PCI_SUBSYS_ID_REG); 417 if (m->subvendor == PCI_VENDOR(subsysid) && 418 m->subdevice == PCI_PRODUCT(subsysid)) 419 return (m); 420 } 421 m++; 422 } 423 424 return (NULL); 425 } 426 427 static int 428 aac_pci_intr_set(struct aac_softc *sc, int (*hand)(void*), void *arg) 429 { 430 struct aac_pci_softc *pcisc; 431 432 pcisc = (struct aac_pci_softc *) sc; 433 434 pci_intr_disestablish(pcisc->sc_pc, sc->sc_ih); 435 sc->sc_ih = pci_intr_establish(pcisc->sc_pc, pcisc->sc_ih, 436 IPL_BIO, hand, arg); 437 if (sc->sc_ih == NULL) { 438 return ENXIO; 439 } 440 return 0; 441 } 442 443 static int 444 aac_pci_match(device_t parent, cfdata_t match, void *aux) 445 { 446 struct pci_attach_args *pa; 447 448 pa = aux; 449 450 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 451 return (0); 452 453 return (aac_find_ident(pa) != NULL); 454 } 455 456 static void 457 aac_pci_attach(device_t parent, device_t self, void *aux) 458 { 459 struct pci_attach_args *pa; 460 pci_chipset_tag_t pc; 461 struct aac_pci_softc *pcisc; 462 struct aac_softc *sc; 463 u_int16_t command; 464 bus_addr_t membase; 465 bus_size_t memsize; 466 const char *intrstr; 467 int state; 468 const struct aac_ident *m; 469 470 pa = aux; 471 pc = pa->pa_pc; 472 pcisc = device_private(self); 473 pcisc->sc_pc = pc; 474 sc = &pcisc->sc_aac; 475 state = 0; 476 477 aprint_naive(": RAID controller\n"); 478 aprint_normal(": "); 479 480 /* 481 * Verify that the adapter is correctly set up in PCI space. 482 */ 483 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 484 command |= PCI_COMMAND_MASTER_ENABLE; 485 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 486 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 487 AAC_DPRINTF(AAC_D_MISC, ("pci command status reg 0x08x ")); 488 489 if ((command & PCI_COMMAND_MASTER_ENABLE) == 0) { 490 aprint_error("can't enable bus-master feature\n"); 491 goto bail_out; 492 } 493 494 if ((command & PCI_COMMAND_MEM_ENABLE) == 0) { 495 aprint_error("memory window not available\n"); 496 goto bail_out; 497 } 498 499 /* 500 * Map control/status registers. 501 */ 502 if (pci_mapreg_map(pa, PCI_MAPREG_START, 503 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_memt, 504 &sc->sc_memh, &membase, &memsize)) { 505 aprint_error("can't find mem space\n"); 506 goto bail_out; 507 } 508 state++; 509 510 if (pci_intr_map(pa, &pcisc->sc_ih)) { 511 aprint_error("couldn't map interrupt\n"); 512 goto bail_out; 513 } 514 intrstr = pci_intr_string(pc, pcisc->sc_ih); 515 sc->sc_ih = pci_intr_establish(pc, pcisc->sc_ih, IPL_BIO, aac_intr, sc); 516 if (sc->sc_ih == NULL) { 517 aprint_error("couldn't establish interrupt"); 518 if (intrstr != NULL) 519 aprint_error(" at %s", intrstr); 520 aprint_error("\n"); 521 goto bail_out; 522 } 523 state++; 524 525 sc->sc_dmat = pa->pa_dmat; 526 527 m = aac_find_ident(pa); 528 aprint_normal("%s\n", m->prodstr); 529 if (intrstr != NULL) 530 aprint_normal_dev(&sc->sc_dv, "interrupting at %s\n", 531 intrstr); 532 533 sc->sc_hwif = m->hwif; 534 sc->sc_quirks = m->quirks; 535 switch (sc->sc_hwif) { 536 case AAC_HWIF_I960RX: 537 AAC_DPRINTF(AAC_D_MISC, 538 ("set hardware up for i960Rx")); 539 sc->sc_if = aac_rx_interface; 540 break; 541 542 case AAC_HWIF_STRONGARM: 543 AAC_DPRINTF(AAC_D_MISC, 544 ("set hardware up for StrongARM")); 545 sc->sc_if = aac_sa_interface; 546 break; 547 548 case AAC_HWIF_RKT: 549 AAC_DPRINTF(AAC_D_MISC, 550 ("set hardware up for MIPS/Rocket")); 551 sc->sc_if = aac_rkt_interface; 552 break; 553 } 554 sc->sc_regsize = memsize; 555 sc->sc_intr_set = aac_pci_intr_set; 556 557 if (!aac_attach(sc)) 558 return; 559 560 bail_out: 561 if (state > 1) 562 pci_intr_disestablish(pc, sc->sc_ih); 563 if (state > 0) 564 bus_space_unmap(sc->sc_memt, sc->sc_memh, memsize); 565 } 566 567 CFATTACH_DECL(aac_pci, sizeof(struct aac_pci_softc), 568 aac_pci_match, aac_pci_attach, NULL, NULL); 569 570 /* 571 * Read the current firmware status word. 572 */ 573 static int 574 aac_sa_get_fwstatus(struct aac_softc *sc) 575 { 576 577 return (AAC_GETREG4(sc, AAC_SA_FWSTATUS)); 578 } 579 580 static int 581 aac_rx_get_fwstatus(struct aac_softc *sc) 582 { 583 584 return (AAC_GETREG4(sc, AAC_RX_FWSTATUS)); 585 } 586 587 static int 588 aac_rkt_get_fwstatus(struct aac_softc *sc) 589 { 590 591 return (AAC_GETREG4(sc, AAC_RKT_FWSTATUS)); 592 } 593 594 /* 595 * Notify the controller of a change in a given queue 596 */ 597 598 static void 599 aac_sa_qnotify(struct aac_softc *sc, int qbit) 600 { 601 602 AAC_SETREG2(sc, AAC_SA_DOORBELL1_SET, qbit); 603 } 604 605 static void 606 aac_rx_qnotify(struct aac_softc *sc, int qbit) 607 { 608 609 AAC_SETREG4(sc, AAC_RX_IDBR, qbit); 610 } 611 612 static void 613 aac_rkt_qnotify(struct aac_softc *sc, int qbit) 614 { 615 616 AAC_SETREG4(sc, AAC_RKT_IDBR, qbit); 617 } 618 619 /* 620 * Get the interrupt reason bits 621 */ 622 static int 623 aac_sa_get_istatus(struct aac_softc *sc) 624 { 625 626 return (AAC_GETREG2(sc, AAC_SA_DOORBELL0)); 627 } 628 629 static int 630 aac_rx_get_istatus(struct aac_softc *sc) 631 { 632 633 return (AAC_GETREG4(sc, AAC_RX_ODBR)); 634 } 635 636 static int 637 aac_rkt_get_istatus(struct aac_softc *sc) 638 { 639 640 return (AAC_GETREG4(sc, AAC_RKT_ODBR)); 641 } 642 643 /* 644 * Clear some interrupt reason bits 645 */ 646 static void 647 aac_sa_clear_istatus(struct aac_softc *sc, int mask) 648 { 649 650 AAC_SETREG2(sc, AAC_SA_DOORBELL0_CLEAR, mask); 651 } 652 653 static void 654 aac_rx_clear_istatus(struct aac_softc *sc, int mask) 655 { 656 657 AAC_SETREG4(sc, AAC_RX_ODBR, mask); 658 } 659 660 static void 661 aac_rkt_clear_istatus(struct aac_softc *sc, int mask) 662 { 663 664 AAC_SETREG4(sc, AAC_RKT_ODBR, mask); 665 } 666 667 /* 668 * Populate the mailbox and set the command word 669 */ 670 static void 671 aac_sa_set_mailbox(struct aac_softc *sc, u_int32_t command, 672 u_int32_t arg0, u_int32_t arg1, u_int32_t arg2, 673 u_int32_t arg3) 674 { 675 676 AAC_SETREG4(sc, AAC_SA_MAILBOX, command); 677 AAC_SETREG4(sc, AAC_SA_MAILBOX + 4, arg0); 678 AAC_SETREG4(sc, AAC_SA_MAILBOX + 8, arg1); 679 AAC_SETREG4(sc, AAC_SA_MAILBOX + 12, arg2); 680 AAC_SETREG4(sc, AAC_SA_MAILBOX + 16, arg3); 681 } 682 683 static void 684 aac_rx_set_mailbox(struct aac_softc *sc, u_int32_t command, 685 u_int32_t arg0, u_int32_t arg1, u_int32_t arg2, 686 u_int32_t arg3) 687 { 688 689 AAC_SETREG4(sc, AAC_RX_MAILBOX, command); 690 AAC_SETREG4(sc, AAC_RX_MAILBOX + 4, arg0); 691 AAC_SETREG4(sc, AAC_RX_MAILBOX + 8, arg1); 692 AAC_SETREG4(sc, AAC_RX_MAILBOX + 12, arg2); 693 AAC_SETREG4(sc, AAC_RX_MAILBOX + 16, arg3); 694 } 695 696 static void 697 aac_rkt_set_mailbox(struct aac_softc *sc, u_int32_t command, 698 u_int32_t arg0, u_int32_t arg1, u_int32_t arg2, 699 u_int32_t arg3) 700 { 701 702 AAC_SETREG4(sc, AAC_RKT_MAILBOX, command); 703 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 4, arg0); 704 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 8, arg1); 705 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 12, arg2); 706 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 16, arg3); 707 } 708 709 /* 710 * Fetch the specified mailbox 711 */ 712 static uint32_t 713 aac_sa_get_mailbox(struct aac_softc *sc, int mb) 714 { 715 716 return (AAC_GETREG4(sc, AAC_SA_MAILBOX + (mb * 4))); 717 } 718 719 static uint32_t 720 aac_rx_get_mailbox(struct aac_softc *sc, int mb) 721 { 722 723 return (AAC_GETREG4(sc, AAC_RX_MAILBOX + (mb * 4))); 724 } 725 726 static uint32_t 727 aac_rkt_get_mailbox(struct aac_softc *sc, int mb) 728 { 729 730 return (AAC_GETREG4(sc, AAC_RKT_MAILBOX + (mb * 4))); 731 } 732 733 /* 734 * Set/clear interrupt masks 735 */ 736 static void 737 aac_sa_set_interrupts(struct aac_softc *sc, int enable) 738 { 739 740 if (enable) 741 AAC_SETREG2((sc), AAC_SA_MASK0_CLEAR, AAC_DB_INTERRUPTS); 742 else 743 AAC_SETREG2((sc), AAC_SA_MASK0_SET, ~0); 744 } 745 746 static void 747 aac_rx_set_interrupts(struct aac_softc *sc, int enable) 748 { 749 750 if (enable) { 751 if (sc->sc_quirks & AAC_QUIRK_NEW_COMM) 752 AAC_SETREG4(sc, AAC_RX_OIMR, ~AAC_DB_INT_NEW_COMM); 753 else 754 AAC_SETREG4(sc, AAC_RX_OIMR, ~AAC_DB_INTERRUPTS); 755 } else { 756 AAC_SETREG4(sc, AAC_RX_OIMR, ~0); 757 } 758 } 759 760 static void 761 aac_rkt_set_interrupts(struct aac_softc *sc, int enable) 762 { 763 764 if (enable) { 765 if (sc->sc_quirks & AAC_QUIRK_NEW_COMM) 766 AAC_SETREG4(sc, AAC_RKT_OIMR, ~AAC_DB_INT_NEW_COMM); 767 else 768 AAC_SETREG4(sc, AAC_RKT_OIMR, ~AAC_DB_INTERRUPTS); 769 } else { 770 AAC_SETREG4(sc, AAC_RKT_OIMR, ~0); 771 } 772 } 773 774 /* 775 * New comm. interface: Send command functions 776 */ 777 static int 778 aac_rx_send_command(struct aac_softc *sc, struct aac_ccb *ac) 779 { 780 u_int32_t index, device; 781 782 index = AAC_GETREG4(sc, AAC_RX_IQUE); 783 if (index == 0xffffffffL) 784 index = AAC_GETREG4(sc, AAC_RX_IQUE); 785 if (index == 0xffffffffL) 786 return index; 787 #ifdef notyet 788 aac_enqueue_busy(ac); 789 #endif 790 device = index; 791 AAC_SETREG4(sc, device, 792 htole32((u_int32_t)(ac->ac_fibphys & 0xffffffffUL))); 793 device += 4; 794 if (sizeof(bus_addr_t) > 4) { 795 AAC_SETREG4(sc, device, 796 htole32((u_int32_t)((u_int64_t)ac->ac_fibphys >> 32))); 797 } else { 798 AAC_SETREG4(sc, device, 0); 799 } 800 device += 4; 801 AAC_SETREG4(sc, device, ac->ac_fib->Header.Size); 802 AAC_SETREG4(sc, AAC_RX_IQUE, index); 803 return 0; 804 } 805 806 static int 807 aac_rkt_send_command(struct aac_softc *sc, struct aac_ccb *ac) 808 { 809 u_int32_t index, device; 810 811 index = AAC_GETREG4(sc, AAC_RKT_IQUE); 812 if (index == 0xffffffffL) 813 index = AAC_GETREG4(sc, AAC_RKT_IQUE); 814 if (index == 0xffffffffL) 815 return index; 816 #ifdef notyet 817 aac_enqueue_busy(ac); 818 #endif 819 device = index; 820 AAC_SETREG4(sc, device, 821 htole32((u_int32_t)(ac->ac_fibphys & 0xffffffffUL))); 822 device += 4; 823 if (sizeof(bus_addr_t) > 4) { 824 AAC_SETREG4(sc, device, 825 htole32((u_int32_t)((u_int64_t)ac->ac_fibphys >> 32))); 826 } else { 827 AAC_SETREG4(sc, device, 0); 828 } 829 device += 4; 830 AAC_SETREG4(sc, device, ac->ac_fib->Header.Size); 831 AAC_SETREG4(sc, AAC_RKT_IQUE, index); 832 return 0; 833 } 834 835 /* 836 * New comm. interface: get, set outbound queue index 837 */ 838 static int 839 aac_rx_get_outb_queue(struct aac_softc *sc) 840 { 841 842 return AAC_GETREG4(sc, AAC_RX_OQUE); 843 } 844 845 static int 846 aac_rkt_get_outb_queue(struct aac_softc *sc) 847 { 848 849 return AAC_GETREG4(sc, AAC_RKT_OQUE); 850 } 851 852 static void 853 aac_rx_set_outb_queue(struct aac_softc *sc, int index) 854 { 855 856 AAC_SETREG4(sc, AAC_RX_OQUE, index); 857 } 858 859 static void 860 aac_rkt_set_outb_queue(struct aac_softc *sc, int index) 861 { 862 863 AAC_SETREG4(sc, AAC_RKT_OQUE, index); 864 } 865
Indexes created Wed Oct 01 19:09:53 GMT 2025