aac_pci.c revision 1.24
1 /* $NetBSD: aac_pci.c,v 1.24 2008/04/28 20:23:54 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 2000 Michael Smith 34 * Copyright (c) 2000 BSDi 35 * Copyright (c) 2000 Niklas Hallqvist 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 48 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 49 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 50 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 51 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 52 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 53 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 55 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 56 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 57 * SUCH DAMAGE. 58 * 59 * from FreeBSD: aac_pci.c,v 1.1 2000/09/13 03:20:34 msmith Exp 60 * via OpenBSD: aac_pci.c,v 1.7 2002/03/14 01:26:58 millert Exp 61 */ 62 63 /* 64 * PCI front-end for the `aac' driver. 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: aac_pci.c,v 1.24 2008/04/28 20:23:54 martin Exp $"); 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/device.h> 73 #include <sys/kernel.h> 74 #include <sys/malloc.h> 75 #include <sys/queue.h> 76 77 #include <sys/bus.h> 78 #include <machine/endian.h> 79 #include <sys/intr.h> 80 81 #include <dev/pci/pcidevs.h> 82 #include <dev/pci/pcireg.h> 83 #include <dev/pci/pcivar.h> 84 85 #include <dev/ic/aacreg.h> 86 #include <dev/ic/aacvar.h> 87 88 struct aac_pci_softc { 89 struct aac_softc sc_aac; 90 pci_chipset_tag_t sc_pc; 91 pci_intr_handle_t sc_ih; 92 }; 93 94 /* i960Rx interface */ 95 static int aac_rx_get_fwstatus(struct aac_softc *); 96 static void aac_rx_qnotify(struct aac_softc *, int); 97 static int aac_rx_get_istatus(struct aac_softc *); 98 static void aac_rx_clear_istatus(struct aac_softc *, int); 99 static void aac_rx_set_mailbox(struct aac_softc *, u_int32_t, u_int32_t, 100 u_int32_t, u_int32_t, u_int32_t); 101 static uint32_t aac_rx_get_mailbox(struct aac_softc *, int); 102 static void aac_rx_set_interrupts(struct aac_softc *, int); 103 static int aac_rx_send_command(struct aac_softc *, struct aac_ccb *); 104 static int aac_rx_get_outb_queue(struct aac_softc *); 105 static void aac_rx_set_outb_queue(struct aac_softc *, int); 106 107 /* StrongARM interface */ 108 static int aac_sa_get_fwstatus(struct aac_softc *); 109 static void aac_sa_qnotify(struct aac_softc *, int); 110 static int aac_sa_get_istatus(struct aac_softc *); 111 static void aac_sa_clear_istatus(struct aac_softc *, int); 112 static void aac_sa_set_mailbox(struct aac_softc *, u_int32_t, u_int32_t, 113 u_int32_t, u_int32_t, u_int32_t); 114 static uint32_t aac_sa_get_mailbox(struct aac_softc *, int); 115 static void aac_sa_set_interrupts(struct aac_softc *, int); 116 117 /* Rocket/MIPS interface */ 118 static int aac_rkt_get_fwstatus(struct aac_softc *); 119 static void aac_rkt_qnotify(struct aac_softc *, int); 120 static int aac_rkt_get_istatus(struct aac_softc *); 121 static void aac_rkt_clear_istatus(struct aac_softc *, int); 122 static void aac_rkt_set_mailbox(struct aac_softc *, u_int32_t, u_int32_t, 123 u_int32_t, u_int32_t, u_int32_t); 124 static uint32_t aac_rkt_get_mailbox(struct aac_softc *, int); 125 static void aac_rkt_set_interrupts(struct aac_softc *, int); 126 static int aac_rkt_send_command(struct aac_softc *, struct aac_ccb *); 127 static int aac_rkt_get_outb_queue(struct aac_softc *); 128 static void aac_rkt_set_outb_queue(struct aac_softc *, int); 129 130 static const struct aac_interface aac_rx_interface = { 131 aac_rx_get_fwstatus, 132 aac_rx_qnotify, 133 aac_rx_get_istatus, 134 aac_rx_clear_istatus, 135 aac_rx_set_mailbox, 136 aac_rx_get_mailbox, 137 aac_rx_set_interrupts, 138 aac_rx_send_command, 139 aac_rx_get_outb_queue, 140 aac_rx_set_outb_queue 141 }; 142 143 static const struct aac_interface aac_sa_interface = { 144 aac_sa_get_fwstatus, 145 aac_sa_qnotify, 146 aac_sa_get_istatus, 147 aac_sa_clear_istatus, 148 aac_sa_set_mailbox, 149 aac_sa_get_mailbox, 150 aac_sa_set_interrupts, 151 NULL, NULL, NULL 152 }; 153 154 static const struct aac_interface aac_rkt_interface = { 155 aac_rkt_get_fwstatus, 156 aac_rkt_qnotify, 157 aac_rkt_get_istatus, 158 aac_rkt_clear_istatus, 159 aac_rkt_set_mailbox, 160 aac_rkt_get_mailbox, 161 aac_rkt_set_interrupts, 162 aac_rkt_send_command, 163 aac_rkt_get_outb_queue, 164 aac_rkt_set_outb_queue 165 }; 166 167 static struct aac_ident { 168 u_short vendor; 169 u_short device; 170 u_short subvendor; 171 u_short subdevice; 172 u_short hwif; 173 u_short quirks; 174 const char *prodstr; 175 } const aac_ident[] = { 176 { 177 PCI_VENDOR_DELL, 178 PCI_PRODUCT_DELL_PERC_2SI, 179 PCI_VENDOR_DELL, 180 PCI_PRODUCT_DELL_PERC_2SI, 181 AAC_HWIF_I960RX, 182 0, 183 "Dell PERC 2/Si" 184 }, 185 { 186 PCI_VENDOR_DELL, 187 PCI_PRODUCT_DELL_PERC_3DI, 188 PCI_VENDOR_DELL, 189 PCI_PRODUCT_DELL_PERC_3DI, 190 AAC_HWIF_I960RX, 191 0, 192 "Dell PERC 3/Di" 193 }, 194 { 195 PCI_VENDOR_DELL, 196 PCI_PRODUCT_DELL_PERC_3DI, 197 PCI_VENDOR_DELL, 198 PCI_PRODUCT_DELL_PERC_3DI_SUB2, 199 AAC_HWIF_I960RX, 200 0, 201 "Dell PERC 3/Di" 202 }, 203 { 204 PCI_VENDOR_DELL, 205 PCI_PRODUCT_DELL_PERC_3DI, 206 PCI_VENDOR_DELL, 207 PCI_PRODUCT_DELL_PERC_3DI_SUB3, 208 AAC_HWIF_I960RX, 209 0, 210 "Dell PERC 3/Di" 211 }, 212 { 213 PCI_VENDOR_DELL, 214 PCI_PRODUCT_DELL_PERC_3DI_2, 215 PCI_VENDOR_DELL, 216 PCI_PRODUCT_DELL_PERC_3DI_2_SUB, 217 AAC_HWIF_I960RX, 218 0, 219 "Dell PERC 3/Di" 220 }, 221 { 222 PCI_VENDOR_DELL, 223 PCI_PRODUCT_DELL_PERC_3DI_3, 224 PCI_VENDOR_DELL, 225 PCI_PRODUCT_DELL_PERC_3DI_3_SUB, 226 AAC_HWIF_I960RX, 227 0, 228 "Dell PERC 3/Di" 229 }, 230 { 231 PCI_VENDOR_DELL, 232 PCI_PRODUCT_DELL_PERC_3DI_3, 233 PCI_VENDOR_DELL, 234 PCI_PRODUCT_DELL_PERC_3DI_3_SUB2, 235 AAC_HWIF_I960RX, 236 0, 237 "Dell PERC 3/Di" 238 }, 239 { 240 PCI_VENDOR_DELL, 241 PCI_PRODUCT_DELL_PERC_3DI_3, 242 PCI_VENDOR_DELL, 243 PCI_PRODUCT_DELL_PERC_3DI_3_SUB3, 244 AAC_HWIF_I960RX, 245 0, 246 "Dell PERC 3/Di" 247 }, 248 { 249 PCI_VENDOR_DELL, 250 PCI_PRODUCT_DELL_PERC_3SI, 251 PCI_VENDOR_DELL, 252 PCI_PRODUCT_DELL_PERC_3SI, 253 AAC_HWIF_I960RX, 254 0, 255 "Dell PERC 3/Si" 256 }, 257 { 258 PCI_VENDOR_DELL, 259 PCI_PRODUCT_DELL_PERC_3SI_2, 260 PCI_VENDOR_DELL, 261 PCI_PRODUCT_DELL_PERC_3SI_2_SUB, 262 AAC_HWIF_I960RX, 263 0, 264 "Dell PERC 3/Si" 265 }, 266 { 267 PCI_VENDOR_ADP2, 268 PCI_PRODUCT_ADP2_ASR2200S, 269 PCI_VENDOR_DELL, 270 PCI_PRODUCT_DELL_CERC_1_5, 271 AAC_HWIF_I960RX, 272 AAC_QUIRK_NO4GB, 273 "Dell CERC SATA RAID 1.5/6ch" 274 }, 275 { 276 PCI_VENDOR_ADP2, 277 PCI_PRODUCT_ADP2_AAC2622, 278 PCI_VENDOR_ADP2, 279 PCI_PRODUCT_ADP2_AAC2622, 280 AAC_HWIF_I960RX, 281 0, 282 "Adaptec ADP-2622" 283 }, 284 { 285 PCI_VENDOR_ADP2, 286 PCI_PRODUCT_ADP2_ASR2200S, 287 PCI_VENDOR_ADP2, 288 PCI_PRODUCT_ADP2_ASR2200S_SUB2M, 289 AAC_HWIF_I960RX, 290 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 291 "Adaptec ASR-2200S" 292 }, 293 { 294 PCI_VENDOR_ADP2, 295 PCI_PRODUCT_ADP2_ASR2200S, 296 PCI_VENDOR_DELL, 297 PCI_PRODUCT_ADP2_ASR2200S_SUB2M, 298 AAC_HWIF_I960RX, 299 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 300 "Dell PERC 320/DC" 301 }, 302 { 303 PCI_VENDOR_ADP2, 304 PCI_PRODUCT_ADP2_ASR2200S, 305 PCI_VENDOR_ADP2, 306 PCI_PRODUCT_ADP2_ASR2200S, 307 AAC_HWIF_I960RX, 308 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 309 "Adaptec ASR-2200S" 310 }, 311 { 312 PCI_VENDOR_ADP2, 313 PCI_PRODUCT_ADP2_ASR2200S, 314 PCI_VENDOR_ADP2, 315 PCI_PRODUCT_ADP2_AAR2810SA, 316 AAC_HWIF_I960RX, 317 AAC_QUIRK_NO4GB, 318 "Adaptec AAR-2810SA" 319 }, 320 { 321 PCI_VENDOR_ADP2, 322 PCI_PRODUCT_ADP2_ASR2200S, 323 PCI_VENDOR_ADP2, 324 PCI_PRODUCT_ADP2_ASR2120S, 325 AAC_HWIF_I960RX, 326 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 327 "Adaptec ASR-2120S" 328 }, 329 { 330 PCI_VENDOR_ADP2, 331 PCI_PRODUCT_ADP2_ASR2200S, 332 PCI_VENDOR_ADP2, 333 PCI_PRODUCT_ADP2_ASR2410SA, 334 AAC_HWIF_I960RX, 335 AAC_QUIRK_NO4GB, 336 "Adaptec ASR-2410SA" 337 }, 338 { 339 PCI_VENDOR_ADP2, 340 PCI_PRODUCT_ADP2_ASR2200S, 341 PCI_VENDOR_HP, 342 PCI_PRODUCT_ADP2_HP_M110_G2, 343 AAC_HWIF_I960RX, 344 AAC_QUIRK_NO4GB, 345 "HP ML110 G2 (Adaptec ASR-2610SA)" 346 }, 347 { 348 PCI_VENDOR_DEC, 349 PCI_PRODUCT_DEC_21554, 350 PCI_VENDOR_ADP2, 351 PCI_PRODUCT_ADP2_AAC364, 352 AAC_HWIF_STRONGARM, 353 0, 354 "Adaptec AAC-364" 355 }, 356 { 357 PCI_VENDOR_DEC, 358 PCI_PRODUCT_DEC_21554, 359 PCI_VENDOR_ADP2, 360 PCI_PRODUCT_ADP2_ASR5400S, 361 AAC_HWIF_STRONGARM, 362 AAC_QUIRK_BROKEN_MMAP, 363 "Adaptec ASR-5400S" 364 }, 365 { 366 PCI_VENDOR_DEC, 367 PCI_PRODUCT_DEC_21554, 368 PCI_VENDOR_ADP2, 369 PCI_PRODUCT_ADP2_PERC_2QC, 370 AAC_HWIF_STRONGARM, 371 AAC_QUIRK_PERC2QC, 372 "Dell PERC 2/QC" 373 }, 374 { 375 PCI_VENDOR_DEC, 376 PCI_PRODUCT_DEC_21554, 377 PCI_VENDOR_ADP2, 378 PCI_PRODUCT_ADP2_PERC_3QC, 379 AAC_HWIF_STRONGARM, 380 0, 381 "Dell PERC 3/QC" 382 }, 383 { 384 PCI_VENDOR_DEC, 385 PCI_PRODUCT_DEC_21554, 386 PCI_VENDOR_HP, 387 PCI_PRODUCT_HP_NETRAID_4M, 388 AAC_HWIF_STRONGARM, 389 0, 390 "HP NetRAID-4M" 391 }, 392 }; 393 394 static const struct aac_ident * 395 aac_find_ident(struct pci_attach_args *pa) 396 { 397 const struct aac_ident *m, *mm; 398 u_int32_t subsysid; 399 400 m = aac_ident; 401 mm = aac_ident + (sizeof(aac_ident) / sizeof(aac_ident[0])); 402 403 while (m < mm) { 404 if (m->vendor == PCI_VENDOR(pa->pa_id) && 405 m->device == PCI_PRODUCT(pa->pa_id)) { 406 subsysid = pci_conf_read(pa->pa_pc, pa->pa_tag, 407 PCI_SUBSYS_ID_REG); 408 if (m->subvendor == PCI_VENDOR(subsysid) && 409 m->subdevice == PCI_PRODUCT(subsysid)) 410 return (m); 411 } 412 m++; 413 } 414 415 return (NULL); 416 } 417 418 static int 419 aac_pci_intr_set(struct aac_softc *sc, int (*hand)(void*), void *arg) 420 { 421 struct aac_pci_softc *pcisc; 422 423 pcisc = (struct aac_pci_softc *) sc; 424 425 pci_intr_disestablish(pcisc->sc_pc, sc->sc_ih); 426 sc->sc_ih = pci_intr_establish(pcisc->sc_pc, pcisc->sc_ih, 427 IPL_BIO, hand, arg); 428 if (sc->sc_ih == NULL) { 429 return ENXIO; 430 } 431 return 0; 432 } 433 434 static int 435 aac_pci_match(struct device *parent, struct cfdata *match, 436 void *aux) 437 { 438 struct pci_attach_args *pa; 439 440 pa = aux; 441 442 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 443 return (0); 444 445 return (aac_find_ident(pa) != NULL); 446 } 447 448 static void 449 aac_pci_attach(struct device *parent, struct device *self, void *aux) 450 { 451 struct pci_attach_args *pa; 452 pci_chipset_tag_t pc; 453 struct aac_pci_softc *pcisc; 454 struct aac_softc *sc; 455 u_int16_t command; 456 bus_addr_t membase; 457 bus_size_t memsize; 458 const char *intrstr; 459 int state; 460 const struct aac_ident *m; 461 462 pa = aux; 463 pc = pa->pa_pc; 464 pcisc = (struct aac_pci_softc *)self; 465 pcisc->sc_pc = pc; 466 sc = &pcisc->sc_aac; 467 state = 0; 468 469 aprint_naive(": RAID controller\n"); 470 aprint_normal(": "); 471 472 /* 473 * Verify that the adapter is correctly set up in PCI space. 474 */ 475 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 476 command |= PCI_COMMAND_MASTER_ENABLE; 477 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 478 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 479 AAC_DPRINTF(AAC_D_MISC, ("pci command status reg 0x08x ")); 480 481 if ((command & PCI_COMMAND_MASTER_ENABLE) == 0) { 482 aprint_error("can't enable bus-master feature\n"); 483 goto bail_out; 484 } 485 486 if ((command & PCI_COMMAND_MEM_ENABLE) == 0) { 487 aprint_error("memory window not available\n"); 488 goto bail_out; 489 } 490 491 /* 492 * Map control/status registers. 493 */ 494 if (pci_mapreg_map(pa, PCI_MAPREG_START, 495 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_memt, 496 &sc->sc_memh, &membase, &memsize)) { 497 aprint_error("can't find mem space\n"); 498 goto bail_out; 499 } 500 state++; 501 502 if (pci_intr_map(pa, &pcisc->sc_ih)) { 503 aprint_error("couldn't map interrupt\n"); 504 goto bail_out; 505 } 506 intrstr = pci_intr_string(pc, pcisc->sc_ih); 507 sc->sc_ih = pci_intr_establish(pc, pcisc->sc_ih, IPL_BIO, aac_intr, sc); 508 if (sc->sc_ih == NULL) { 509 aprint_error("couldn't establish interrupt"); 510 if (intrstr != NULL) 511 aprint_normal(" at %s", intrstr); 512 aprint_normal("\n"); 513 goto bail_out; 514 } 515 state++; 516 517 sc->sc_dmat = pa->pa_dmat; 518 519 m = aac_find_ident(pa); 520 aprint_normal("%s\n", m->prodstr); 521 if (intrstr != NULL) 522 aprint_normal_dev(&sc->sc_dv, "interrupting at %s\n", 523 intrstr); 524 525 sc->sc_hwif = m->hwif; 526 sc->sc_quirks = m->quirks; 527 switch (sc->sc_hwif) { 528 case AAC_HWIF_I960RX: 529 AAC_DPRINTF(AAC_D_MISC, 530 ("set hardware up for i960Rx")); 531 sc->sc_if = aac_rx_interface; 532 break; 533 534 case AAC_HWIF_STRONGARM: 535 AAC_DPRINTF(AAC_D_MISC, 536 ("set hardware up for StrongARM")); 537 sc->sc_if = aac_sa_interface; 538 break; 539 540 case AAC_HWIF_RKT: 541 AAC_DPRINTF(AAC_D_MISC, 542 ("set hardware up for MIPS/Rocket")); 543 sc->sc_if = aac_rkt_interface; 544 break; 545 } 546 sc->sc_regsize = memsize; 547 sc->sc_intr_set = aac_pci_intr_set; 548 549 if (!aac_attach(sc)) 550 return; 551 552 bail_out: 553 if (state > 1) 554 pci_intr_disestablish(pc, sc->sc_ih); 555 if (state > 0) 556 bus_space_unmap(sc->sc_memt, sc->sc_memh, memsize); 557 } 558 559 CFATTACH_DECL(aac_pci, sizeof(struct aac_softc), 560 aac_pci_match, aac_pci_attach, NULL, NULL); 561 562 /* 563 * Read the current firmware status word. 564 */ 565 static int 566 aac_sa_get_fwstatus(struct aac_softc *sc) 567 { 568 569 return (AAC_GETREG4(sc, AAC_SA_FWSTATUS)); 570 } 571 572 static int 573 aac_rx_get_fwstatus(struct aac_softc *sc) 574 { 575 576 return (AAC_GETREG4(sc, AAC_RX_FWSTATUS)); 577 } 578 579 static int 580 aac_rkt_get_fwstatus(struct aac_softc *sc) 581 { 582 583 return (AAC_GETREG4(sc, AAC_RKT_FWSTATUS)); 584 } 585 586 /* 587 * Notify the controller of a change in a given queue 588 */ 589 590 static void 591 aac_sa_qnotify(struct aac_softc *sc, int qbit) 592 { 593 594 AAC_SETREG2(sc, AAC_SA_DOORBELL1_SET, qbit); 595 } 596 597 static void 598 aac_rx_qnotify(struct aac_softc *sc, int qbit) 599 { 600 601 AAC_SETREG4(sc, AAC_RX_IDBR, qbit); 602 } 603 604 static void 605 aac_rkt_qnotify(struct aac_softc *sc, int qbit) 606 { 607 608 AAC_SETREG4(sc, AAC_RKT_IDBR, qbit); 609 } 610 611 /* 612 * Get the interrupt reason bits 613 */ 614 static int 615 aac_sa_get_istatus(struct aac_softc *sc) 616 { 617 618 return (AAC_GETREG2(sc, AAC_SA_DOORBELL0)); 619 } 620 621 static int 622 aac_rx_get_istatus(struct aac_softc *sc) 623 { 624 625 return (AAC_GETREG4(sc, AAC_RX_ODBR)); 626 } 627 628 static int 629 aac_rkt_get_istatus(struct aac_softc *sc) 630 { 631 632 return (AAC_GETREG4(sc, AAC_RKT_ODBR)); 633 } 634 635 /* 636 * Clear some interrupt reason bits 637 */ 638 static void 639 aac_sa_clear_istatus(struct aac_softc *sc, int mask) 640 { 641 642 AAC_SETREG2(sc, AAC_SA_DOORBELL0_CLEAR, mask); 643 } 644 645 static void 646 aac_rx_clear_istatus(struct aac_softc *sc, int mask) 647 { 648 649 AAC_SETREG4(sc, AAC_RX_ODBR, mask); 650 } 651 652 static void 653 aac_rkt_clear_istatus(struct aac_softc *sc, int mask) 654 { 655 656 AAC_SETREG4(sc, AAC_RKT_ODBR, mask); 657 } 658 659 /* 660 * Populate the mailbox and set the command word 661 */ 662 static void 663 aac_sa_set_mailbox(struct aac_softc *sc, u_int32_t command, 664 u_int32_t arg0, u_int32_t arg1, u_int32_t arg2, 665 u_int32_t arg3) 666 { 667 668 AAC_SETREG4(sc, AAC_SA_MAILBOX, command); 669 AAC_SETREG4(sc, AAC_SA_MAILBOX + 4, arg0); 670 AAC_SETREG4(sc, AAC_SA_MAILBOX + 8, arg1); 671 AAC_SETREG4(sc, AAC_SA_MAILBOX + 12, arg2); 672 AAC_SETREG4(sc, AAC_SA_MAILBOX + 16, arg3); 673 } 674 675 static void 676 aac_rx_set_mailbox(struct aac_softc *sc, u_int32_t command, 677 u_int32_t arg0, u_int32_t arg1, u_int32_t arg2, 678 u_int32_t arg3) 679 { 680 681 AAC_SETREG4(sc, AAC_RX_MAILBOX, command); 682 AAC_SETREG4(sc, AAC_RX_MAILBOX + 4, arg0); 683 AAC_SETREG4(sc, AAC_RX_MAILBOX + 8, arg1); 684 AAC_SETREG4(sc, AAC_RX_MAILBOX + 12, arg2); 685 AAC_SETREG4(sc, AAC_RX_MAILBOX + 16, arg3); 686 } 687 688 static void 689 aac_rkt_set_mailbox(struct aac_softc *sc, u_int32_t command, 690 u_int32_t arg0, u_int32_t arg1, u_int32_t arg2, 691 u_int32_t arg3) 692 { 693 694 AAC_SETREG4(sc, AAC_RKT_MAILBOX, command); 695 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 4, arg0); 696 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 8, arg1); 697 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 12, arg2); 698 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 16, arg3); 699 } 700 701 /* 702 * Fetch the specified mailbox 703 */ 704 static uint32_t 705 aac_sa_get_mailbox(struct aac_softc *sc, int mb) 706 { 707 708 return (AAC_GETREG4(sc, AAC_SA_MAILBOX + (mb * 4))); 709 } 710 711 static uint32_t 712 aac_rx_get_mailbox(struct aac_softc *sc, int mb) 713 { 714 715 return (AAC_GETREG4(sc, AAC_RX_MAILBOX + (mb * 4))); 716 } 717 718 static uint32_t 719 aac_rkt_get_mailbox(struct aac_softc *sc, int mb) 720 { 721 722 return (AAC_GETREG4(sc, AAC_RKT_MAILBOX + (mb * 4))); 723 } 724 725 /* 726 * Set/clear interrupt masks 727 */ 728 static void 729 aac_sa_set_interrupts(struct aac_softc *sc, int enable) 730 { 731 732 if (enable) 733 AAC_SETREG2((sc), AAC_SA_MASK0_CLEAR, AAC_DB_INTERRUPTS); 734 else 735 AAC_SETREG2((sc), AAC_SA_MASK0_SET, ~0); 736 } 737 738 static void 739 aac_rx_set_interrupts(struct aac_softc *sc, int enable) 740 { 741 742 if (enable) { 743 if (sc->sc_quirks & AAC_QUIRK_NEW_COMM) 744 AAC_SETREG4(sc, AAC_RX_OIMR, ~AAC_DB_INT_NEW_COMM); 745 else 746 AAC_SETREG4(sc, AAC_RX_OIMR, ~AAC_DB_INTERRUPTS); 747 } else { 748 AAC_SETREG4(sc, AAC_RX_OIMR, ~0); 749 } 750 } 751 752 static void 753 aac_rkt_set_interrupts(struct aac_softc *sc, int enable) 754 { 755 756 if (enable) { 757 if (sc->sc_quirks & AAC_QUIRK_NEW_COMM) 758 AAC_SETREG4(sc, AAC_RKT_OIMR, ~AAC_DB_INT_NEW_COMM); 759 else 760 AAC_SETREG4(sc, AAC_RKT_OIMR, ~AAC_DB_INTERRUPTS); 761 } else { 762 AAC_SETREG4(sc, AAC_RKT_OIMR, ~0); 763 } 764 } 765 766 /* 767 * New comm. interface: Send command functions 768 */ 769 static int 770 aac_rx_send_command(struct aac_softc *sc, struct aac_ccb *ac) 771 { 772 u_int32_t index, device; 773 774 index = AAC_GETREG4(sc, AAC_RX_IQUE); 775 if (index == 0xffffffffL) 776 index = AAC_GETREG4(sc, AAC_RX_IQUE); 777 if (index == 0xffffffffL) 778 return index; 779 #ifdef notyet 780 aac_enqueue_busy(ac); 781 #endif 782 device = index; 783 AAC_SETREG4(sc, device, 784 htole32((u_int32_t)(ac->ac_fibphys & 0xffffffffUL))); 785 device += 4; 786 if (sizeof(bus_addr_t) > 4) { 787 AAC_SETREG4(sc, device, 788 htole32((u_int32_t)((u_int64_t)ac->ac_fibphys >> 32))); 789 } else { 790 AAC_SETREG4(sc, device, 0); 791 } 792 device += 4; 793 AAC_SETREG4(sc, device, ac->ac_fib->Header.Size); 794 AAC_SETREG4(sc, AAC_RX_IQUE, index); 795 return 0; 796 } 797 798 static int 799 aac_rkt_send_command(struct aac_softc *sc, struct aac_ccb *ac) 800 { 801 u_int32_t index, device; 802 803 index = AAC_GETREG4(sc, AAC_RKT_IQUE); 804 if (index == 0xffffffffL) 805 index = AAC_GETREG4(sc, AAC_RKT_IQUE); 806 if (index == 0xffffffffL) 807 return index; 808 #ifdef notyet 809 aac_enqueue_busy(ac); 810 #endif 811 device = index; 812 AAC_SETREG4(sc, device, 813 htole32((u_int32_t)(ac->ac_fibphys & 0xffffffffUL))); 814 device += 4; 815 if (sizeof(bus_addr_t) > 4) { 816 AAC_SETREG4(sc, device, 817 htole32((u_int32_t)((u_int64_t)ac->ac_fibphys >> 32))); 818 } else { 819 AAC_SETREG4(sc, device, 0); 820 } 821 device += 4; 822 AAC_SETREG4(sc, device, ac->ac_fib->Header.Size); 823 AAC_SETREG4(sc, AAC_RKT_IQUE, index); 824 return 0; 825 } 826 827 /* 828 * New comm. interface: get, set outbound queue index 829 */ 830 static int 831 aac_rx_get_outb_queue(struct aac_softc *sc) 832 { 833 834 return AAC_GETREG4(sc, AAC_RX_OQUE); 835 } 836 837 static int 838 aac_rkt_get_outb_queue(struct aac_softc *sc) 839 { 840 841 return AAC_GETREG4(sc, AAC_RKT_OQUE); 842 } 843 844 static void 845 aac_rx_set_outb_queue(struct aac_softc *sc, int index) 846 { 847 848 AAC_SETREG4(sc, AAC_RX_OQUE, index); 849 } 850 851 static void 852 aac_rkt_set_outb_queue(struct aac_softc *sc, int index) 853 { 854 855 AAC_SETREG4(sc, AAC_RKT_OQUE, index); 856 } 857
Indexes created Wed Oct 01 19:09:53 GMT 2025