aac_pci.c revision 1.34
1 /* $NetBSD: aac_pci.c,v 1.34 2012/09/23 01:10:59 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 2000 Michael Smith 34 * Copyright (c) 2000 BSDi 35 * Copyright (c) 2000 Niklas Hallqvist 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 48 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 49 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 50 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 51 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 52 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 53 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 55 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 56 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 57 * SUCH DAMAGE. 58 * 59 * from FreeBSD: aac_pci.c,v 1.1 2000/09/13 03:20:34 msmith Exp 60 * via OpenBSD: aac_pci.c,v 1.7 2002/03/14 01:26:58 millert Exp 61 */ 62 63 /* 64 * PCI front-end for the `aac' driver. 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: aac_pci.c,v 1.34 2012/09/23 01:10:59 chs Exp $"); 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/device.h> 73 #include <sys/kernel.h> 74 #include <sys/malloc.h> 75 #include <sys/queue.h> 76 77 #include <sys/bus.h> 78 #include <machine/endian.h> 79 #include <sys/intr.h> 80 81 #include <dev/pci/pcidevs.h> 82 #include <dev/pci/pcireg.h> 83 #include <dev/pci/pcivar.h> 84 85 #include <dev/ic/aacreg.h> 86 #include <dev/ic/aacvar.h> 87 88 struct aac_pci_softc { 89 struct aac_softc sc_aac; 90 pci_chipset_tag_t sc_pc; 91 pci_intr_handle_t sc_ih; 92 }; 93 94 /* i960Rx interface */ 95 static int aac_rx_get_fwstatus(struct aac_softc *); 96 static void aac_rx_qnotify(struct aac_softc *, int); 97 static int aac_rx_get_istatus(struct aac_softc *); 98 static void aac_rx_clear_istatus(struct aac_softc *, int); 99 static void aac_rx_set_mailbox(struct aac_softc *, u_int32_t, u_int32_t, 100 u_int32_t, u_int32_t, u_int32_t); 101 static uint32_t aac_rx_get_mailbox(struct aac_softc *, int); 102 static void aac_rx_set_interrupts(struct aac_softc *, int); 103 static int aac_rx_send_command(struct aac_softc *, struct aac_ccb *); 104 static int aac_rx_get_outb_queue(struct aac_softc *); 105 static void aac_rx_set_outb_queue(struct aac_softc *, int); 106 107 /* StrongARM interface */ 108 static int aac_sa_get_fwstatus(struct aac_softc *); 109 static void aac_sa_qnotify(struct aac_softc *, int); 110 static int aac_sa_get_istatus(struct aac_softc *); 111 static void aac_sa_clear_istatus(struct aac_softc *, int); 112 static void aac_sa_set_mailbox(struct aac_softc *, u_int32_t, u_int32_t, 113 u_int32_t, u_int32_t, u_int32_t); 114 static uint32_t aac_sa_get_mailbox(struct aac_softc *, int); 115 static void aac_sa_set_interrupts(struct aac_softc *, int); 116 117 /* Rocket/MIPS interface */ 118 static int aac_rkt_get_fwstatus(struct aac_softc *); 119 static void aac_rkt_qnotify(struct aac_softc *, int); 120 static int aac_rkt_get_istatus(struct aac_softc *); 121 static void aac_rkt_clear_istatus(struct aac_softc *, int); 122 static void aac_rkt_set_mailbox(struct aac_softc *, u_int32_t, u_int32_t, 123 u_int32_t, u_int32_t, u_int32_t); 124 static uint32_t aac_rkt_get_mailbox(struct aac_softc *, int); 125 static void aac_rkt_set_interrupts(struct aac_softc *, int); 126 static int aac_rkt_send_command(struct aac_softc *, struct aac_ccb *); 127 static int aac_rkt_get_outb_queue(struct aac_softc *); 128 static void aac_rkt_set_outb_queue(struct aac_softc *, int); 129 130 static const struct aac_interface aac_rx_interface = { 131 aac_rx_get_fwstatus, 132 aac_rx_qnotify, 133 aac_rx_get_istatus, 134 aac_rx_clear_istatus, 135 aac_rx_set_mailbox, 136 aac_rx_get_mailbox, 137 aac_rx_set_interrupts, 138 aac_rx_send_command, 139 aac_rx_get_outb_queue, 140 aac_rx_set_outb_queue 141 }; 142 143 static const struct aac_interface aac_sa_interface = { 144 aac_sa_get_fwstatus, 145 aac_sa_qnotify, 146 aac_sa_get_istatus, 147 aac_sa_clear_istatus, 148 aac_sa_set_mailbox, 149 aac_sa_get_mailbox, 150 aac_sa_set_interrupts, 151 NULL, NULL, NULL 152 }; 153 154 static const struct aac_interface aac_rkt_interface = { 155 aac_rkt_get_fwstatus, 156 aac_rkt_qnotify, 157 aac_rkt_get_istatus, 158 aac_rkt_clear_istatus, 159 aac_rkt_set_mailbox, 160 aac_rkt_get_mailbox, 161 aac_rkt_set_interrupts, 162 aac_rkt_send_command, 163 aac_rkt_get_outb_queue, 164 aac_rkt_set_outb_queue 165 }; 166 167 static struct aac_ident { 168 u_short vendor; 169 u_short device; 170 u_short subvendor; 171 u_short subdevice; 172 u_short hwif; 173 u_short quirks; 174 const char *prodstr; 175 } const aac_ident[] = { 176 { 177 PCI_VENDOR_DELL, 178 PCI_PRODUCT_DELL_PERC_2SI, 179 PCI_VENDOR_DELL, 180 PCI_PRODUCT_DELL_PERC_2SI, 181 AAC_HWIF_I960RX, 182 0, 183 "Dell PERC 2/Si" 184 }, 185 { 186 PCI_VENDOR_DELL, 187 PCI_PRODUCT_DELL_PERC_3DI, 188 PCI_VENDOR_DELL, 189 PCI_PRODUCT_DELL_PERC_3DI, 190 AAC_HWIF_I960RX, 191 0, 192 "Dell PERC 3/Di" 193 }, 194 { 195 PCI_VENDOR_DELL, 196 PCI_PRODUCT_DELL_PERC_3DI, 197 PCI_VENDOR_DELL, 198 PCI_PRODUCT_DELL_PERC_3DI_SUB2, 199 AAC_HWIF_I960RX, 200 0, 201 "Dell PERC 3/Di" 202 }, 203 { 204 PCI_VENDOR_DELL, 205 PCI_PRODUCT_DELL_PERC_3DI, 206 PCI_VENDOR_DELL, 207 PCI_PRODUCT_DELL_PERC_3DI_SUB3, 208 AAC_HWIF_I960RX, 209 0, 210 "Dell PERC 3/Di" 211 }, 212 { 213 PCI_VENDOR_DELL, 214 PCI_PRODUCT_DELL_PERC_3DI_2, 215 PCI_VENDOR_DELL, 216 PCI_PRODUCT_DELL_PERC_3DI_2_SUB, 217 AAC_HWIF_I960RX, 218 0, 219 "Dell PERC 3/Di" 220 }, 221 { 222 PCI_VENDOR_DELL, 223 PCI_PRODUCT_DELL_PERC_3DI_3, 224 PCI_VENDOR_DELL, 225 PCI_PRODUCT_DELL_PERC_3DI_3_SUB, 226 AAC_HWIF_I960RX, 227 0, 228 "Dell PERC 3/Di" 229 }, 230 { 231 PCI_VENDOR_DELL, 232 PCI_PRODUCT_DELL_PERC_3DI_3, 233 PCI_VENDOR_DELL, 234 PCI_PRODUCT_DELL_PERC_3DI_3_SUB2, 235 AAC_HWIF_I960RX, 236 0, 237 "Dell PERC 3/Di" 238 }, 239 { 240 PCI_VENDOR_DELL, 241 PCI_PRODUCT_DELL_PERC_3DI_3, 242 PCI_VENDOR_DELL, 243 PCI_PRODUCT_DELL_PERC_3DI_3_SUB3, 244 AAC_HWIF_I960RX, 245 0, 246 "Dell PERC 3/Di" 247 }, 248 { 249 PCI_VENDOR_DELL, 250 PCI_PRODUCT_DELL_PERC_3SI, 251 PCI_VENDOR_DELL, 252 PCI_PRODUCT_DELL_PERC_3SI, 253 AAC_HWIF_I960RX, 254 0, 255 "Dell PERC 3/Si" 256 }, 257 { 258 PCI_VENDOR_DELL, 259 PCI_PRODUCT_DELL_PERC_3SI_2, 260 PCI_VENDOR_DELL, 261 PCI_PRODUCT_DELL_PERC_3SI_2_SUB, 262 AAC_HWIF_I960RX, 263 0, 264 "Dell PERC 3/Si" 265 }, 266 { 267 PCI_VENDOR_ADP2, 268 PCI_PRODUCT_ADP2_ASR2200S, 269 PCI_VENDOR_DELL, 270 PCI_PRODUCT_DELL_CERC_1_5, 271 AAC_HWIF_I960RX, 272 AAC_QUIRK_NO4GB, 273 "Dell CERC SATA RAID 1.5/6ch" 274 }, 275 { 276 PCI_VENDOR_ADP2, 277 PCI_PRODUCT_ADP2_AAC2622, 278 PCI_VENDOR_ADP2, 279 PCI_PRODUCT_ADP2_AAC2622, 280 AAC_HWIF_I960RX, 281 0, 282 "Adaptec ADP-2622" 283 }, 284 { 285 PCI_VENDOR_ADP2, 286 PCI_PRODUCT_ADP2_ASR2200S, 287 PCI_VENDOR_ADP2, 288 PCI_PRODUCT_ADP2_ASR2200S_SUB2M, 289 AAC_HWIF_I960RX, 290 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 291 "Adaptec ASR-2200S" 292 }, 293 { 294 PCI_VENDOR_ADP2, 295 PCI_PRODUCT_ADP2_ASR2200S, 296 PCI_VENDOR_DELL, 297 PCI_PRODUCT_ADP2_ASR2200S_SUB2M, 298 AAC_HWIF_I960RX, 299 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 300 "Dell PERC 320/DC" 301 }, 302 { 303 PCI_VENDOR_ADP2, 304 PCI_PRODUCT_ADP2_ASR2200S, 305 PCI_VENDOR_ADP2, 306 PCI_PRODUCT_ADP2_ASR2200S, 307 AAC_HWIF_I960RX, 308 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 309 "Adaptec ASR-2200S" 310 }, 311 { 312 PCI_VENDOR_ADP2, 313 PCI_PRODUCT_ADP2_ASR2200S, 314 PCI_VENDOR_ADP2, 315 PCI_PRODUCT_ADP2_AAR2810SA, 316 AAC_HWIF_I960RX, 317 AAC_QUIRK_NO4GB, 318 "Adaptec AAR-2810SA" 319 }, 320 { 321 PCI_VENDOR_ADP2, 322 PCI_PRODUCT_ADP2_ASR2200S, 323 PCI_VENDOR_ADP2, 324 PCI_PRODUCT_ADP2_ASR2120S, 325 AAC_HWIF_I960RX, 326 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 327 "Adaptec ASR-2120S" 328 }, 329 { 330 PCI_VENDOR_ADP2, 331 PCI_PRODUCT_ADP2_ASR2200S, 332 PCI_VENDOR_ADP2, 333 PCI_PRODUCT_ADP2_ASR2410SA, 334 AAC_HWIF_I960RX, 335 AAC_QUIRK_NO4GB, 336 "Adaptec ASR-2410SA" 337 }, 338 { 339 PCI_VENDOR_ADP2, 340 PCI_PRODUCT_ADP2_ASR2200S, 341 PCI_VENDOR_HP, 342 PCI_PRODUCT_ADP2_HP_M110_G2, 343 AAC_HWIF_I960RX, 344 AAC_QUIRK_NO4GB, 345 "HP ML110 G2 (Adaptec ASR-2610SA)" 346 }, 347 { 348 PCI_VENDOR_ADP2, 349 PCI_PRODUCT_ADP2_ASR2120S, 350 PCI_VENDOR_IBM, 351 PCI_PRODUCT_IBM_SERVERAID8K, 352 AAC_HWIF_RKT, 353 0, 354 "IBM ServeRAID 8k" 355 }, 356 { PCI_VENDOR_ADP2, 357 PCI_PRODUCT_ADP2_ASR2200S, 358 PCI_VENDOR_ADP2, 359 PCI_PRODUCT_ADP2_2405, 360 AAC_HWIF_I960RX, 361 0, 362 "Adaptec RAID 2405" 363 }, 364 { PCI_VENDOR_ADP2, 365 PCI_PRODUCT_ADP2_ASR2200S, 366 PCI_VENDOR_ADP2, 367 PCI_PRODUCT_ADP2_3405, 368 AAC_HWIF_I960RX, 369 0, 370 "Adaptec RAID 3405" 371 }, 372 { PCI_VENDOR_ADP2, 373 PCI_PRODUCT_ADP2_ASR2200S, 374 PCI_VENDOR_ADP2, 375 PCI_PRODUCT_ADP2_3805, 376 AAC_HWIF_I960RX, 377 0, 378 "Adaptec RAID 3805" 379 }, 380 { 381 PCI_VENDOR_DEC, 382 PCI_PRODUCT_DEC_21554, 383 PCI_VENDOR_ADP2, 384 PCI_PRODUCT_ADP2_AAC364, 385 AAC_HWIF_STRONGARM, 386 0, 387 "Adaptec AAC-364" 388 }, 389 { 390 PCI_VENDOR_DEC, 391 PCI_PRODUCT_DEC_21554, 392 PCI_VENDOR_ADP2, 393 PCI_PRODUCT_ADP2_ASR5400S, 394 AAC_HWIF_STRONGARM, 395 AAC_QUIRK_BROKEN_MMAP, 396 "Adaptec ASR-5400S" 397 }, 398 { 399 PCI_VENDOR_DEC, 400 PCI_PRODUCT_DEC_21554, 401 PCI_VENDOR_ADP2, 402 PCI_PRODUCT_ADP2_PERC_2QC, 403 AAC_HWIF_STRONGARM, 404 AAC_QUIRK_PERC2QC, 405 "Dell PERC 2/QC" 406 }, 407 { 408 PCI_VENDOR_DEC, 409 PCI_PRODUCT_DEC_21554, 410 PCI_VENDOR_ADP2, 411 PCI_PRODUCT_ADP2_PERC_3QC, 412 AAC_HWIF_STRONGARM, 413 0, 414 "Dell PERC 3/QC" 415 }, 416 { 417 PCI_VENDOR_DEC, 418 PCI_PRODUCT_DEC_21554, 419 PCI_VENDOR_HP, 420 PCI_PRODUCT_HP_NETRAID_4M, 421 AAC_HWIF_STRONGARM, 422 0, 423 "HP NetRAID-4M" 424 }, 425 { 426 PCI_VENDOR_ADP2, 427 PCI_PRODUCT_ADP2_ASR2200S, 428 PCI_VENDOR_SUN, 429 PCI_PRODUCT_ADP2_ASR2120S, 430 AAC_HWIF_I960RX, 431 0, 432 "SG-XPCIESAS-R-IN" 433 }, 434 }; 435 436 static const struct aac_ident * 437 aac_find_ident(struct pci_attach_args *pa) 438 { 439 const struct aac_ident *m, *mm; 440 u_int32_t subsysid; 441 442 m = aac_ident; 443 mm = aac_ident + (sizeof(aac_ident) / sizeof(aac_ident[0])); 444 445 while (m < mm) { 446 if (m->vendor == PCI_VENDOR(pa->pa_id) && 447 m->device == PCI_PRODUCT(pa->pa_id)) { 448 subsysid = pci_conf_read(pa->pa_pc, pa->pa_tag, 449 PCI_SUBSYS_ID_REG); 450 if (m->subvendor == PCI_VENDOR(subsysid) && 451 m->subdevice == PCI_PRODUCT(subsysid)) 452 return (m); 453 } 454 m++; 455 } 456 457 return (NULL); 458 } 459 460 static int 461 aac_pci_intr_set(struct aac_softc *sc, int (*hand)(void*), void *arg) 462 { 463 struct aac_pci_softc *pcisc; 464 465 pcisc = (struct aac_pci_softc *) sc; 466 467 pci_intr_disestablish(pcisc->sc_pc, sc->sc_ih); 468 sc->sc_ih = pci_intr_establish(pcisc->sc_pc, pcisc->sc_ih, 469 IPL_BIO, hand, arg); 470 if (sc->sc_ih == NULL) { 471 return ENXIO; 472 } 473 return 0; 474 } 475 476 static int 477 aac_pci_match(device_t parent, cfdata_t match, void *aux) 478 { 479 struct pci_attach_args *pa; 480 481 pa = aux; 482 483 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 484 return (0); 485 486 return (aac_find_ident(pa) != NULL); 487 } 488 489 static void 490 aac_pci_attach(device_t parent, device_t self, void *aux) 491 { 492 struct pci_attach_args *pa; 493 pci_chipset_tag_t pc; 494 struct aac_pci_softc *pcisc; 495 struct aac_softc *sc; 496 u_int16_t command; 497 bus_addr_t membase; 498 bus_size_t memsize; 499 const char *intrstr; 500 int state; 501 const struct aac_ident *m; 502 503 pa = aux; 504 pc = pa->pa_pc; 505 pcisc = device_private(self); 506 pcisc->sc_pc = pc; 507 sc = &pcisc->sc_aac; 508 state = 0; 509 510 aprint_naive(": RAID controller\n"); 511 aprint_normal(": "); 512 513 /* 514 * Verify that the adapter is correctly set up in PCI space. 515 */ 516 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 517 command |= PCI_COMMAND_MASTER_ENABLE; 518 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 519 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 520 AAC_DPRINTF(AAC_D_MISC, ("pci command status reg 0x08x ")); 521 522 if ((command & PCI_COMMAND_MASTER_ENABLE) == 0) { 523 aprint_error("can't enable bus-master feature\n"); 524 goto bail_out; 525 } 526 527 if ((command & PCI_COMMAND_MEM_ENABLE) == 0) { 528 aprint_error("memory window not available\n"); 529 goto bail_out; 530 } 531 532 /* 533 * Map control/status registers. 534 */ 535 if (pci_mapreg_map(pa, PCI_MAPREG_START, 536 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_memt, 537 &sc->sc_memh, &membase, &memsize)) { 538 aprint_error("can't find mem space\n"); 539 goto bail_out; 540 } 541 state++; 542 543 if (pci_intr_map(pa, &pcisc->sc_ih)) { 544 aprint_error("couldn't map interrupt\n"); 545 goto bail_out; 546 } 547 intrstr = pci_intr_string(pc, pcisc->sc_ih); 548 sc->sc_ih = pci_intr_establish(pc, pcisc->sc_ih, IPL_BIO, aac_intr, sc); 549 if (sc->sc_ih == NULL) { 550 aprint_error("couldn't establish interrupt"); 551 if (intrstr != NULL) 552 aprint_error(" at %s", intrstr); 553 aprint_error("\n"); 554 goto bail_out; 555 } 556 state++; 557 558 sc->sc_dmat = pa->pa_dmat; 559 560 m = aac_find_ident(pa); 561 aprint_normal("%s\n", m->prodstr); 562 if (intrstr != NULL) 563 aprint_normal_dev(&sc->sc_dv, "interrupting at %s\n", 564 intrstr); 565 566 sc->sc_hwif = m->hwif; 567 sc->sc_quirks = m->quirks; 568 switch (sc->sc_hwif) { 569 case AAC_HWIF_I960RX: 570 AAC_DPRINTF(AAC_D_MISC, 571 ("set hardware up for i960Rx")); 572 sc->sc_if = aac_rx_interface; 573 break; 574 575 case AAC_HWIF_STRONGARM: 576 AAC_DPRINTF(AAC_D_MISC, 577 ("set hardware up for StrongARM")); 578 sc->sc_if = aac_sa_interface; 579 break; 580 581 case AAC_HWIF_RKT: 582 AAC_DPRINTF(AAC_D_MISC, 583 ("set hardware up for MIPS/Rocket")); 584 sc->sc_if = aac_rkt_interface; 585 break; 586 } 587 sc->sc_regsize = memsize; 588 sc->sc_intr_set = aac_pci_intr_set; 589 590 if (!aac_attach(sc)) 591 return; 592 593 bail_out: 594 if (state > 1) 595 pci_intr_disestablish(pc, sc->sc_ih); 596 if (state > 0) 597 bus_space_unmap(sc->sc_memt, sc->sc_memh, memsize); 598 } 599 600 CFATTACH_DECL(aac_pci, sizeof(struct aac_pci_softc), 601 aac_pci_match, aac_pci_attach, NULL, NULL); 602 603 /* 604 * Read the current firmware status word. 605 */ 606 static int 607 aac_sa_get_fwstatus(struct aac_softc *sc) 608 { 609 610 return (AAC_GETREG4(sc, AAC_SA_FWSTATUS)); 611 } 612 613 static int 614 aac_rx_get_fwstatus(struct aac_softc *sc) 615 { 616 617 return (AAC_GETREG4(sc, AAC_RX_FWSTATUS)); 618 } 619 620 static int 621 aac_rkt_get_fwstatus(struct aac_softc *sc) 622 { 623 624 return (AAC_GETREG4(sc, AAC_RKT_FWSTATUS)); 625 } 626 627 /* 628 * Notify the controller of a change in a given queue 629 */ 630 631 static void 632 aac_sa_qnotify(struct aac_softc *sc, int qbit) 633 { 634 635 AAC_SETREG2(sc, AAC_SA_DOORBELL1_SET, qbit); 636 } 637 638 static void 639 aac_rx_qnotify(struct aac_softc *sc, int qbit) 640 { 641 642 AAC_SETREG4(sc, AAC_RX_IDBR, qbit); 643 } 644 645 static void 646 aac_rkt_qnotify(struct aac_softc *sc, int qbit) 647 { 648 649 AAC_SETREG4(sc, AAC_RKT_IDBR, qbit); 650 } 651 652 /* 653 * Get the interrupt reason bits 654 */ 655 static int 656 aac_sa_get_istatus(struct aac_softc *sc) 657 { 658 659 return (AAC_GETREG2(sc, AAC_SA_DOORBELL0)); 660 } 661 662 static int 663 aac_rx_get_istatus(struct aac_softc *sc) 664 { 665 666 return (AAC_GETREG4(sc, AAC_RX_ODBR)); 667 } 668 669 static int 670 aac_rkt_get_istatus(struct aac_softc *sc) 671 { 672 673 return (AAC_GETREG4(sc, AAC_RKT_ODBR)); 674 } 675 676 /* 677 * Clear some interrupt reason bits 678 */ 679 static void 680 aac_sa_clear_istatus(struct aac_softc *sc, int mask) 681 { 682 683 AAC_SETREG2(sc, AAC_SA_DOORBELL0_CLEAR, mask); 684 } 685 686 static void 687 aac_rx_clear_istatus(struct aac_softc *sc, int mask) 688 { 689 690 AAC_SETREG4(sc, AAC_RX_ODBR, mask); 691 } 692 693 static void 694 aac_rkt_clear_istatus(struct aac_softc *sc, int mask) 695 { 696 697 AAC_SETREG4(sc, AAC_RKT_ODBR, mask); 698 } 699 700 /* 701 * Populate the mailbox and set the command word 702 */ 703 static void 704 aac_sa_set_mailbox(struct aac_softc *sc, u_int32_t command, 705 u_int32_t arg0, u_int32_t arg1, u_int32_t arg2, 706 u_int32_t arg3) 707 { 708 709 AAC_SETREG4(sc, AAC_SA_MAILBOX, command); 710 AAC_SETREG4(sc, AAC_SA_MAILBOX + 4, arg0); 711 AAC_SETREG4(sc, AAC_SA_MAILBOX + 8, arg1); 712 AAC_SETREG4(sc, AAC_SA_MAILBOX + 12, arg2); 713 AAC_SETREG4(sc, AAC_SA_MAILBOX + 16, arg3); 714 } 715 716 static void 717 aac_rx_set_mailbox(struct aac_softc *sc, u_int32_t command, 718 u_int32_t arg0, u_int32_t arg1, u_int32_t arg2, 719 u_int32_t arg3) 720 { 721 722 AAC_SETREG4(sc, AAC_RX_MAILBOX, command); 723 AAC_SETREG4(sc, AAC_RX_MAILBOX + 4, arg0); 724 AAC_SETREG4(sc, AAC_RX_MAILBOX + 8, arg1); 725 AAC_SETREG4(sc, AAC_RX_MAILBOX + 12, arg2); 726 AAC_SETREG4(sc, AAC_RX_MAILBOX + 16, arg3); 727 } 728 729 static void 730 aac_rkt_set_mailbox(struct aac_softc *sc, u_int32_t command, 731 u_int32_t arg0, u_int32_t arg1, u_int32_t arg2, 732 u_int32_t arg3) 733 { 734 735 AAC_SETREG4(sc, AAC_RKT_MAILBOX, command); 736 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 4, arg0); 737 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 8, arg1); 738 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 12, arg2); 739 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 16, arg3); 740 } 741 742 /* 743 * Fetch the specified mailbox 744 */ 745 static uint32_t 746 aac_sa_get_mailbox(struct aac_softc *sc, int mb) 747 { 748 749 return (AAC_GETREG4(sc, AAC_SA_MAILBOX + (mb * 4))); 750 } 751 752 static uint32_t 753 aac_rx_get_mailbox(struct aac_softc *sc, int mb) 754 { 755 756 return (AAC_GETREG4(sc, AAC_RX_MAILBOX + (mb * 4))); 757 } 758 759 static uint32_t 760 aac_rkt_get_mailbox(struct aac_softc *sc, int mb) 761 { 762 763 return (AAC_GETREG4(sc, AAC_RKT_MAILBOX + (mb * 4))); 764 } 765 766 /* 767 * Set/clear interrupt masks 768 */ 769 static void 770 aac_sa_set_interrupts(struct aac_softc *sc, int enable) 771 { 772 773 if (enable) 774 AAC_SETREG2((sc), AAC_SA_MASK0_CLEAR, AAC_DB_INTERRUPTS); 775 else 776 AAC_SETREG2((sc), AAC_SA_MASK0_SET, ~0); 777 } 778 779 static void 780 aac_rx_set_interrupts(struct aac_softc *sc, int enable) 781 { 782 783 if (enable) { 784 if (sc->sc_quirks & AAC_QUIRK_NEW_COMM) 785 AAC_SETREG4(sc, AAC_RX_OIMR, ~AAC_DB_INT_NEW_COMM); 786 else 787 AAC_SETREG4(sc, AAC_RX_OIMR, ~AAC_DB_INTERRUPTS); 788 } else { 789 AAC_SETREG4(sc, AAC_RX_OIMR, ~0); 790 } 791 } 792 793 static void 794 aac_rkt_set_interrupts(struct aac_softc *sc, int enable) 795 { 796 797 if (enable) { 798 if (sc->sc_quirks & AAC_QUIRK_NEW_COMM) 799 AAC_SETREG4(sc, AAC_RKT_OIMR, ~AAC_DB_INT_NEW_COMM); 800 else 801 AAC_SETREG4(sc, AAC_RKT_OIMR, ~AAC_DB_INTERRUPTS); 802 } else { 803 AAC_SETREG4(sc, AAC_RKT_OIMR, ~0); 804 } 805 } 806 807 /* 808 * New comm. interface: Send command functions 809 */ 810 static int 811 aac_rx_send_command(struct aac_softc *sc, struct aac_ccb *ac) 812 { 813 u_int32_t index, device; 814 815 index = AAC_GETREG4(sc, AAC_RX_IQUE); 816 if (index == 0xffffffffL) 817 index = AAC_GETREG4(sc, AAC_RX_IQUE); 818 if (index == 0xffffffffL) 819 return index; 820 #ifdef notyet 821 aac_enqueue_busy(ac); 822 #endif 823 device = index; 824 AAC_SETREG4(sc, device, 825 htole32((u_int32_t)(ac->ac_fibphys & 0xffffffffUL))); 826 device += 4; 827 if (sizeof(bus_addr_t) > 4) { 828 AAC_SETREG4(sc, device, 829 htole32((u_int32_t)((u_int64_t)ac->ac_fibphys >> 32))); 830 } else { 831 AAC_SETREG4(sc, device, 0); 832 } 833 device += 4; 834 AAC_SETREG4(sc, device, ac->ac_fib->Header.Size); 835 AAC_SETREG4(sc, AAC_RX_IQUE, index); 836 return 0; 837 } 838 839 static int 840 aac_rkt_send_command(struct aac_softc *sc, struct aac_ccb *ac) 841 { 842 u_int32_t index, device; 843 844 index = AAC_GETREG4(sc, AAC_RKT_IQUE); 845 if (index == 0xffffffffL) 846 index = AAC_GETREG4(sc, AAC_RKT_IQUE); 847 if (index == 0xffffffffL) 848 return index; 849 #ifdef notyet 850 aac_enqueue_busy(ac); 851 #endif 852 device = index; 853 AAC_SETREG4(sc, device, 854 htole32((u_int32_t)(ac->ac_fibphys & 0xffffffffUL))); 855 device += 4; 856 if (sizeof(bus_addr_t) > 4) { 857 AAC_SETREG4(sc, device, 858 htole32((u_int32_t)((u_int64_t)ac->ac_fibphys >> 32))); 859 } else { 860 AAC_SETREG4(sc, device, 0); 861 } 862 device += 4; 863 AAC_SETREG4(sc, device, ac->ac_fib->Header.Size); 864 AAC_SETREG4(sc, AAC_RKT_IQUE, index); 865 return 0; 866 } 867 868 /* 869 * New comm. interface: get, set outbound queue index 870 */ 871 static int 872 aac_rx_get_outb_queue(struct aac_softc *sc) 873 { 874 875 return AAC_GETREG4(sc, AAC_RX_OQUE); 876 } 877 878 static int 879 aac_rkt_get_outb_queue(struct aac_softc *sc) 880 { 881 882 return AAC_GETREG4(sc, AAC_RKT_OQUE); 883 } 884 885 static void 886 aac_rx_set_outb_queue(struct aac_softc *sc, int index) 887 { 888 889 AAC_SETREG4(sc, AAC_RX_OQUE, index); 890 } 891 892 static void 893 aac_rkt_set_outb_queue(struct aac_softc *sc, int index) 894 { 895 896 AAC_SETREG4(sc, AAC_RKT_OQUE, index); 897 } 898
Indexes created Wed Oct 01 19:09:53 GMT 2025