aac_pci.c revision 1.41
1 /* $NetBSD: aac_pci.c,v 1.41 2021/04/24 23:36:57 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 2000 Michael Smith 34 * Copyright (c) 2000 BSDi 35 * Copyright (c) 2000 Niklas Hallqvist 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 48 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 49 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 50 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 51 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 52 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 53 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 55 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 56 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 57 * SUCH DAMAGE. 58 * 59 * from FreeBSD: aac_pci.c,v 1.1 2000/09/13 03:20:34 msmith Exp 60 * via OpenBSD: aac_pci.c,v 1.7 2002/03/14 01:26:58 millert Exp 61 */ 62 63 /* 64 * PCI front-end for the `aac' driver. 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: aac_pci.c,v 1.41 2021/04/24 23:36:57 thorpej Exp $"); 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/device.h> 73 #include <sys/kernel.h> 74 #include <sys/malloc.h> 75 #include <sys/queue.h> 76 77 #include <sys/bus.h> 78 #include <machine/endian.h> 79 #include <sys/intr.h> 80 81 #include <dev/pci/pcidevs.h> 82 #include <dev/pci/pcireg.h> 83 #include <dev/pci/pcivar.h> 84 85 #include <dev/ic/aacreg.h> 86 #include <dev/ic/aacvar.h> 87 88 struct aac_pci_softc { 89 struct aac_softc sc_aac; 90 pci_chipset_tag_t sc_pc; 91 pci_intr_handle_t sc_ih; 92 }; 93 94 /* i960Rx interface */ 95 static int aac_rx_get_fwstatus(struct aac_softc *); 96 static void aac_rx_qnotify(struct aac_softc *, int); 97 static int aac_rx_get_istatus(struct aac_softc *); 98 static void aac_rx_clear_istatus(struct aac_softc *, int); 99 static void aac_rx_set_mailbox(struct aac_softc *, u_int32_t, u_int32_t, 100 u_int32_t, u_int32_t, u_int32_t); 101 static uint32_t aac_rx_get_mailbox(struct aac_softc *, int); 102 static void aac_rx_set_interrupts(struct aac_softc *, int); 103 static int aac_rx_send_command(struct aac_softc *, struct aac_ccb *); 104 static int aac_rx_get_outb_queue(struct aac_softc *); 105 static void aac_rx_set_outb_queue(struct aac_softc *, int); 106 107 /* StrongARM interface */ 108 static int aac_sa_get_fwstatus(struct aac_softc *); 109 static void aac_sa_qnotify(struct aac_softc *, int); 110 static int aac_sa_get_istatus(struct aac_softc *); 111 static void aac_sa_clear_istatus(struct aac_softc *, int); 112 static void aac_sa_set_mailbox(struct aac_softc *, u_int32_t, u_int32_t, 113 u_int32_t, u_int32_t, u_int32_t); 114 static uint32_t aac_sa_get_mailbox(struct aac_softc *, int); 115 static void aac_sa_set_interrupts(struct aac_softc *, int); 116 117 /* Rocket/MIPS interface */ 118 static int aac_rkt_get_fwstatus(struct aac_softc *); 119 static void aac_rkt_qnotify(struct aac_softc *, int); 120 static int aac_rkt_get_istatus(struct aac_softc *); 121 static void aac_rkt_clear_istatus(struct aac_softc *, int); 122 static void aac_rkt_set_mailbox(struct aac_softc *, u_int32_t, u_int32_t, 123 u_int32_t, u_int32_t, u_int32_t); 124 static uint32_t aac_rkt_get_mailbox(struct aac_softc *, int); 125 static void aac_rkt_set_interrupts(struct aac_softc *, int); 126 static int aac_rkt_send_command(struct aac_softc *, struct aac_ccb *); 127 static int aac_rkt_get_outb_queue(struct aac_softc *); 128 static void aac_rkt_set_outb_queue(struct aac_softc *, int); 129 130 static const struct aac_interface aac_rx_interface = { 131 aac_rx_get_fwstatus, 132 aac_rx_qnotify, 133 aac_rx_get_istatus, 134 aac_rx_clear_istatus, 135 aac_rx_set_mailbox, 136 aac_rx_get_mailbox, 137 aac_rx_set_interrupts, 138 aac_rx_send_command, 139 aac_rx_get_outb_queue, 140 aac_rx_set_outb_queue 141 }; 142 143 static const struct aac_interface aac_sa_interface = { 144 aac_sa_get_fwstatus, 145 aac_sa_qnotify, 146 aac_sa_get_istatus, 147 aac_sa_clear_istatus, 148 aac_sa_set_mailbox, 149 aac_sa_get_mailbox, 150 aac_sa_set_interrupts, 151 NULL, NULL, NULL 152 }; 153 154 static const struct aac_interface aac_rkt_interface = { 155 aac_rkt_get_fwstatus, 156 aac_rkt_qnotify, 157 aac_rkt_get_istatus, 158 aac_rkt_clear_istatus, 159 aac_rkt_set_mailbox, 160 aac_rkt_get_mailbox, 161 aac_rkt_set_interrupts, 162 aac_rkt_send_command, 163 aac_rkt_get_outb_queue, 164 aac_rkt_set_outb_queue 165 }; 166 167 static struct aac_ident { 168 u_short vendor; 169 u_short device; 170 u_short subvendor; 171 u_short subdevice; 172 u_short hwif; 173 u_short quirks; 174 const char *prodstr; 175 } const aac_ident[] = { 176 { 177 PCI_VENDOR_DELL, 178 PCI_PRODUCT_DELL_PERC_2SI, 179 PCI_VENDOR_DELL, 180 PCI_PRODUCT_DELL_PERC_2SI, 181 AAC_HWIF_I960RX, 182 0, 183 "Dell PERC 2/Si" 184 }, 185 { 186 PCI_VENDOR_DELL, 187 PCI_PRODUCT_DELL_PERC_3DI, 188 PCI_VENDOR_DELL, 189 PCI_PRODUCT_DELL_PERC_3DI, 190 AAC_HWIF_I960RX, 191 0, 192 "Dell PERC 3/Di" 193 }, 194 { 195 PCI_VENDOR_DELL, 196 PCI_PRODUCT_DELL_PERC_3DI, 197 PCI_VENDOR_DELL, 198 PCI_PRODUCT_DELL_PERC_3DI_SUB2, 199 AAC_HWIF_I960RX, 200 0, 201 "Dell PERC 3/Di" 202 }, 203 { 204 PCI_VENDOR_DELL, 205 PCI_PRODUCT_DELL_PERC_3DI, 206 PCI_VENDOR_DELL, 207 PCI_PRODUCT_DELL_PERC_3DI_SUB3, 208 AAC_HWIF_I960RX, 209 0, 210 "Dell PERC 3/Di" 211 }, 212 { 213 PCI_VENDOR_DELL, 214 PCI_PRODUCT_DELL_PERC_3DI_2, 215 PCI_VENDOR_DELL, 216 PCI_PRODUCT_DELL_PERC_3DI_2_SUB, 217 AAC_HWIF_I960RX, 218 0, 219 "Dell PERC 3/Di" 220 }, 221 { 222 PCI_VENDOR_DELL, 223 PCI_PRODUCT_DELL_PERC_3DI_3, 224 PCI_VENDOR_DELL, 225 PCI_PRODUCT_DELL_PERC_3DI_3_SUB, 226 AAC_HWIF_I960RX, 227 0, 228 "Dell PERC 3/Di" 229 }, 230 { 231 PCI_VENDOR_DELL, 232 PCI_PRODUCT_DELL_PERC_3DI_3, 233 PCI_VENDOR_DELL, 234 PCI_PRODUCT_DELL_PERC_3DI_3_SUB2, 235 AAC_HWIF_I960RX, 236 0, 237 "Dell PERC 3/Di" 238 }, 239 { 240 PCI_VENDOR_DELL, 241 PCI_PRODUCT_DELL_PERC_3DI_3, 242 PCI_VENDOR_DELL, 243 PCI_PRODUCT_DELL_PERC_3DI_3_SUB3, 244 AAC_HWIF_I960RX, 245 0, 246 "Dell PERC 3/Di" 247 }, 248 { 249 PCI_VENDOR_DELL, 250 PCI_PRODUCT_DELL_PERC_3SI, 251 PCI_VENDOR_DELL, 252 PCI_PRODUCT_DELL_PERC_3SI, 253 AAC_HWIF_I960RX, 254 0, 255 "Dell PERC 3/Si" 256 }, 257 { 258 PCI_VENDOR_DELL, 259 PCI_PRODUCT_DELL_PERC_3SI_2, 260 PCI_VENDOR_DELL, 261 PCI_PRODUCT_DELL_PERC_3SI_2_SUB, 262 AAC_HWIF_I960RX, 263 0, 264 "Dell PERC 3/Si" 265 }, 266 { 267 PCI_VENDOR_ADP2, 268 PCI_PRODUCT_ADP2_ASR2200S, 269 PCI_VENDOR_DELL, 270 PCI_PRODUCT_DELL_CERC_1_5, 271 AAC_HWIF_I960RX, 272 AAC_QUIRK_NO4GB, 273 "Dell CERC SATA RAID 1.5/6ch" 274 }, 275 { 276 PCI_VENDOR_ADP2, 277 PCI_PRODUCT_ADP2_AAC2622, 278 PCI_VENDOR_ADP2, 279 PCI_PRODUCT_ADP2_AAC2622, 280 AAC_HWIF_I960RX, 281 0, 282 "Adaptec ADP-2622" 283 }, 284 { 285 PCI_VENDOR_ADP2, 286 PCI_PRODUCT_ADP2_ASR2200S, 287 PCI_VENDOR_ADP2, 288 PCI_PRODUCT_ADP2_ASR2200S_SUB2M, 289 AAC_HWIF_I960RX, 290 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 291 "Adaptec ASR-2200S" 292 }, 293 { 294 PCI_VENDOR_ADP2, 295 PCI_PRODUCT_ADP2_ASR2200S, 296 PCI_VENDOR_DELL, 297 PCI_PRODUCT_ADP2_ASR2200S_SUB2M, 298 AAC_HWIF_I960RX, 299 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 300 "Dell PERC 320/DC" 301 }, 302 { 303 PCI_VENDOR_ADP2, 304 PCI_PRODUCT_ADP2_ASR2200S, 305 PCI_VENDOR_ADP2, 306 PCI_PRODUCT_ADP2_ASR2200S, 307 AAC_HWIF_I960RX, 308 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 309 "Adaptec ASR-2200S" 310 }, 311 { 312 PCI_VENDOR_ADP2, 313 PCI_PRODUCT_ADP2_ASR2200S, 314 PCI_VENDOR_ADP2, 315 PCI_PRODUCT_ADP2_AAR2810SA, 316 AAC_HWIF_I960RX, 317 AAC_QUIRK_NO4GB, 318 "Adaptec AAR-2810SA" 319 }, 320 { 321 PCI_VENDOR_ADP2, 322 PCI_PRODUCT_ADP2_ASR2200S, 323 PCI_VENDOR_ADP2, 324 PCI_PRODUCT_ADP2_ASR2120S, 325 AAC_HWIF_I960RX, 326 AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS, 327 "Adaptec ASR-2120S" 328 }, 329 { 330 PCI_VENDOR_ADP2, 331 PCI_PRODUCT_ADP2_ASR2200S, 332 PCI_VENDOR_ADP2, 333 PCI_PRODUCT_ADP2_ASR2410SA, 334 AAC_HWIF_I960RX, 335 AAC_QUIRK_NO4GB, 336 "Adaptec ASR-2410SA" 337 }, 338 { 339 PCI_VENDOR_ADP2, 340 PCI_PRODUCT_ADP2_ASR2200S, 341 PCI_VENDOR_HP, 342 PCI_PRODUCT_ADP2_HP_M110_G2, 343 AAC_HWIF_I960RX, 344 AAC_QUIRK_NO4GB, 345 "HP ML110 G2 (Adaptec ASR-2610SA)" 346 }, 347 { 348 PCI_VENDOR_ADP2, 349 PCI_PRODUCT_ADP2_ASR2120S, 350 PCI_VENDOR_IBM, 351 PCI_PRODUCT_IBM_SERVERAID8K, 352 AAC_HWIF_RKT, 353 0, 354 "IBM ServeRAID 8k" 355 }, 356 { PCI_VENDOR_ADP2, 357 PCI_PRODUCT_ADP2_ASR2200S, 358 PCI_VENDOR_ADP2, 359 PCI_PRODUCT_ADP2_2405, 360 AAC_HWIF_I960RX, 361 0, 362 "Adaptec RAID 2405" 363 }, 364 { PCI_VENDOR_ADP2, 365 PCI_PRODUCT_ADP2_ASR2200S, 366 PCI_VENDOR_ADP2, 367 PCI_PRODUCT_ADP2_2445, 368 AAC_HWIF_I960RX, 369 0, 370 "Adaptec RAID 2445" 371 }, 372 { PCI_VENDOR_ADP2, 373 PCI_PRODUCT_ADP2_ASR2200S, 374 PCI_VENDOR_ADP2, 375 PCI_PRODUCT_ADP2_2805, 376 AAC_HWIF_I960RX, 377 0, 378 "Adaptec RAID 2805" 379 }, 380 { PCI_VENDOR_ADP2, 381 PCI_PRODUCT_ADP2_ASR2200S, 382 PCI_VENDOR_ADP2, 383 PCI_PRODUCT_ADP2_3405, 384 AAC_HWIF_I960RX, 385 0, 386 "Adaptec RAID 3405" 387 }, 388 { PCI_VENDOR_ADP2, 389 PCI_PRODUCT_ADP2_ASR2200S, 390 PCI_VENDOR_ADP2, 391 PCI_PRODUCT_ADP2_3805, 392 AAC_HWIF_I960RX, 393 0, 394 "Adaptec RAID 3805" 395 }, 396 { 397 PCI_VENDOR_DEC, 398 PCI_PRODUCT_DEC_21554, 399 PCI_VENDOR_ADP2, 400 PCI_PRODUCT_ADP2_AAC364, 401 AAC_HWIF_STRONGARM, 402 0, 403 "Adaptec AAC-364" 404 }, 405 { 406 PCI_VENDOR_DEC, 407 PCI_PRODUCT_DEC_21554, 408 PCI_VENDOR_ADP2, 409 PCI_PRODUCT_ADP2_ASR5400S, 410 AAC_HWIF_STRONGARM, 411 AAC_QUIRK_BROKEN_MMAP, 412 "Adaptec ASR-5400S" 413 }, 414 { 415 PCI_VENDOR_DEC, 416 PCI_PRODUCT_DEC_21554, 417 PCI_VENDOR_ADP2, 418 PCI_PRODUCT_ADP2_PERC_2QC, 419 AAC_HWIF_STRONGARM, 420 AAC_QUIRK_PERC2QC, 421 "Dell PERC 2/QC" 422 }, 423 { 424 PCI_VENDOR_DEC, 425 PCI_PRODUCT_DEC_21554, 426 PCI_VENDOR_ADP2, 427 PCI_PRODUCT_ADP2_PERC_3QC, 428 AAC_HWIF_STRONGARM, 429 0, 430 "Dell PERC 3/QC" 431 }, 432 { 433 PCI_VENDOR_DEC, 434 PCI_PRODUCT_DEC_21554, 435 PCI_VENDOR_HP, 436 PCI_PRODUCT_HP_NETRAID_4M, 437 AAC_HWIF_STRONGARM, 438 0, 439 "HP NetRAID-4M" 440 }, 441 { 442 PCI_VENDOR_ADP2, 443 PCI_PRODUCT_ADP2_ASR2200S, 444 PCI_VENDOR_SUN, 445 PCI_PRODUCT_ADP2_ASR2120S, 446 AAC_HWIF_I960RX, 447 0, 448 "SG-XPCIESAS-R-IN" 449 }, 450 }; 451 452 static const struct aac_ident * 453 aac_find_ident(struct pci_attach_args *pa) 454 { 455 const struct aac_ident *m, *mm; 456 u_int32_t subsysid; 457 458 m = aac_ident; 459 mm = aac_ident + (sizeof(aac_ident) / sizeof(aac_ident[0])); 460 461 while (m < mm) { 462 if (m->vendor == PCI_VENDOR(pa->pa_id) && 463 m->device == PCI_PRODUCT(pa->pa_id)) { 464 subsysid = pci_conf_read(pa->pa_pc, pa->pa_tag, 465 PCI_SUBSYS_ID_REG); 466 if (m->subvendor == PCI_VENDOR(subsysid) && 467 m->subdevice == PCI_PRODUCT(subsysid)) 468 return (m); 469 } 470 m++; 471 } 472 473 return (NULL); 474 } 475 476 static int 477 aac_pci_intr_set(struct aac_softc *sc, int (*hand)(void*), void *arg) 478 { 479 struct aac_pci_softc *pcisc; 480 481 pcisc = (struct aac_pci_softc *) sc; 482 483 pci_intr_disestablish(pcisc->sc_pc, sc->sc_ih); 484 sc->sc_ih = pci_intr_establish_xname(pcisc->sc_pc, pcisc->sc_ih, 485 IPL_BIO, hand, arg, device_xname(sc->sc_dv)); 486 if (sc->sc_ih == NULL) { 487 return ENXIO; 488 } 489 return 0; 490 } 491 492 static int 493 aac_pci_match(device_t parent, cfdata_t match, void *aux) 494 { 495 struct pci_attach_args *pa; 496 497 pa = aux; 498 499 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 500 return (0); 501 502 return (aac_find_ident(pa) != NULL); 503 } 504 505 static void 506 aac_pci_attach(device_t parent, device_t self, void *aux) 507 { 508 struct pci_attach_args *pa; 509 pci_chipset_tag_t pc; 510 struct aac_pci_softc *pcisc; 511 struct aac_softc *sc; 512 u_int16_t command; 513 bus_addr_t membase; 514 bus_size_t memsize; 515 const char *intrstr; 516 int state; 517 const struct aac_ident *m; 518 char intrbuf[PCI_INTRSTR_LEN]; 519 520 pa = aux; 521 pc = pa->pa_pc; 522 pcisc = device_private(self); 523 pcisc->sc_pc = pc; 524 sc = &pcisc->sc_aac; 525 sc->sc_dv = self; 526 state = 0; 527 528 aprint_naive(": RAID controller\n"); 529 aprint_normal(": "); 530 531 /* 532 * Verify that the adapter is correctly set up in PCI space. 533 */ 534 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 535 command |= PCI_COMMAND_MASTER_ENABLE; 536 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 537 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 538 AAC_DPRINTF(AAC_D_MISC, ("pci command status reg 0x08x ")); 539 540 if ((command & PCI_COMMAND_MASTER_ENABLE) == 0) { 541 aprint_error("can't enable bus-master feature\n"); 542 goto bail_out; 543 } 544 545 if ((command & PCI_COMMAND_MEM_ENABLE) == 0) { 546 aprint_error("memory window not available\n"); 547 goto bail_out; 548 } 549 550 /* 551 * Map control/status registers. 552 */ 553 if (pci_mapreg_map(pa, PCI_MAPREG_START, 554 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_memt, 555 &sc->sc_memh, &membase, &memsize)) { 556 aprint_error("can't find mem space\n"); 557 goto bail_out; 558 } 559 state++; 560 561 if (pci_intr_map(pa, &pcisc->sc_ih)) { 562 aprint_error("couldn't map interrupt\n"); 563 goto bail_out; 564 } 565 intrstr = pci_intr_string(pc, pcisc->sc_ih, intrbuf, sizeof(intrbuf)); 566 sc->sc_ih = pci_intr_establish_xname(pc, pcisc->sc_ih, IPL_BIO, 567 aac_intr, sc, device_xname(self)); 568 if (sc->sc_ih == NULL) { 569 aprint_error("couldn't establish interrupt"); 570 if (intrstr != NULL) 571 aprint_error(" at %s", intrstr); 572 aprint_error("\n"); 573 goto bail_out; 574 } 575 state++; 576 577 sc->sc_dmat = pa->pa_dmat; 578 579 m = aac_find_ident(pa); 580 aprint_normal("%s\n", m->prodstr); 581 if (intrstr != NULL) 582 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 583 584 sc->sc_hwif = m->hwif; 585 sc->sc_quirks = m->quirks; 586 switch (sc->sc_hwif) { 587 case AAC_HWIF_I960RX: 588 AAC_DPRINTF(AAC_D_MISC, 589 ("set hardware up for i960Rx")); 590 sc->sc_if = aac_rx_interface; 591 break; 592 593 case AAC_HWIF_STRONGARM: 594 AAC_DPRINTF(AAC_D_MISC, 595 ("set hardware up for StrongARM")); 596 sc->sc_if = aac_sa_interface; 597 break; 598 599 case AAC_HWIF_RKT: 600 AAC_DPRINTF(AAC_D_MISC, 601 ("set hardware up for MIPS/Rocket")); 602 sc->sc_if = aac_rkt_interface; 603 break; 604 } 605 sc->sc_regsize = memsize; 606 sc->sc_intr_set = aac_pci_intr_set; 607 608 if (!aac_attach(sc)) 609 return; 610 611 bail_out: 612 if (state > 1) 613 pci_intr_disestablish(pc, sc->sc_ih); 614 if (state > 0) 615 bus_space_unmap(sc->sc_memt, sc->sc_memh, memsize); 616 } 617 618 /* ARGSUSED */ 619 static int 620 aac_pci_rescan(device_t self, const char *ifattr, const int *locs) 621 { 622 623 return aac_devscan(device_private(self)); 624 } 625 626 CFATTACH_DECL3_NEW(aac_pci, sizeof(struct aac_pci_softc), 627 aac_pci_match, aac_pci_attach, NULL, NULL, aac_pci_rescan, NULL, 0); 628 629 /* 630 * Read the current firmware status word. 631 */ 632 static int 633 aac_sa_get_fwstatus(struct aac_softc *sc) 634 { 635 636 return (AAC_GETREG4(sc, AAC_SA_FWSTATUS)); 637 } 638 639 static int 640 aac_rx_get_fwstatus(struct aac_softc *sc) 641 { 642 643 return (AAC_GETREG4(sc, AAC_RX_FWSTATUS)); 644 } 645 646 static int 647 aac_rkt_get_fwstatus(struct aac_softc *sc) 648 { 649 650 return (AAC_GETREG4(sc, AAC_RKT_FWSTATUS)); 651 } 652 653 /* 654 * Notify the controller of a change in a given queue 655 */ 656 657 static void 658 aac_sa_qnotify(struct aac_softc *sc, int qbit) 659 { 660 661 AAC_SETREG2(sc, AAC_SA_DOORBELL1_SET, qbit); 662 } 663 664 static void 665 aac_rx_qnotify(struct aac_softc *sc, int qbit) 666 { 667 668 AAC_SETREG4(sc, AAC_RX_IDBR, qbit); 669 } 670 671 static void 672 aac_rkt_qnotify(struct aac_softc *sc, int qbit) 673 { 674 675 AAC_SETREG4(sc, AAC_RKT_IDBR, qbit); 676 } 677 678 /* 679 * Get the interrupt reason bits 680 */ 681 static int 682 aac_sa_get_istatus(struct aac_softc *sc) 683 { 684 685 return (AAC_GETREG2(sc, AAC_SA_DOORBELL0)); 686 } 687 688 static int 689 aac_rx_get_istatus(struct aac_softc *sc) 690 { 691 692 return (AAC_GETREG4(sc, AAC_RX_ODBR)); 693 } 694 695 static int 696 aac_rkt_get_istatus(struct aac_softc *sc) 697 { 698 699 return (AAC_GETREG4(sc, AAC_RKT_ODBR)); 700 } 701 702 /* 703 * Clear some interrupt reason bits 704 */ 705 static void 706 aac_sa_clear_istatus(struct aac_softc *sc, int mask) 707 { 708 709 AAC_SETREG2(sc, AAC_SA_DOORBELL0_CLEAR, mask); 710 } 711 712 static void 713 aac_rx_clear_istatus(struct aac_softc *sc, int mask) 714 { 715 716 AAC_SETREG4(sc, AAC_RX_ODBR, mask); 717 } 718 719 static void 720 aac_rkt_clear_istatus(struct aac_softc *sc, int mask) 721 { 722 723 AAC_SETREG4(sc, AAC_RKT_ODBR, mask); 724 } 725 726 /* 727 * Populate the mailbox and set the command word 728 */ 729 static void 730 aac_sa_set_mailbox(struct aac_softc *sc, u_int32_t command, 731 u_int32_t arg0, u_int32_t arg1, u_int32_t arg2, 732 u_int32_t arg3) 733 { 734 735 AAC_SETREG4(sc, AAC_SA_MAILBOX, command); 736 AAC_SETREG4(sc, AAC_SA_MAILBOX + 4, arg0); 737 AAC_SETREG4(sc, AAC_SA_MAILBOX + 8, arg1); 738 AAC_SETREG4(sc, AAC_SA_MAILBOX + 12, arg2); 739 AAC_SETREG4(sc, AAC_SA_MAILBOX + 16, arg3); 740 } 741 742 static void 743 aac_rx_set_mailbox(struct aac_softc *sc, u_int32_t command, 744 u_int32_t arg0, u_int32_t arg1, u_int32_t arg2, 745 u_int32_t arg3) 746 { 747 748 AAC_SETREG4(sc, AAC_RX_MAILBOX, command); 749 AAC_SETREG4(sc, AAC_RX_MAILBOX + 4, arg0); 750 AAC_SETREG4(sc, AAC_RX_MAILBOX + 8, arg1); 751 AAC_SETREG4(sc, AAC_RX_MAILBOX + 12, arg2); 752 AAC_SETREG4(sc, AAC_RX_MAILBOX + 16, arg3); 753 } 754 755 static void 756 aac_rkt_set_mailbox(struct aac_softc *sc, u_int32_t command, 757 u_int32_t arg0, u_int32_t arg1, u_int32_t arg2, 758 u_int32_t arg3) 759 { 760 761 AAC_SETREG4(sc, AAC_RKT_MAILBOX, command); 762 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 4, arg0); 763 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 8, arg1); 764 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 12, arg2); 765 AAC_SETREG4(sc, AAC_RKT_MAILBOX + 16, arg3); 766 } 767 768 /* 769 * Fetch the specified mailbox 770 */ 771 static uint32_t 772 aac_sa_get_mailbox(struct aac_softc *sc, int mb) 773 { 774 775 return (AAC_GETREG4(sc, AAC_SA_MAILBOX + (mb * 4))); 776 } 777 778 static uint32_t 779 aac_rx_get_mailbox(struct aac_softc *sc, int mb) 780 { 781 782 return (AAC_GETREG4(sc, AAC_RX_MAILBOX + (mb * 4))); 783 } 784 785 static uint32_t 786 aac_rkt_get_mailbox(struct aac_softc *sc, int mb) 787 { 788 789 return (AAC_GETREG4(sc, AAC_RKT_MAILBOX + (mb * 4))); 790 } 791 792 /* 793 * Set/clear interrupt masks 794 */ 795 static void 796 aac_sa_set_interrupts(struct aac_softc *sc, int enable) 797 { 798 799 if (enable) 800 AAC_SETREG2((sc), AAC_SA_MASK0_CLEAR, AAC_DB_INTERRUPTS); 801 else 802 AAC_SETREG2((sc), AAC_SA_MASK0_SET, ~0); 803 } 804 805 static void 806 aac_rx_set_interrupts(struct aac_softc *sc, int enable) 807 { 808 809 if (enable) { 810 if (sc->sc_quirks & AAC_QUIRK_NEW_COMM) 811 AAC_SETREG4(sc, AAC_RX_OIMR, ~AAC_DB_INT_NEW_COMM); 812 else 813 AAC_SETREG4(sc, AAC_RX_OIMR, ~AAC_DB_INTERRUPTS); 814 } else { 815 AAC_SETREG4(sc, AAC_RX_OIMR, ~0); 816 } 817 } 818 819 static void 820 aac_rkt_set_interrupts(struct aac_softc *sc, int enable) 821 { 822 823 if (enable) { 824 if (sc->sc_quirks & AAC_QUIRK_NEW_COMM) 825 AAC_SETREG4(sc, AAC_RKT_OIMR, ~AAC_DB_INT_NEW_COMM); 826 else 827 AAC_SETREG4(sc, AAC_RKT_OIMR, ~AAC_DB_INTERRUPTS); 828 } else { 829 AAC_SETREG4(sc, AAC_RKT_OIMR, ~0); 830 } 831 } 832 833 /* 834 * New comm. interface: Send command functions 835 */ 836 static int 837 aac_rx_send_command(struct aac_softc *sc, struct aac_ccb *ac) 838 { 839 u_int32_t index, device; 840 841 index = AAC_GETREG4(sc, AAC_RX_IQUE); 842 if (index == 0xffffffffL) 843 index = AAC_GETREG4(sc, AAC_RX_IQUE); 844 if (index == 0xffffffffL) 845 return index; 846 #ifdef notyet 847 aac_enqueue_busy(ac); 848 #endif 849 device = index; 850 AAC_SETREG4(sc, device, 851 htole32((u_int32_t)(ac->ac_fibphys & 0xffffffffUL))); 852 device += 4; 853 if (sizeof(bus_addr_t) > 4) { 854 AAC_SETREG4(sc, device, 855 htole32((u_int32_t)((u_int64_t)ac->ac_fibphys >> 32))); 856 } else { 857 AAC_SETREG4(sc, device, 0); 858 } 859 device += 4; 860 AAC_SETREG4(sc, device, ac->ac_fib->Header.Size); 861 AAC_SETREG4(sc, AAC_RX_IQUE, index); 862 return 0; 863 } 864 865 static int 866 aac_rkt_send_command(struct aac_softc *sc, struct aac_ccb *ac) 867 { 868 u_int32_t index, device; 869 870 index = AAC_GETREG4(sc, AAC_RKT_IQUE); 871 if (index == 0xffffffffL) 872 index = AAC_GETREG4(sc, AAC_RKT_IQUE); 873 if (index == 0xffffffffL) 874 return index; 875 #ifdef notyet 876 aac_enqueue_busy(ac); 877 #endif 878 device = index; 879 AAC_SETREG4(sc, device, 880 htole32((u_int32_t)(ac->ac_fibphys & 0xffffffffUL))); 881 device += 4; 882 if (sizeof(bus_addr_t) > 4) { 883 AAC_SETREG4(sc, device, 884 htole32((u_int32_t)((u_int64_t)ac->ac_fibphys >> 32))); 885 } else { 886 AAC_SETREG4(sc, device, 0); 887 } 888 device += 4; 889 AAC_SETREG4(sc, device, ac->ac_fib->Header.Size); 890 AAC_SETREG4(sc, AAC_RKT_IQUE, index); 891 return 0; 892 } 893 894 /* 895 * New comm. interface: get, set outbound queue index 896 */ 897 static int 898 aac_rx_get_outb_queue(struct aac_softc *sc) 899 { 900 901 return AAC_GETREG4(sc, AAC_RX_OQUE); 902 } 903 904 static int 905 aac_rkt_get_outb_queue(struct aac_softc *sc) 906 { 907 908 return AAC_GETREG4(sc, AAC_RKT_OQUE); 909 } 910 911 static void 912 aac_rx_set_outb_queue(struct aac_softc *sc, int index) 913 { 914 915 AAC_SETREG4(sc, AAC_RX_OQUE, index); 916 } 917 918 static void 919 aac_rkt_set_outb_queue(struct aac_softc *sc, int index) 920 { 921 922 AAC_SETREG4(sc, AAC_RKT_OQUE, index); 923 } 924
Indexes created Wed Oct 01 19:09:53 GMT 2025