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acardide.c revision 1.9.2.5
      1  1.9.2.5  skrll /*	$NetBSD: acardide.c,v 1.9.2.5 2004/09/21 13:31:00 skrll Exp $	*/
      2  1.9.2.2  skrll 
      3  1.9.2.2  skrll /*
      4  1.9.2.2  skrll  * Copyright (c) 2001 Izumi Tsutsui.
      5  1.9.2.2  skrll  *
      6  1.9.2.2  skrll  * Redistribution and use in source and binary forms, with or without
      7  1.9.2.2  skrll  * modification, are permitted provided that the following conditions
      8  1.9.2.2  skrll  * are met:
      9  1.9.2.2  skrll  * 1. Redistributions of source code must retain the above copyright
     10  1.9.2.2  skrll  *    notice, this list of conditions and the following disclaimer.
     11  1.9.2.2  skrll  * 2. Redistributions in binary form must reproduce the above copyright
     12  1.9.2.2  skrll  *    notice, this list of conditions and the following disclaimer in the
     13  1.9.2.2  skrll  *    documentation and/or other materials provided with the distribution.
     14  1.9.2.2  skrll  * 3. The name of the author may not be used to endorse or promote products
     15  1.9.2.2  skrll  *    derived from this software without specific prior written permission.
     16  1.9.2.2  skrll  *
     17  1.9.2.2  skrll  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     18  1.9.2.2  skrll  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     19  1.9.2.2  skrll  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     20  1.9.2.2  skrll  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     21  1.9.2.2  skrll  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     22  1.9.2.2  skrll  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     23  1.9.2.2  skrll  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     24  1.9.2.2  skrll  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     25  1.9.2.2  skrll  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     26  1.9.2.2  skrll  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     27  1.9.2.2  skrll  */
     28  1.9.2.2  skrll 
     29  1.9.2.2  skrll #include <sys/param.h>
     30  1.9.2.2  skrll #include <sys/systm.h>
     31  1.9.2.2  skrll 
     32  1.9.2.2  skrll #include <dev/pci/pcivar.h>
     33  1.9.2.2  skrll #include <dev/pci/pcidevs.h>
     34  1.9.2.2  skrll #include <dev/pci/pciidereg.h>
     35  1.9.2.2  skrll #include <dev/pci/pciidevar.h>
     36  1.9.2.2  skrll #include <dev/pci/pciide_acard_reg.h>
     37  1.9.2.2  skrll 
     38  1.9.2.2  skrll static void acard_chip_map(struct pciide_softc*, struct pci_attach_args*);
     39  1.9.2.3  skrll static void acard_setup_channel(struct ata_channel*);
     40  1.9.2.2  skrll #if 0 /* XXX !! */
     41  1.9.2.2  skrll static int  acard_pci_intr(void *);
     42  1.9.2.2  skrll #endif
     43  1.9.2.2  skrll 
     44  1.9.2.2  skrll static int  acardide_match(struct device *, struct cfdata *, void *);
     45  1.9.2.2  skrll static void acardide_attach(struct device *, struct device *, void *);
     46  1.9.2.2  skrll 
     47  1.9.2.2  skrll CFATTACH_DECL(acardide, sizeof(struct pciide_softc),
     48  1.9.2.2  skrll     acardide_match, acardide_attach, NULL, NULL);
     49  1.9.2.2  skrll 
     50  1.9.2.2  skrll static const struct pciide_product_desc pciide_acard_products[] =  {
     51  1.9.2.2  skrll 	{ PCI_PRODUCT_ACARD_ATP850U,
     52  1.9.2.2  skrll 	  0,
     53  1.9.2.2  skrll 	  "Acard ATP850U Ultra33 IDE Controller",
     54  1.9.2.2  skrll 	  acard_chip_map,
     55  1.9.2.2  skrll 	},
     56  1.9.2.2  skrll 	{ PCI_PRODUCT_ACARD_ATP860,
     57  1.9.2.2  skrll 	  0,
     58  1.9.2.2  skrll 	  "Acard ATP860 Ultra66 IDE Controller",
     59  1.9.2.2  skrll 	  acard_chip_map,
     60  1.9.2.2  skrll 	},
     61  1.9.2.2  skrll 	{ PCI_PRODUCT_ACARD_ATP860A,
     62  1.9.2.2  skrll 	  0,
     63  1.9.2.2  skrll 	  "Acard ATP860-A Ultra66 IDE Controller",
     64  1.9.2.2  skrll 	  acard_chip_map,
     65  1.9.2.2  skrll 	},
     66  1.9.2.2  skrll 	{ PCI_PRODUCT_ACARD_ATP865,
     67  1.9.2.2  skrll 	  0,
     68  1.9.2.2  skrll 	  "Acard ATP865 Ultra100 IDE Controller",
     69  1.9.2.2  skrll 	  acard_chip_map,
     70  1.9.2.2  skrll 	},
     71  1.9.2.2  skrll 	{ PCI_PRODUCT_ACARD_ATP865A,
     72  1.9.2.2  skrll 	  0,
     73  1.9.2.2  skrll 	  "Acard ATP865-A Ultra100 IDE Controller",
     74  1.9.2.2  skrll 	  acard_chip_map,
     75  1.9.2.2  skrll 	},
     76  1.9.2.2  skrll 	{ 0,
     77  1.9.2.2  skrll 	  0,
     78  1.9.2.2  skrll 	  NULL,
     79  1.9.2.2  skrll 	  NULL
     80  1.9.2.2  skrll 	}
     81  1.9.2.2  skrll };
     82  1.9.2.2  skrll 
     83  1.9.2.2  skrll static int
     84  1.9.2.2  skrll acardide_match(struct device *parent, struct cfdata *match, void *aux)
     85  1.9.2.2  skrll {
     86  1.9.2.2  skrll 	struct pci_attach_args *pa = aux;
     87  1.9.2.2  skrll 
     88  1.9.2.2  skrll 	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ACARD) {
     89  1.9.2.2  skrll 		if (pciide_lookup_product(pa->pa_id, pciide_acard_products))
     90  1.9.2.2  skrll 			return (2);
     91  1.9.2.2  skrll 	}
     92  1.9.2.2  skrll 	return (0);
     93  1.9.2.2  skrll }
     94  1.9.2.2  skrll 
     95  1.9.2.2  skrll static void
     96  1.9.2.2  skrll acardide_attach(struct device *parent, struct device *self, void *aux)
     97  1.9.2.2  skrll {
     98  1.9.2.2  skrll 	struct pci_attach_args *pa = aux;
     99  1.9.2.2  skrll 	struct pciide_softc *sc = (struct pciide_softc *)self;
    100  1.9.2.2  skrll 
    101  1.9.2.2  skrll 	pciide_common_attach(sc, pa,
    102  1.9.2.2  skrll 	    pciide_lookup_product(pa->pa_id, pciide_acard_products));
    103  1.9.2.2  skrll 
    104  1.9.2.2  skrll }
    105  1.9.2.2  skrll 
    106  1.9.2.2  skrll #define	ACARD_IS_850(sc)						\
    107  1.9.2.2  skrll 	((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U)
    108  1.9.2.2  skrll 
    109  1.9.2.2  skrll static void
    110  1.9.2.2  skrll acard_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
    111  1.9.2.2  skrll {
    112  1.9.2.2  skrll 	struct pciide_channel *cp;
    113  1.9.2.2  skrll 	int i;
    114  1.9.2.2  skrll 	pcireg_t interface;
    115  1.9.2.2  skrll 	bus_size_t cmdsize, ctlsize;
    116  1.9.2.2  skrll 
    117  1.9.2.2  skrll 	if (pciide_chipen(sc, pa) == 0)
    118  1.9.2.2  skrll 		return;
    119  1.9.2.2  skrll 
    120  1.9.2.2  skrll 	/*
    121  1.9.2.2  skrll 	 * when the chip is in native mode it identifies itself as a
    122  1.9.2.2  skrll 	 * 'misc mass storage'. Fake interface in this case.
    123  1.9.2.2  skrll 	 */
    124  1.9.2.2  skrll 	if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) {
    125  1.9.2.2  skrll 		interface = PCI_INTERFACE(pa->pa_class);
    126  1.9.2.2  skrll 	} else {
    127  1.9.2.2  skrll 		interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
    128  1.9.2.2  skrll 		    PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
    129  1.9.2.2  skrll 	}
    130  1.9.2.2  skrll 
    131  1.9.2.2  skrll 	aprint_normal("%s: bus-master DMA support present",
    132  1.9.2.3  skrll 	    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
    133  1.9.2.2  skrll 	pciide_mapreg_dma(sc, pa);
    134  1.9.2.2  skrll 	aprint_normal("\n");
    135  1.9.2.3  skrll 	sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
    136  1.9.2.2  skrll 
    137  1.9.2.2  skrll 	if (sc->sc_dma_ok) {
    138  1.9.2.3  skrll 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
    139  1.9.2.2  skrll 		sc->sc_wdcdev.irqack = pciide_irqack;
    140  1.9.2.2  skrll 	}
    141  1.9.2.3  skrll 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
    142  1.9.2.3  skrll 	sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
    143  1.9.2.2  skrll 	switch (sc->sc_pp->ide_product) {
    144  1.9.2.2  skrll 	case PCI_PRODUCT_ACARD_ATP860:
    145  1.9.2.2  skrll 	case PCI_PRODUCT_ACARD_ATP860A:
    146  1.9.2.3  skrll 		sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
    147  1.9.2.2  skrll 		break;
    148  1.9.2.2  skrll 	case PCI_PRODUCT_ACARD_ATP865:
    149  1.9.2.2  skrll 	case PCI_PRODUCT_ACARD_ATP865A:
    150  1.9.2.3  skrll 		sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
    151  1.9.2.2  skrll 		break;
    152  1.9.2.2  skrll 	default:
    153  1.9.2.3  skrll 		sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
    154  1.9.2.2  skrll 		break;
    155  1.9.2.2  skrll 	}
    156  1.9.2.2  skrll 
    157  1.9.2.3  skrll 	sc->sc_wdcdev.sc_atac.atac_set_modes = acard_setup_channel;
    158  1.9.2.3  skrll 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
    159  1.9.2.3  skrll 	sc->sc_wdcdev.sc_atac.atac_nchannels = 2;
    160  1.9.2.2  skrll 
    161  1.9.2.3  skrll 	wdc_allocate_regs(&sc->sc_wdcdev);
    162  1.9.2.3  skrll 
    163  1.9.2.3  skrll 	for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
    164  1.9.2.2  skrll 		cp = &sc->pciide_channels[i];
    165  1.9.2.2  skrll 		if (pciide_chansetup(sc, i, interface) == 0)
    166  1.9.2.2  skrll 			continue;
    167  1.9.2.2  skrll 		pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
    168  1.9.2.2  skrll 		    pciide_pci_intr);
    169  1.9.2.2  skrll 	}
    170  1.9.2.2  skrll 	if (!ACARD_IS_850(sc)) {
    171  1.9.2.2  skrll 		u_int32_t reg;
    172  1.9.2.2  skrll 		reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL);
    173  1.9.2.2  skrll 		reg &= ~ATP860_CTRL_INT;
    174  1.9.2.2  skrll 		pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg);
    175  1.9.2.2  skrll 	}
    176  1.9.2.2  skrll }
    177  1.9.2.2  skrll 
    178  1.9.2.2  skrll static void
    179  1.9.2.3  skrll acard_setup_channel(struct ata_channel *chp)
    180  1.9.2.2  skrll {
    181  1.9.2.2  skrll 	struct ata_drive_datas *drvp;
    182  1.9.2.3  skrll 	struct atac_softc *atac = chp->ch_atac;
    183  1.9.2.3  skrll 	struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
    184  1.9.2.3  skrll 	struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
    185  1.9.2.2  skrll 	int channel = chp->ch_channel;
    186  1.9.2.3  skrll 	int drive, s;
    187  1.9.2.2  skrll 	u_int32_t idetime, udma_mode;
    188  1.9.2.2  skrll 	u_int32_t idedma_ctl;
    189  1.9.2.2  skrll 
    190  1.9.2.2  skrll 	/* setup DMA if needed */
    191  1.9.2.2  skrll 	pciide_channel_dma_setup(cp);
    192  1.9.2.2  skrll 
    193  1.9.2.2  skrll 	if (ACARD_IS_850(sc)) {
    194  1.9.2.2  skrll 		idetime = 0;
    195  1.9.2.2  skrll 		udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA);
    196  1.9.2.2  skrll 		udma_mode &= ~ATP850_UDMA_MASK(channel);
    197  1.9.2.2  skrll 	} else {
    198  1.9.2.2  skrll 		idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME);
    199  1.9.2.2  skrll 		idetime &= ~ATP860_SETTIME_MASK(channel);
    200  1.9.2.2  skrll 		udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA);
    201  1.9.2.2  skrll 		udma_mode &= ~ATP860_UDMA_MASK(channel);
    202  1.9.2.2  skrll 
    203  1.9.2.2  skrll 		/* check 80 pins cable */
    204  1.9.2.2  skrll 		if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) ||
    205  1.9.2.2  skrll 		    (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) {
    206  1.9.2.2  skrll 			if (pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL)
    207  1.9.2.2  skrll 			    & ATP860_CTRL_80P(chp->ch_channel)) {
    208  1.9.2.2  skrll 				if (chp->ch_drive[0].UDMA_mode > 2)
    209  1.9.2.2  skrll 					chp->ch_drive[0].UDMA_mode = 2;
    210  1.9.2.2  skrll 				if (chp->ch_drive[1].UDMA_mode > 2)
    211  1.9.2.2  skrll 					chp->ch_drive[1].UDMA_mode = 2;
    212  1.9.2.2  skrll 			}
    213  1.9.2.2  skrll 		}
    214  1.9.2.2  skrll 	}
    215  1.9.2.2  skrll 
    216  1.9.2.2  skrll 	idedma_ctl = 0;
    217  1.9.2.2  skrll 
    218  1.9.2.2  skrll 	/* Per drive settings */
    219  1.9.2.2  skrll 	for (drive = 0; drive < 2; drive++) {
    220  1.9.2.2  skrll 		drvp = &chp->ch_drive[drive];
    221  1.9.2.2  skrll 		/* If no drive, skip */
    222  1.9.2.2  skrll 		if ((drvp->drive_flags & DRIVE) == 0)
    223  1.9.2.2  skrll 			continue;
    224  1.9.2.2  skrll 		/* add timing values, setup DMA if needed */
    225  1.9.2.3  skrll 		if ((atac->atac_cap & ATAC_CAP_UDMA) &&
    226  1.9.2.2  skrll 		    (drvp->drive_flags & DRIVE_UDMA)) {
    227  1.9.2.2  skrll 			/* use Ultra/DMA */
    228  1.9.2.2  skrll 			if (ACARD_IS_850(sc)) {
    229  1.9.2.2  skrll 				idetime |= ATP850_SETTIME(drive,
    230  1.9.2.2  skrll 				    acard_act_udma[drvp->UDMA_mode],
    231  1.9.2.2  skrll 				    acard_rec_udma[drvp->UDMA_mode]);
    232  1.9.2.2  skrll 				udma_mode |= ATP850_UDMA_MODE(channel, drive,
    233  1.9.2.2  skrll 				    acard_udma_conf[drvp->UDMA_mode]);
    234  1.9.2.2  skrll 			} else {
    235  1.9.2.2  skrll 				idetime |= ATP860_SETTIME(channel, drive,
    236  1.9.2.2  skrll 				    acard_act_udma[drvp->UDMA_mode],
    237  1.9.2.2  skrll 				    acard_rec_udma[drvp->UDMA_mode]);
    238  1.9.2.2  skrll 				udma_mode |= ATP860_UDMA_MODE(channel, drive,
    239  1.9.2.2  skrll 				    acard_udma_conf[drvp->UDMA_mode]);
    240  1.9.2.2  skrll 			}
    241  1.9.2.2  skrll 			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
    242  1.9.2.3  skrll 		} else if ((atac->atac_cap & ATAC_CAP_DMA) &&
    243  1.9.2.2  skrll 		    (drvp->drive_flags & DRIVE_DMA)) {
    244  1.9.2.2  skrll 			/* use Multiword DMA */
    245  1.9.2.3  skrll 			s = splbio();
    246  1.9.2.2  skrll 			drvp->drive_flags &= ~DRIVE_UDMA;
    247  1.9.2.3  skrll 			splx(s);
    248  1.9.2.2  skrll 			if (ACARD_IS_850(sc)) {
    249  1.9.2.2  skrll 				idetime |= ATP850_SETTIME(drive,
    250  1.9.2.2  skrll 				    acard_act_dma[drvp->DMA_mode],
    251  1.9.2.2  skrll 				    acard_rec_dma[drvp->DMA_mode]);
    252  1.9.2.2  skrll 			} else {
    253  1.9.2.2  skrll 				idetime |= ATP860_SETTIME(channel, drive,
    254  1.9.2.2  skrll 				    acard_act_dma[drvp->DMA_mode],
    255  1.9.2.2  skrll 				    acard_rec_dma[drvp->DMA_mode]);
    256  1.9.2.2  skrll 			}
    257  1.9.2.2  skrll 			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
    258  1.9.2.2  skrll 		} else {
    259  1.9.2.2  skrll 			/* PIO only */
    260  1.9.2.3  skrll 			s = splbio();
    261  1.9.2.2  skrll 			drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA);
    262  1.9.2.3  skrll 			splx(s);
    263  1.9.2.2  skrll 			if (ACARD_IS_850(sc)) {
    264  1.9.2.2  skrll 				idetime |= ATP850_SETTIME(drive,
    265  1.9.2.2  skrll 				    acard_act_pio[drvp->PIO_mode],
    266  1.9.2.2  skrll 				    acard_rec_pio[drvp->PIO_mode]);
    267  1.9.2.2  skrll 			} else {
    268  1.9.2.2  skrll 				idetime |= ATP860_SETTIME(channel, drive,
    269  1.9.2.2  skrll 				    acard_act_pio[drvp->PIO_mode],
    270  1.9.2.2  skrll 				    acard_rec_pio[drvp->PIO_mode]);
    271  1.9.2.2  skrll 			}
    272  1.9.2.2  skrll 		pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL,
    273  1.9.2.2  skrll 		    pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL)
    274  1.9.2.2  skrll 		    | ATP8x0_CTRL_EN(channel));
    275  1.9.2.2  skrll 		}
    276  1.9.2.2  skrll 	}
    277  1.9.2.2  skrll 
    278  1.9.2.2  skrll 	if (idedma_ctl != 0) {
    279  1.9.2.2  skrll 		/* Add software bits in status register */
    280  1.9.2.2  skrll 		bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
    281  1.9.2.2  skrll 		    idedma_ctl);
    282  1.9.2.2  skrll 	}
    283  1.9.2.2  skrll 
    284  1.9.2.2  skrll 	if (ACARD_IS_850(sc)) {
    285  1.9.2.2  skrll 		pci_conf_write(sc->sc_pc, sc->sc_tag,
    286  1.9.2.2  skrll 		    ATP850_IDETIME(channel), idetime);
    287  1.9.2.2  skrll 		pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode);
    288  1.9.2.2  skrll 	} else {
    289  1.9.2.2  skrll 		pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime);
    290  1.9.2.2  skrll 		pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode);
    291  1.9.2.2  skrll 	}
    292  1.9.2.2  skrll }
    293  1.9.2.2  skrll 
    294  1.9.2.2  skrll #if 0 /* XXX !! */
    295  1.9.2.2  skrll static int
    296  1.9.2.2  skrll acard_pci_intr(void *arg)
    297  1.9.2.2  skrll {
    298  1.9.2.2  skrll 	struct pciide_softc *sc = arg;
    299  1.9.2.2  skrll 	struct pciide_channel *cp;
    300  1.9.2.3  skrll 	struct ata_channel *wdc_cp;
    301  1.9.2.2  skrll 	int rv = 0;
    302  1.9.2.2  skrll 	int dmastat, i, crv;
    303  1.9.2.2  skrll 
    304  1.9.2.3  skrll 	for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
    305  1.9.2.2  skrll 		cp = &sc->pciide_channels[i];
    306  1.9.2.2  skrll 		dmastat = bus_space_read_1(sc->sc_dma_iot,
    307  1.9.2.2  skrll 		    cp->dma_iohs[IDEDMA_CTL], 0);
    308  1.9.2.2  skrll 		if ((dmastat & IDEDMA_CTL_INTR) == 0)
    309  1.9.2.2  skrll 			continue;
    310  1.9.2.3  skrll 		wdc_cp = &cp->ata_channel;
    311  1.9.2.3  skrll 		if ((wdc_cp->ch_flags & ATACH_IRQ_WAIT) == 0) {
    312  1.9.2.2  skrll 			(void)wdcintr(wdc_cp);
    313  1.9.2.2  skrll 			bus_space_write_1(sc->sc_dma_iot,
    314  1.9.2.2  skrll 			    cp->dma_iohs[IDEDMA_CTL], 0, dmastat);
    315  1.9.2.2  skrll 			continue;
    316  1.9.2.2  skrll 		}
    317  1.9.2.2  skrll 		crv = wdcintr(wdc_cp);
    318  1.9.2.2  skrll 		if (crv == 0) {
    319  1.9.2.2  skrll 			printf("%s:%d: bogus intr\n",
    320  1.9.2.3  skrll 			    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, i);
    321  1.9.2.2  skrll 			bus_space_write_1(sc->sc_dma_iot,
    322  1.9.2.2  skrll 			    cp->dma_iohs[IDEDMA_CTL], 0, dmastat);
    323  1.9.2.2  skrll 		} else if (crv == 1)
    324  1.9.2.2  skrll 			rv = 1;
    325  1.9.2.2  skrll 		else if (rv == 0)
    326  1.9.2.2  skrll 			rv = crv;
    327  1.9.2.2  skrll 	}
    328  1.9.2.2  skrll 	return rv;
    329  1.9.2.2  skrll }
    330  1.9.2.2  skrll #endif
    331