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acardide.c revision 1.30.2.2 
      1 /*	$NetBSD: acardide.c,v 1.30.2.2 2014/08/20 00:03:41 tls Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2001 Izumi Tsutsui.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     25  */
     26 
     27 #include <sys/cdefs.h>
     28 __KERNEL_RCSID(0, "$NetBSD: acardide.c,v 1.30.2.2 2014/08/20 00:03:41 tls Exp $");
     29 
     30 #include <sys/param.h>
     31 #include <sys/systm.h>
     32 
     33 #include <dev/pci/pcivar.h>
     34 #include <dev/pci/pcidevs.h>
     35 #include <dev/pci/pciidereg.h>
     36 #include <dev/pci/pciidevar.h>
     37 #include <dev/pci/pciide_acard_reg.h>
     38 
     39 static void acard_chip_map(struct pciide_softc*, const struct pci_attach_args*);
     40 static void acard_setup_channel(struct ata_channel*);
     41 #if 0 /* XXX !! */
     42 static int  acard_pci_intr(void *);
     43 #endif
     44 
     45 static int  acardide_match(device_t, cfdata_t, void *);
     46 static void acardide_attach(device_t, device_t, void *);
     47 
     48 CFATTACH_DECL_NEW(acardide, sizeof(struct pciide_softc),
     49     acardide_match, acardide_attach, pciide_detach, NULL);
     50 
     51 static const struct pciide_product_desc pciide_acard_products[] =  {
     52 	{ PCI_PRODUCT_ACARD_ATP850U,
     53 	  0,
     54 	  "Acard ATP850U Ultra33 IDE Controller",
     55 	  acard_chip_map,
     56 	},
     57 	{ PCI_PRODUCT_ACARD_ATP860,
     58 	  0,
     59 	  "Acard ATP860 Ultra66 IDE Controller",
     60 	  acard_chip_map,
     61 	},
     62 	{ PCI_PRODUCT_ACARD_ATP860A,
     63 	  0,
     64 	  "Acard ATP860-A Ultra66 IDE Controller",
     65 	  acard_chip_map,
     66 	},
     67 	{ PCI_PRODUCT_ACARD_ATP865,
     68 	  0,
     69 	  "Acard ATP865 Ultra133 IDE Controller",
     70 	  acard_chip_map,
     71 	},
     72 	{ PCI_PRODUCT_ACARD_ATP865A,
     73 	  0,
     74 	  "Acard ATP865-A Ultra133 IDE Controller",
     75 	  acard_chip_map,
     76 	},
     77 	{ 0,
     78 	  0,
     79 	  NULL,
     80 	  NULL
     81 	}
     82 };
     83 
     84 static int
     85 acardide_match(device_t parent, cfdata_t match, void *aux)
     86 {
     87 	struct pci_attach_args *pa = aux;
     88 
     89 	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ACARD) {
     90 		if (pciide_lookup_product(pa->pa_id, pciide_acard_products))
     91 			return (2);
     92 	}
     93 	return (0);
     94 }
     95 
     96 static void
     97 acardide_attach(device_t parent, device_t self, void *aux)
     98 {
     99 	struct pci_attach_args *pa = aux;
    100 	struct pciide_softc *sc = device_private(self);
    101 
    102 	self->dv_maxphys = MIN(parent->dv_maxphys, MACHINE_MAXPHYS);
    103 
    104 	sc->sc_wdcdev.sc_atac.atac_dev = self;
    105 
    106 	pciide_common_attach(sc, pa,
    107 	    pciide_lookup_product(pa->pa_id, pciide_acard_products));
    108 
    109 }
    110 
    111 #define	ACARD_IS_850(sc)						\
    112 	((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U)
    113 
    114 static void
    115 acard_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
    116 {
    117 	struct pciide_channel *cp;
    118 	int i;
    119 	pcireg_t interface;
    120 
    121 	if (pciide_chipen(sc, pa) == 0)
    122 		return;
    123 
    124 	/*
    125 	 * when the chip is in native mode it identifies itself as a
    126 	 * 'misc mass storage'. Fake interface in this case.
    127 	 */
    128 	if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) {
    129 		interface = PCI_INTERFACE(pa->pa_class);
    130 	} else {
    131 		interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
    132 		    PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
    133 	}
    134 
    135 	aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    136 	    "bus-master DMA support present");
    137 	pciide_mapreg_dma(sc, pa);
    138 	aprint_verbose("\n");
    139 	sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
    140 
    141 	if (sc->sc_dma_ok) {
    142 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
    143 		sc->sc_wdcdev.irqack = pciide_irqack;
    144 	}
    145 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
    146 	sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
    147 	switch (sc->sc_pp->ide_product) {
    148 	case PCI_PRODUCT_ACARD_ATP860:
    149 	case PCI_PRODUCT_ACARD_ATP860A:
    150 		sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
    151 		break;
    152 	case PCI_PRODUCT_ACARD_ATP865:
    153 	case PCI_PRODUCT_ACARD_ATP865A:
    154 		sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    155 		break;
    156 	default:
    157 		sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
    158 		break;
    159 	}
    160 
    161 	sc->sc_wdcdev.sc_atac.atac_set_modes = acard_setup_channel;
    162 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
    163 	sc->sc_wdcdev.sc_atac.atac_nchannels = 2;
    164 	sc->sc_wdcdev.wdc_maxdrives = 2;
    165 
    166 	wdc_allocate_regs(&sc->sc_wdcdev);
    167 
    168 	for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
    169 		cp = &sc->pciide_channels[i];
    170 		if (pciide_chansetup(sc, i, interface) == 0)
    171 			continue;
    172 		pciide_mapchan(pa, cp, interface, pciide_pci_intr);
    173 	}
    174 	if (!ACARD_IS_850(sc)) {
    175 		u_int32_t reg;
    176 		reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL);
    177 		reg &= ~ATP860_CTRL_INT;
    178 		pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg);
    179 	}
    180 }
    181 
    182 static void
    183 acard_setup_channel(struct ata_channel *chp)
    184 {
    185 	struct ata_drive_datas *drvp;
    186 	struct atac_softc *atac = chp->ch_atac;
    187 	struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
    188 	struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
    189 	int channel = chp->ch_channel;
    190 	int drive, s;
    191 	u_int32_t idetime, udma_mode;
    192 	u_int32_t idedma_ctl;
    193 
    194 	/* setup DMA if needed */
    195 	pciide_channel_dma_setup(cp);
    196 
    197 	if (ACARD_IS_850(sc)) {
    198 		idetime = 0;
    199 		udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA);
    200 		udma_mode &= ~ATP850_UDMA_MASK(channel);
    201 	} else {
    202 		idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME);
    203 		idetime &= ~ATP860_SETTIME_MASK(channel);
    204 		udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA);
    205 		udma_mode &= ~ATP860_UDMA_MASK(channel);
    206 
    207 		/* check 80 pins cable */
    208 		if ((chp->ch_drive[0].drive_flags & ATA_DRIVE_UDMA) ||
    209 		    (chp->ch_drive[1].drive_flags & ATA_DRIVE_UDMA)) {
    210 			if (pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL)
    211 			    & ATP860_CTRL_80P(chp->ch_channel)) {
    212 				if (chp->ch_drive[0].UDMA_mode > 2)
    213 					chp->ch_drive[0].UDMA_mode = 2;
    214 				if (chp->ch_drive[1].UDMA_mode > 2)
    215 					chp->ch_drive[1].UDMA_mode = 2;
    216 			}
    217 		}
    218 	}
    219 
    220 	idedma_ctl = 0;
    221 
    222 	/* Per drive settings */
    223 	for (drive = 0; drive < 2; drive++) {
    224 		drvp = &chp->ch_drive[drive];
    225 		/* If no drive, skip */
    226 		if (drvp->drive_type == ATA_DRIVET_NONE)
    227 			continue;
    228 		/* add timing values, setup DMA if needed */
    229 		if ((atac->atac_cap & ATAC_CAP_UDMA) &&
    230 		    (drvp->drive_flags & ATA_DRIVE_UDMA)) {
    231 			/* use Ultra/DMA */
    232 			if (ACARD_IS_850(sc)) {
    233 				idetime |= ATP850_SETTIME(drive,
    234 				    acard_act_udma[drvp->UDMA_mode],
    235 				    acard_rec_udma[drvp->UDMA_mode]);
    236 				udma_mode |= ATP850_UDMA_MODE(channel, drive,
    237 				    acard_udma_conf[drvp->UDMA_mode]);
    238 			} else {
    239 				idetime |= ATP860_SETTIME(channel, drive,
    240 				    acard_act_udma[drvp->UDMA_mode],
    241 				    acard_rec_udma[drvp->UDMA_mode]);
    242 				udma_mode |= ATP860_UDMA_MODE(channel, drive,
    243 				    acard_udma_conf[drvp->UDMA_mode]);
    244 			}
    245 			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
    246 		} else if ((atac->atac_cap & ATAC_CAP_DMA) &&
    247 		    (drvp->drive_flags & ATA_DRIVE_DMA)) {
    248 			/* use Multiword DMA */
    249 			s = splbio();
    250 			drvp->drive_flags &= ~ATA_DRIVE_UDMA;
    251 			splx(s);
    252 			if (ACARD_IS_850(sc)) {
    253 				idetime |= ATP850_SETTIME(drive,
    254 				    acard_act_dma[drvp->DMA_mode],
    255 				    acard_rec_dma[drvp->DMA_mode]);
    256 			} else {
    257 				idetime |= ATP860_SETTIME(channel, drive,
    258 				    acard_act_dma[drvp->DMA_mode],
    259 				    acard_rec_dma[drvp->DMA_mode]);
    260 			}
    261 			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
    262 		} else {
    263 			/* PIO only */
    264 			s = splbio();
    265 			drvp->drive_flags &= ~(ATA_DRIVE_UDMA | ATA_DRIVE_DMA);
    266 			splx(s);
    267 			if (ACARD_IS_850(sc)) {
    268 				idetime |= ATP850_SETTIME(drive,
    269 				    acard_act_pio[drvp->PIO_mode],
    270 				    acard_rec_pio[drvp->PIO_mode]);
    271 			} else {
    272 				idetime |= ATP860_SETTIME(channel, drive,
    273 				    acard_act_pio[drvp->PIO_mode],
    274 				    acard_rec_pio[drvp->PIO_mode]);
    275 			}
    276 		pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL,
    277 		    pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL)
    278 		    | ATP8x0_CTRL_EN(channel));
    279 		}
    280 	}
    281 
    282 	if (idedma_ctl != 0) {
    283 		/* Add software bits in status register */
    284 		bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
    285 		    idedma_ctl);
    286 	}
    287 
    288 	if (ACARD_IS_850(sc)) {
    289 		pci_conf_write(sc->sc_pc, sc->sc_tag,
    290 		    ATP850_IDETIME(channel), idetime);
    291 		pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode);
    292 	} else {
    293 		pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime);
    294 		pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode);
    295 	}
    296 }
    297 
    298 #if 0 /* XXX !! */
    299 static int
    300 acard_pci_intr(void *arg)
    301 {
    302 	struct pciide_softc *sc = arg;
    303 	struct pciide_channel *cp;
    304 	struct ata_channel *wdc_cp;
    305 	int rv = 0;
    306 	int dmastat, i, crv;
    307 
    308 	for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
    309 		cp = &sc->pciide_channels[i];
    310 		dmastat = bus_space_read_1(sc->sc_dma_iot,
    311 		    cp->dma_iohs[IDEDMA_CTL], 0);
    312 		if ((dmastat & IDEDMA_CTL_INTR) == 0)
    313 			continue;
    314 		wdc_cp = &cp->ata_channel;
    315 		if ((wdc_cp->ch_flags & ATACH_IRQ_WAIT) == 0) {
    316 			(void)wdcintr(wdc_cp);
    317 			bus_space_write_1(sc->sc_dma_iot,
    318 			    cp->dma_iohs[IDEDMA_CTL], 0, dmastat);
    319 			continue;
    320 		}
    321 		crv = wdcintr(wdc_cp);
    322 		if (crv == 0) {
    323 			printf("%s:%d: bogus intr\n",
    324 			    device_xname(sc->sc_wdcdev.sc_atac.atac_dev), i);
    325 			bus_space_write_1(sc->sc_dma_iot,
    326 			    cp->dma_iohs[IDEDMA_CTL], 0, dmastat);
    327 		} else if (crv == 1)
    328 			rv = 1;
    329 		else if (rv == 0)
    330 			rv = crv;
    331 	}
    332 	return rv;
    333 }
    334 #endif
    335