aceride.c revision 1.14.2.3
1 /* $NetBSD: aceride.c,v 1.14.2.3 2005/08/18 20:07:26 tron Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_acer_reg.h> 40 41 static int acer_pcib_match(struct pci_attach_args *); 42 static void acer_do_reset(struct ata_channel *, int); 43 static void acer_chip_map(struct pciide_softc*, struct pci_attach_args*); 44 static void acer_setup_channel(struct ata_channel*); 45 static int acer_pci_intr(void *); 46 47 static int aceride_match(struct device *, struct cfdata *, void *); 48 static void aceride_attach(struct device *, struct device *, void *); 49 50 struct aceride_softc { 51 struct pciide_softc pciide_sc; 52 struct pci_attach_args pcib_pa; 53 }; 54 55 CFATTACH_DECL(aceride, sizeof(struct aceride_softc), 56 aceride_match, aceride_attach, NULL, NULL); 57 58 static const struct pciide_product_desc pciide_acer_products[] = { 59 { PCI_PRODUCT_ALI_M5229, 60 0, 61 "Acer Labs M5229 UDMA IDE Controller", 62 acer_chip_map, 63 }, 64 { 0, 65 0, 66 NULL, 67 NULL 68 } 69 }; 70 71 static int 72 aceride_match(struct device *parent, struct cfdata *match, void *aux) 73 { 74 struct pci_attach_args *pa = aux; 75 76 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI && 77 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 78 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 79 if (pciide_lookup_product(pa->pa_id, pciide_acer_products)) 80 return (2); 81 } 82 return (0); 83 } 84 85 static void 86 aceride_attach(struct device *parent, struct device *self, void *aux) 87 { 88 struct pci_attach_args *pa = aux; 89 struct pciide_softc *sc = (struct pciide_softc *)self; 90 91 pciide_common_attach(sc, pa, 92 pciide_lookup_product(pa->pa_id, pciide_acer_products)); 93 94 } 95 96 static int 97 acer_pcib_match(struct pci_attach_args *pa) 98 { 99 /* 100 * we need to access the PCI config space of the pcib, see 101 * acer_do_reset() 102 */ 103 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 104 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 105 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI && 106 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M1543) 107 return 1; 108 return 0; 109 } 110 111 static void 112 acer_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 113 { 114 struct pciide_channel *cp; 115 int channel; 116 pcireg_t cr, interface; 117 bus_size_t cmdsize, ctlsize; 118 pcireg_t rev = PCI_REVISION(pa->pa_class); 119 struct aceride_softc *acer_sc = (struct aceride_softc *)sc; 120 121 if (pciide_chipen(sc, pa) == 0) 122 return; 123 124 aprint_normal("%s: bus-master DMA support present", 125 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 126 pciide_mapreg_dma(sc, pa); 127 aprint_normal("\n"); 128 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 129 if (sc->sc_dma_ok) { 130 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 131 if (rev >= 0x20) { 132 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 133 if (rev >= 0xC4) 134 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 135 else if (rev >= 0xC2) 136 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 137 else 138 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 139 } 140 sc->sc_wdcdev.irqack = pciide_irqack; 141 } 142 143 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 144 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 145 sc->sc_wdcdev.sc_atac.atac_set_modes = acer_setup_channel; 146 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 147 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 148 149 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 150 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 151 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 152 153 /* Enable "microsoft register bits" R/W. */ 154 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 155 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 156 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 157 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 158 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 159 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 160 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 161 ~ACER_CHANSTATUSREGS_RO); 162 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 163 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 164 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 165 /* Don't use cr, re-read the real register content instead */ 166 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 167 PCI_CLASS_REG)); 168 169 /* From linux: enable "Cable Detection" */ 170 if (rev >= 0xC2) { 171 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 172 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 173 | ACER_0x4B_CDETECT); 174 } 175 176 wdc_allocate_regs(&sc->sc_wdcdev); 177 if (rev == 0xC3) { 178 /* install reset bug workaround */ 179 if (pci_find_device(&acer_sc->pcib_pa, acer_pcib_match) == 0) { 180 printf("%s: WARNING: can't find pci-isa bridge\n", 181 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 182 } else 183 sc->sc_wdcdev.reset = acer_do_reset; 184 } 185 186 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 187 channel++) { 188 cp = &sc->pciide_channels[channel]; 189 if (pciide_chansetup(sc, channel, interface) == 0) 190 continue; 191 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 192 aprint_normal("%s: %s channel ignored (disabled)\n", 193 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 194 cp->ata_channel.ch_flags |= ATACH_DISABLED; 195 continue; 196 } 197 /* newer controllers seems to lack the ACER_CHIDS. Sigh */ 198 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 199 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 200 } 201 } 202 203 static void 204 acer_do_reset(struct ata_channel *chp, int poll) 205 { 206 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 207 struct aceride_softc *acer_sc = (struct aceride_softc *)sc; 208 u_int8_t reg; 209 210 /* 211 * From OpenSolaris: after a reset we need to disable/enable the 212 * corresponding channel, or data corruption will occur in 213 * UltraDMA modes 214 */ 215 216 wdc_do_reset(chp, poll); 217 reg = pciide_pci_read(acer_sc->pcib_pa.pa_pc, acer_sc->pcib_pa.pa_tag, 218 ACER_PCIB_CTRL); 219 pciide_pci_write(acer_sc->pcib_pa.pa_pc, acer_sc->pcib_pa.pa_tag, 220 ACER_PCIB_CTRL, reg & ~ACER_PCIB_CTRL_ENCHAN(chp->ch_channel)); 221 delay(1000); 222 pciide_pci_write(acer_sc->pcib_pa.pa_pc, acer_sc->pcib_pa.pa_tag, 223 ACER_PCIB_CTRL, reg); 224 } 225 226 static void 227 acer_setup_channel(struct ata_channel *chp) 228 { 229 struct ata_drive_datas *drvp; 230 int drive, s; 231 u_int32_t acer_fifo_udma; 232 u_int32_t idedma_ctl; 233 struct pciide_channel *cp = (struct pciide_channel*)chp; 234 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 235 236 idedma_ctl = 0; 237 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 238 ATADEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 239 acer_fifo_udma), DEBUG_PROBE); 240 /* setup DMA if needed */ 241 pciide_channel_dma_setup(cp); 242 243 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 244 DRIVE_UDMA) { /* check 80 pins cable */ 245 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 246 ACER_0x4A_80PIN(chp->ch_channel)) { 247 if (chp->ch_drive[0].UDMA_mode > 2) 248 chp->ch_drive[0].UDMA_mode = 2; 249 if (chp->ch_drive[1].UDMA_mode > 2) 250 chp->ch_drive[1].UDMA_mode = 2; 251 } 252 } 253 254 for (drive = 0; drive < 2; drive++) { 255 drvp = &chp->ch_drive[drive]; 256 /* If no drive, skip */ 257 if ((drvp->drive_flags & DRIVE) == 0) 258 continue; 259 ATADEBUG_PRINT(("acer_setup_channel: old timings reg for " 260 "channel %d drive %d 0x%x\n", chp->ch_channel, drive, 261 pciide_pci_read(sc->sc_pc, sc->sc_tag, 262 ACER_IDETIM(chp->ch_channel, drive))), DEBUG_PROBE); 263 /* clear FIFO/DMA mode */ 264 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->ch_channel, drive, 0x3) | 265 ACER_UDMA_EN(chp->ch_channel, drive) | 266 ACER_UDMA_TIM(chp->ch_channel, drive, 0x7)); 267 268 /* add timing values, setup DMA if needed */ 269 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 270 (drvp->drive_flags & DRIVE_UDMA) == 0) { 271 acer_fifo_udma |= 272 ACER_FTH_OPL(chp->ch_channel, drive, 0x1); 273 goto pio; 274 } 275 276 acer_fifo_udma |= ACER_FTH_OPL(chp->ch_channel, drive, 0x2); 277 if (drvp->drive_flags & DRIVE_UDMA) { 278 /* use Ultra/DMA */ 279 s = splbio(); 280 drvp->drive_flags &= ~DRIVE_DMA; 281 splx(s); 282 acer_fifo_udma |= ACER_UDMA_EN(chp->ch_channel, drive); 283 acer_fifo_udma |= 284 ACER_UDMA_TIM(chp->ch_channel, drive, 285 acer_udma[drvp->UDMA_mode]); 286 /* XXX disable if one drive < UDMA3 ? */ 287 if (drvp->UDMA_mode >= 3) { 288 pciide_pci_write(sc->sc_pc, sc->sc_tag, 289 ACER_0x4B, 290 pciide_pci_read(sc->sc_pc, sc->sc_tag, 291 ACER_0x4B) | ACER_0x4B_UDMA66); 292 } 293 } else { 294 /* 295 * use Multiword DMA 296 * Timings will be used for both PIO and DMA, 297 * so adjust DMA mode if needed 298 */ 299 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 300 drvp->PIO_mode = drvp->DMA_mode + 2; 301 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 302 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 303 drvp->PIO_mode - 2 : 0; 304 if (drvp->DMA_mode == 0) 305 drvp->PIO_mode = 0; 306 } 307 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 308 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 309 ACER_IDETIM(chp->ch_channel, drive), 310 acer_pio[drvp->PIO_mode]); 311 } 312 ATADEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 313 acer_fifo_udma), DEBUG_PROBE); 314 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 315 if (idedma_ctl != 0) { 316 /* Add software bits in status register */ 317 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 318 idedma_ctl); 319 } 320 } 321 322 static int 323 acer_pci_intr(void *arg) 324 { 325 struct pciide_softc *sc = arg; 326 struct pciide_channel *cp; 327 struct ata_channel *wdc_cp; 328 int i, rv, crv; 329 u_int32_t chids; 330 331 rv = 0; 332 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 333 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 334 cp = &sc->pciide_channels[i]; 335 wdc_cp = &cp->ata_channel; 336 /* If a compat channel skip. */ 337 if (cp->compat) 338 continue; 339 if (chids & ACER_CHIDS_INT(i)) { 340 crv = wdcintr(wdc_cp); 341 if (crv == 0) { 342 printf("%s:%d: bogus intr\n", 343 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, i); 344 pciide_irqack(wdc_cp); 345 } else 346 rv = 1; 347 } 348 } 349 return rv; 350 } 351
Indexes created Thu Oct 23 18:09:57 GMT 2025