aceride.c revision 1.20
1 /* $NetBSD: aceride.c,v 1.20 2006/10/12 01:31:27 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: aceride.c,v 1.20 2006/10/12 01:31:27 christos Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_acer_reg.h> 43 44 static int acer_pcib_match(struct pci_attach_args *); 45 static void acer_do_reset(struct ata_channel *, int); 46 static void acer_chip_map(struct pciide_softc*, struct pci_attach_args*); 47 static void acer_setup_channel(struct ata_channel*); 48 static int acer_pci_intr(void *); 49 50 static int aceride_match(struct device *, struct cfdata *, void *); 51 static void aceride_attach(struct device *, struct device *, void *); 52 53 struct aceride_softc { 54 struct pciide_softc pciide_sc; 55 struct pci_attach_args pcib_pa; 56 }; 57 58 CFATTACH_DECL(aceride, sizeof(struct aceride_softc), 59 aceride_match, aceride_attach, NULL, NULL); 60 61 static const struct pciide_product_desc pciide_acer_products[] = { 62 { PCI_PRODUCT_ALI_M5229, 63 0, 64 "Acer Labs M5229 UDMA IDE Controller", 65 acer_chip_map, 66 }, 67 { 0, 68 0, 69 NULL, 70 NULL 71 } 72 }; 73 74 static int 75 aceride_match(struct device *parent __unused, struct cfdata *match __unused, 76 void *aux) 77 { 78 struct pci_attach_args *pa = aux; 79 80 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI && 81 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 82 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 83 if (pciide_lookup_product(pa->pa_id, pciide_acer_products)) 84 return (2); 85 } 86 return (0); 87 } 88 89 static void 90 aceride_attach(struct device *parent __unused, struct device *self, void *aux) 91 { 92 struct pci_attach_args *pa = aux; 93 struct pciide_softc *sc = (struct pciide_softc *)self; 94 95 pciide_common_attach(sc, pa, 96 pciide_lookup_product(pa->pa_id, pciide_acer_products)); 97 98 } 99 100 static int 101 acer_pcib_match(struct pci_attach_args *pa) 102 { 103 /* 104 * we need to access the PCI config space of the pcib, see 105 * acer_do_reset() 106 */ 107 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 108 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 109 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI && 110 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M1543) 111 return 1; 112 return 0; 113 } 114 115 static void 116 acer_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 117 { 118 struct pciide_channel *cp; 119 int channel; 120 pcireg_t cr, interface; 121 bus_size_t cmdsize, ctlsize; 122 pcireg_t rev = PCI_REVISION(pa->pa_class); 123 struct aceride_softc *acer_sc = (struct aceride_softc *)sc; 124 125 if (pciide_chipen(sc, pa) == 0) 126 return; 127 128 aprint_normal("%s: bus-master DMA support present", 129 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 130 pciide_mapreg_dma(sc, pa); 131 aprint_normal("\n"); 132 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 133 if (sc->sc_dma_ok) { 134 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 135 if (rev >= 0x20) { 136 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 137 if (rev >= 0xC4) 138 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 139 else if (rev >= 0xC2) 140 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 141 else 142 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 143 } 144 sc->sc_wdcdev.irqack = pciide_irqack; 145 } 146 147 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 148 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 149 sc->sc_wdcdev.sc_atac.atac_set_modes = acer_setup_channel; 150 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 151 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 152 153 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 154 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 155 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 156 157 /* Enable "microsoft register bits" R/W. */ 158 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 159 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 160 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 161 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 162 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 163 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 164 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 165 ~ACER_CHANSTATUSREGS_RO); 166 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 167 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 168 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 169 /* Don't use cr, re-read the real register content instead */ 170 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 171 PCI_CLASS_REG)); 172 173 /* From linux: enable "Cable Detection" */ 174 if (rev >= 0xC2) { 175 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 176 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 177 | ACER_0x4B_CDETECT); 178 } 179 180 wdc_allocate_regs(&sc->sc_wdcdev); 181 if (rev == 0xC3) { 182 /* install reset bug workaround */ 183 if (pci_find_device(&acer_sc->pcib_pa, acer_pcib_match) == 0) { 184 printf("%s: WARNING: can't find pci-isa bridge\n", 185 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 186 } else 187 sc->sc_wdcdev.reset = acer_do_reset; 188 } 189 190 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 191 channel++) { 192 cp = &sc->pciide_channels[channel]; 193 if (pciide_chansetup(sc, channel, interface) == 0) 194 continue; 195 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 196 aprint_normal("%s: %s channel ignored (disabled)\n", 197 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 198 cp->ata_channel.ch_flags |= ATACH_DISABLED; 199 continue; 200 } 201 /* newer controllers seems to lack the ACER_CHIDS. Sigh */ 202 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 203 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 204 } 205 } 206 207 static void 208 acer_do_reset(struct ata_channel *chp, int poll) 209 { 210 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 211 struct aceride_softc *acer_sc = (struct aceride_softc *)sc; 212 u_int8_t reg; 213 214 /* 215 * From OpenSolaris: after a reset we need to disable/enable the 216 * corresponding channel, or data corruption will occur in 217 * UltraDMA modes 218 */ 219 220 wdc_do_reset(chp, poll); 221 reg = pciide_pci_read(acer_sc->pcib_pa.pa_pc, acer_sc->pcib_pa.pa_tag, 222 ACER_PCIB_CTRL); 223 pciide_pci_write(acer_sc->pcib_pa.pa_pc, acer_sc->pcib_pa.pa_tag, 224 ACER_PCIB_CTRL, reg & ~ACER_PCIB_CTRL_ENCHAN(chp->ch_channel)); 225 delay(1000); 226 pciide_pci_write(acer_sc->pcib_pa.pa_pc, acer_sc->pcib_pa.pa_tag, 227 ACER_PCIB_CTRL, reg); 228 } 229 230 static void 231 acer_setup_channel(struct ata_channel *chp) 232 { 233 struct ata_drive_datas *drvp; 234 int drive, s; 235 u_int32_t acer_fifo_udma; 236 u_int32_t idedma_ctl; 237 struct pciide_channel *cp = (struct pciide_channel*)chp; 238 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 239 240 idedma_ctl = 0; 241 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 242 ATADEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 243 acer_fifo_udma), DEBUG_PROBE); 244 /* setup DMA if needed */ 245 pciide_channel_dma_setup(cp); 246 247 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 248 DRIVE_UDMA) { /* check 80 pins cable */ 249 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 250 ACER_0x4A_80PIN(chp->ch_channel)) { 251 if (chp->ch_drive[0].UDMA_mode > 2) 252 chp->ch_drive[0].UDMA_mode = 2; 253 if (chp->ch_drive[1].UDMA_mode > 2) 254 chp->ch_drive[1].UDMA_mode = 2; 255 } 256 } 257 258 for (drive = 0; drive < 2; drive++) { 259 drvp = &chp->ch_drive[drive]; 260 /* If no drive, skip */ 261 if ((drvp->drive_flags & DRIVE) == 0) 262 continue; 263 ATADEBUG_PRINT(("acer_setup_channel: old timings reg for " 264 "channel %d drive %d 0x%x\n", chp->ch_channel, drive, 265 pciide_pci_read(sc->sc_pc, sc->sc_tag, 266 ACER_IDETIM(chp->ch_channel, drive))), DEBUG_PROBE); 267 /* clear FIFO/DMA mode */ 268 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->ch_channel, drive, 0x3) | 269 ACER_UDMA_EN(chp->ch_channel, drive) | 270 ACER_UDMA_TIM(chp->ch_channel, drive, 0x7)); 271 272 /* add timing values, setup DMA if needed */ 273 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 274 (drvp->drive_flags & DRIVE_UDMA) == 0) { 275 acer_fifo_udma |= 276 ACER_FTH_OPL(chp->ch_channel, drive, 0x1); 277 goto pio; 278 } 279 280 acer_fifo_udma |= ACER_FTH_OPL(chp->ch_channel, drive, 0x2); 281 if (drvp->drive_flags & DRIVE_UDMA) { 282 /* use Ultra/DMA */ 283 s = splbio(); 284 drvp->drive_flags &= ~DRIVE_DMA; 285 splx(s); 286 acer_fifo_udma |= ACER_UDMA_EN(chp->ch_channel, drive); 287 acer_fifo_udma |= 288 ACER_UDMA_TIM(chp->ch_channel, drive, 289 acer_udma[drvp->UDMA_mode]); 290 /* XXX disable if one drive < UDMA3 ? */ 291 if (drvp->UDMA_mode >= 3) { 292 pciide_pci_write(sc->sc_pc, sc->sc_tag, 293 ACER_0x4B, 294 pciide_pci_read(sc->sc_pc, sc->sc_tag, 295 ACER_0x4B) | ACER_0x4B_UDMA66); 296 } 297 } else { 298 /* 299 * use Multiword DMA 300 * Timings will be used for both PIO and DMA, 301 * so adjust DMA mode if needed 302 */ 303 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 304 drvp->PIO_mode = drvp->DMA_mode + 2; 305 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 306 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 307 drvp->PIO_mode - 2 : 0; 308 if (drvp->DMA_mode == 0) 309 drvp->PIO_mode = 0; 310 } 311 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 312 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 313 ACER_IDETIM(chp->ch_channel, drive), 314 acer_pio[drvp->PIO_mode]); 315 } 316 ATADEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 317 acer_fifo_udma), DEBUG_PROBE); 318 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 319 if (idedma_ctl != 0) { 320 /* Add software bits in status register */ 321 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 322 idedma_ctl); 323 } 324 } 325 326 static int 327 acer_pci_intr(void *arg) 328 { 329 struct pciide_softc *sc = arg; 330 struct pciide_channel *cp; 331 struct ata_channel *wdc_cp; 332 int i, rv, crv; 333 u_int32_t chids; 334 335 rv = 0; 336 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 337 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 338 cp = &sc->pciide_channels[i]; 339 wdc_cp = &cp->ata_channel; 340 /* If a compat channel skip. */ 341 if (cp->compat) 342 continue; 343 if (chids & ACER_CHIDS_INT(i)) { 344 crv = wdcintr(wdc_cp); 345 if (crv == 0) { 346 printf("%s:%d: bogus intr\n", 347 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, i); 348 pciide_irqack(wdc_cp); 349 } else 350 rv = 1; 351 } 352 } 353 return rv; 354 } 355
Indexes created Mon Sep 22 13:09:51 GMT 2025