aceride.c revision 1.25.14.1
1 /* $NetBSD: aceride.c,v 1.25.14.1 2010/11/21 23:41:20 riz Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: aceride.c,v 1.25.14.1 2010/11/21 23:41:20 riz Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_acer_reg.h> 43 44 static int acer_pcib_match(struct pci_attach_args *); 45 static void acer_do_reset(struct ata_channel *, int); 46 static void acer_chip_map(struct pciide_softc*, struct pci_attach_args*); 47 static void acer_setup_channel(struct ata_channel*); 48 static int acer_pci_intr(void *); 49 static int acer_dma_init(void *, int, int, void *, size_t, int); 50 51 static int aceride_match(device_t, cfdata_t, void *); 52 static void aceride_attach(device_t, device_t, void *); 53 54 struct aceride_softc { 55 struct pciide_softc pciide_sc; 56 struct pci_attach_args pcib_pa; 57 }; 58 59 CFATTACH_DECL_NEW(aceride, sizeof(struct aceride_softc), 60 aceride_match, aceride_attach, NULL, NULL); 61 62 static const struct pciide_product_desc pciide_acer_products[] = { 63 { PCI_PRODUCT_ALI_M5229, 64 0, 65 "Acer Labs M5229 UDMA IDE Controller", 66 acer_chip_map, 67 }, 68 { 0, 69 0, 70 NULL, 71 NULL 72 } 73 }; 74 75 static int 76 aceride_match(device_t parent, cfdata_t match, void *aux) 77 { 78 struct pci_attach_args *pa = aux; 79 80 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI && 81 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 82 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 83 if (pciide_lookup_product(pa->pa_id, pciide_acer_products)) 84 return (2); 85 } 86 return (0); 87 } 88 89 static void 90 aceride_attach(device_t parent, device_t self, void *aux) 91 { 92 struct pci_attach_args *pa = aux; 93 struct pciide_softc *sc = device_private(self); 94 95 sc->sc_wdcdev.sc_atac.atac_dev = self; 96 97 pciide_common_attach(sc, pa, 98 pciide_lookup_product(pa->pa_id, pciide_acer_products)); 99 } 100 101 static int 102 acer_pcib_match(struct pci_attach_args *pa) 103 { 104 /* 105 * we need to access the PCI config space of the pcib, see 106 * acer_do_reset() 107 */ 108 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 109 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 110 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI && 111 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M1543) 112 return 1; 113 return 0; 114 } 115 116 static void 117 acer_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 118 { 119 struct pciide_channel *cp; 120 int channel; 121 pcireg_t cr, interface; 122 bus_size_t cmdsize, ctlsize; 123 pcireg_t rev = PCI_REVISION(pa->pa_class); 124 struct aceride_softc *acer_sc = (struct aceride_softc *)sc; 125 126 if (pciide_chipen(sc, pa) == 0) 127 return; 128 129 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 130 "bus-master DMA support present"); 131 pciide_mapreg_dma(sc, pa); 132 aprint_verbose("\n"); 133 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 134 if (sc->sc_dma_ok) { 135 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 136 if (rev >= 0x20) { 137 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 138 if (rev >= 0xC7) 139 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 140 else if (rev >= 0xC4) 141 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 142 else if (rev >= 0xC2) 143 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 144 else 145 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 146 } 147 sc->sc_wdcdev.irqack = pciide_irqack; 148 if (rev <= 0xc4) { 149 sc->sc_wdcdev.dma_init = acer_dma_init; 150 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 151 "using PIO transfers above 137GB as workaround for " 152 "48bit DMA access bug, expect reduced performance\n"); 153 } 154 } 155 156 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 157 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 158 sc->sc_wdcdev.sc_atac.atac_set_modes = acer_setup_channel; 159 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 160 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 161 162 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 163 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 164 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 165 166 /* Enable "microsoft register bits" R/W. */ 167 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 168 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 169 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 170 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 171 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 172 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 173 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 174 ~ACER_CHANSTATUSREGS_RO); 175 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 176 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 177 178 { 179 /* 180 * some BIOSes (port-cats ABLE) enable native mode, but don't 181 * setup everything correctly, so allow the forcing of 182 * compat mode 183 */ 184 bool force_compat_mode; 185 bool property_is_set; 186 property_is_set = prop_dictionary_get_bool( 187 device_properties(sc->sc_wdcdev.sc_atac.atac_dev), 188 "ali1543-ide-force-compat-mode", 189 &force_compat_mode); 190 if (property_is_set && force_compat_mode) { 191 cr &= ~((PCIIDE_INTERFACE_PCI(0) 192 | PCIIDE_INTERFACE_PCI(1)) 193 << PCI_INTERFACE_SHIFT); 194 } 195 } 196 197 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 198 /* Don't use cr, re-read the real register content instead */ 199 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 200 PCI_CLASS_REG)); 201 202 /* From linux: enable "Cable Detection" */ 203 if (rev >= 0xC2) { 204 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 205 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 206 | ACER_0x4B_CDETECT); 207 } 208 209 wdc_allocate_regs(&sc->sc_wdcdev); 210 if (rev == 0xC3) { 211 /* install reset bug workaround */ 212 if (pci_find_device(&acer_sc->pcib_pa, acer_pcib_match) == 0) { 213 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 214 "WARNING: can't find pci-isa bridge\n"); 215 } else 216 sc->sc_wdcdev.reset = acer_do_reset; 217 } 218 219 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 220 channel++) { 221 cp = &sc->pciide_channels[channel]; 222 if (pciide_chansetup(sc, channel, interface) == 0) 223 continue; 224 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 225 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 226 "%s channel ignored (disabled)\n", cp->name); 227 cp->ata_channel.ch_flags |= ATACH_DISABLED; 228 continue; 229 } 230 /* newer controllers seems to lack the ACER_CHIDS. Sigh */ 231 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 232 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 233 } 234 } 235 236 static void 237 acer_do_reset(struct ata_channel *chp, int poll) 238 { 239 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 240 struct aceride_softc *acer_sc = (struct aceride_softc *)sc; 241 u_int8_t reg; 242 243 /* 244 * From OpenSolaris: after a reset we need to disable/enable the 245 * corresponding channel, or data corruption will occur in 246 * UltraDMA modes 247 */ 248 249 wdc_do_reset(chp, poll); 250 reg = pciide_pci_read(acer_sc->pcib_pa.pa_pc, acer_sc->pcib_pa.pa_tag, 251 ACER_PCIB_CTRL); 252 pciide_pci_write(acer_sc->pcib_pa.pa_pc, acer_sc->pcib_pa.pa_tag, 253 ACER_PCIB_CTRL, reg & ~ACER_PCIB_CTRL_ENCHAN(chp->ch_channel)); 254 delay(1000); 255 pciide_pci_write(acer_sc->pcib_pa.pa_pc, acer_sc->pcib_pa.pa_tag, 256 ACER_PCIB_CTRL, reg); 257 } 258 259 static void 260 acer_setup_channel(struct ata_channel *chp) 261 { 262 struct ata_drive_datas *drvp; 263 int drive, s; 264 u_int32_t acer_fifo_udma; 265 u_int32_t idedma_ctl; 266 struct pciide_channel *cp = (struct pciide_channel*)chp; 267 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 268 269 idedma_ctl = 0; 270 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 271 ATADEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 272 acer_fifo_udma), DEBUG_PROBE); 273 /* setup DMA if needed */ 274 pciide_channel_dma_setup(cp); 275 276 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 277 DRIVE_UDMA) { /* check 80 pins cable */ 278 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 279 ACER_0x4A_80PIN(chp->ch_channel)) { 280 if (chp->ch_drive[0].UDMA_mode > 2) 281 chp->ch_drive[0].UDMA_mode = 2; 282 if (chp->ch_drive[1].UDMA_mode > 2) 283 chp->ch_drive[1].UDMA_mode = 2; 284 } 285 } 286 287 for (drive = 0; drive < 2; drive++) { 288 drvp = &chp->ch_drive[drive]; 289 /* If no drive, skip */ 290 if ((drvp->drive_flags & DRIVE) == 0) 291 continue; 292 ATADEBUG_PRINT(("acer_setup_channel: old timings reg for " 293 "channel %d drive %d 0x%x\n", chp->ch_channel, drive, 294 pciide_pci_read(sc->sc_pc, sc->sc_tag, 295 ACER_IDETIM(chp->ch_channel, drive))), DEBUG_PROBE); 296 /* clear FIFO/DMA mode */ 297 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->ch_channel, drive, 0x3) | 298 ACER_UDMA_EN(chp->ch_channel, drive) | 299 ACER_UDMA_TIM(chp->ch_channel, drive, 0x7)); 300 301 /* add timing values, setup DMA if needed */ 302 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 303 (drvp->drive_flags & DRIVE_UDMA) == 0) { 304 acer_fifo_udma |= 305 ACER_FTH_OPL(chp->ch_channel, drive, 0x1); 306 goto pio; 307 } 308 309 acer_fifo_udma |= ACER_FTH_OPL(chp->ch_channel, drive, 0x2); 310 if (drvp->drive_flags & DRIVE_UDMA) { 311 /* use Ultra/DMA */ 312 s = splbio(); 313 drvp->drive_flags &= ~DRIVE_DMA; 314 splx(s); 315 acer_fifo_udma |= ACER_UDMA_EN(chp->ch_channel, drive); 316 acer_fifo_udma |= 317 ACER_UDMA_TIM(chp->ch_channel, drive, 318 acer_udma[drvp->UDMA_mode]); 319 /* XXX disable if one drive < UDMA3 ? */ 320 if (drvp->UDMA_mode >= 3) { 321 pciide_pci_write(sc->sc_pc, sc->sc_tag, 322 ACER_0x4B, 323 pciide_pci_read(sc->sc_pc, sc->sc_tag, 324 ACER_0x4B) | ACER_0x4B_UDMA66); 325 } 326 } else { 327 /* 328 * use Multiword DMA 329 * Timings will be used for both PIO and DMA, 330 * so adjust DMA mode if needed 331 */ 332 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 333 drvp->PIO_mode = drvp->DMA_mode + 2; 334 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 335 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 336 drvp->PIO_mode - 2 : 0; 337 if (drvp->DMA_mode == 0) 338 drvp->PIO_mode = 0; 339 } 340 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 341 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 342 ACER_IDETIM(chp->ch_channel, drive), 343 acer_pio[drvp->PIO_mode]); 344 } 345 ATADEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 346 acer_fifo_udma), DEBUG_PROBE); 347 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 348 if (idedma_ctl != 0) { 349 /* Add software bits in status register */ 350 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 351 idedma_ctl); 352 } 353 } 354 355 static int 356 acer_pci_intr(void *arg) 357 { 358 struct pciide_softc *sc = arg; 359 struct pciide_channel *cp; 360 struct ata_channel *wdc_cp; 361 int i, rv, crv; 362 u_int32_t chids; 363 364 rv = 0; 365 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 366 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 367 cp = &sc->pciide_channels[i]; 368 wdc_cp = &cp->ata_channel; 369 /* If a compat channel skip. */ 370 if (cp->compat) 371 continue; 372 if (chids & ACER_CHIDS_INT(i)) { 373 crv = wdcintr(wdc_cp); 374 if (crv == 0) { 375 aprint_error("%s:%d: bogus intr\n", 376 device_xname( 377 sc->sc_wdcdev.sc_atac.atac_dev), i); 378 pciide_irqack(wdc_cp); 379 } else 380 rv = 1; 381 } 382 } 383 return rv; 384 } 385 386 static int 387 acer_dma_init(void *v, int channel, int drive, void *databuf, 388 size_t datalen, int flags) 389 { 390 391 /* use PIO for LBA48 transfer */ 392 if (flags & WDC_DMA_LBA48) 393 return EINVAL; 394 395 return pciide_dma_init(v, channel, drive, databuf, datalen, flags); 396 } 397
Indexes created Wed Oct 22 00:09:40 GMT 2025