aceride.c revision 1.35.2.3
1 /* $NetBSD: aceride.c,v 1.35.2.3 2017/12/03 11:37:07 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: aceride.c,v 1.35.2.3 2017/12/03 11:37:07 jdolecek Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 33 #include <dev/pci/pcivar.h> 34 #include <dev/pci/pcidevs.h> 35 #include <dev/pci/pciidereg.h> 36 #include <dev/pci/pciidevar.h> 37 #include <dev/pci/pciide_acer_reg.h> 38 39 static int acer_pcib_match(const struct pci_attach_args *); 40 static void acer_do_reset(struct ata_channel *, int); 41 static void acer_chip_map(struct pciide_softc*, const struct pci_attach_args*); 42 static void acer_setup_channel(struct ata_channel*); 43 static int acer_pci_intr(void *); 44 static int acer_dma_init(void *, int, int, void *, size_t, int); 45 46 static int aceride_match(device_t, cfdata_t, void *); 47 static void aceride_attach(device_t, device_t, void *); 48 49 struct aceride_softc { 50 struct pciide_softc pciide_sc; 51 struct pci_attach_args pcib_pa; 52 }; 53 54 CFATTACH_DECL_NEW(aceride, sizeof(struct aceride_softc), 55 aceride_match, aceride_attach, pciide_detach, NULL); 56 57 static const struct pciide_product_desc pciide_acer_products[] = { 58 { PCI_PRODUCT_ALI_M5229, 59 0, 60 "Acer Labs M5229 UDMA IDE Controller", 61 acer_chip_map, 62 }, 63 { 0, 64 0, 65 NULL, 66 NULL 67 } 68 }; 69 70 static int 71 aceride_match(device_t parent, cfdata_t match, void *aux) 72 { 73 struct pci_attach_args *pa = aux; 74 75 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI && 76 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 77 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 78 if (pciide_lookup_product(pa->pa_id, pciide_acer_products)) 79 return (2); 80 } 81 return (0); 82 } 83 84 static void 85 aceride_attach(device_t parent, device_t self, void *aux) 86 { 87 struct pci_attach_args *pa = aux; 88 struct pciide_softc *sc = device_private(self); 89 90 self->dv_maxphys = MIN(parent->dv_maxphys, MACHINE_MAXPHYS); 91 92 sc->sc_wdcdev.sc_atac.atac_dev = self; 93 94 pciide_common_attach(sc, pa, 95 pciide_lookup_product(pa->pa_id, pciide_acer_products)); 96 } 97 98 static int 99 acer_pcib_match(const struct pci_attach_args *pa) 100 { 101 /* 102 * we need to access the PCI config space of the pcib, see 103 * acer_do_reset() 104 */ 105 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 106 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 107 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI && 108 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M1533) 109 return 1; 110 return 0; 111 } 112 113 static void 114 acer_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 115 { 116 struct pciide_channel *cp; 117 int channel; 118 pcireg_t cr, interface; 119 pcireg_t rev = PCI_REVISION(pa->pa_class); 120 struct aceride_softc *acer_sc = (struct aceride_softc *)sc; 121 122 if (pciide_chipen(sc, pa) == 0) 123 return; 124 125 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 126 "bus-master DMA support present"); 127 pciide_mapreg_dma(sc, pa); 128 aprint_verbose("\n"); 129 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 130 if (sc->sc_dma_ok) { 131 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 132 if (rev >= 0x20) { 133 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 134 if (rev >= 0xC7) 135 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 136 else if (rev >= 0xC4) 137 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 138 else if (rev >= 0xC2) 139 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 140 else 141 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 142 } 143 sc->sc_wdcdev.irqack = pciide_irqack; 144 if (rev <= 0xc4) { 145 sc->sc_wdcdev.dma_init = acer_dma_init; 146 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 147 "using PIO transfers above 137GB as workaround for " 148 "48bit DMA access bug, expect reduced performance\n"); 149 } 150 } 151 152 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 153 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 154 sc->sc_wdcdev.sc_atac.atac_set_modes = acer_setup_channel; 155 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 156 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 157 sc->sc_wdcdev.wdc_maxdrives = 2; 158 159 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 160 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 161 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 162 163 /* Enable "microsoft register bits" R/W. */ 164 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 165 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 166 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 167 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 168 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 169 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 170 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 171 ~ACER_CHANSTATUSREGS_RO); 172 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 173 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 174 175 { 176 /* 177 * some BIOSes (port-cats ABLE) enable native mode, but don't 178 * setup everything correctly, so allow the forcing of 179 * compat mode 180 */ 181 bool force_compat_mode; 182 bool property_is_set; 183 property_is_set = prop_dictionary_get_bool( 184 device_properties(sc->sc_wdcdev.sc_atac.atac_dev), 185 "ali1543-ide-force-compat-mode", 186 &force_compat_mode); 187 if (property_is_set && force_compat_mode) { 188 cr &= ~((PCIIDE_INTERFACE_PCI(0) 189 | PCIIDE_INTERFACE_PCI(1)) 190 << PCI_INTERFACE_SHIFT); 191 } 192 } 193 194 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 195 /* Don't use cr, re-read the real register content instead */ 196 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 197 PCI_CLASS_REG)); 198 199 if (rev >= 0xC2) { 200 /* From FreeBSD: use device interrupt as byte count end */ 201 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4A, 202 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) 203 | ACER_0x4A_BCEINT); 204 205 /* From linux: enable "Cable Detection" */ 206 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 207 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 208 | ACER_0x4B_CDETECT); 209 } 210 211 wdc_allocate_regs(&sc->sc_wdcdev); 212 if (rev == 0xC3) { 213 /* install reset bug workaround */ 214 if (pci_find_device(&acer_sc->pcib_pa, acer_pcib_match) == 0) { 215 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 216 "WARNING: can't find pci-isa bridge\n"); 217 } else 218 sc->sc_wdcdev.reset = acer_do_reset; 219 } 220 221 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 222 channel++) { 223 cp = &sc->pciide_channels[channel]; 224 if (pciide_chansetup(sc, channel, interface) == 0) 225 continue; 226 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 227 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 228 "%s channel ignored (disabled)\n", cp->name); 229 cp->ata_channel.ch_flags |= ATACH_DISABLED; 230 continue; 231 } 232 /* newer controllers seems to lack the ACER_CHIDS. Sigh */ 233 pciide_mapchan(pa, cp, interface, 234 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 235 } 236 } 237 238 static void 239 acer_do_reset(struct ata_channel *chp, int poll) 240 { 241 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 242 struct aceride_softc *acer_sc = (struct aceride_softc *)sc; 243 u_int8_t reg; 244 245 /* 246 * From OpenSolaris: after a reset we need to disable/enable the 247 * corresponding channel, or data corruption will occur in 248 * UltraDMA modes 249 */ 250 251 wdc_do_reset(chp, poll); 252 reg = pciide_pci_read(acer_sc->pcib_pa.pa_pc, acer_sc->pcib_pa.pa_tag, 253 ACER_PCIB_CTRL); 254 pciide_pci_write(acer_sc->pcib_pa.pa_pc, acer_sc->pcib_pa.pa_tag, 255 ACER_PCIB_CTRL, reg & ~ACER_PCIB_CTRL_ENCHAN(chp->ch_channel)); 256 delay(1000); 257 pciide_pci_write(acer_sc->pcib_pa.pa_pc, acer_sc->pcib_pa.pa_tag, 258 ACER_PCIB_CTRL, reg); 259 } 260 261 static void 262 acer_setup_channel(struct ata_channel *chp) 263 { 264 struct ata_drive_datas *drvp; 265 int drive, s; 266 u_int32_t acer_fifo_udma; 267 u_int32_t idedma_ctl; 268 struct pciide_channel *cp = (struct pciide_channel*)chp; 269 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 270 271 idedma_ctl = 0; 272 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 273 ATADEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 274 acer_fifo_udma), DEBUG_PROBE); 275 /* setup DMA if needed */ 276 pciide_channel_dma_setup(cp); 277 278 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 279 ATA_DRIVE_UDMA) { /* check 80 pins cable */ 280 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 281 ACER_0x4A_80PIN(chp->ch_channel)) { 282 if (chp->ch_drive[0].UDMA_mode > 2) 283 chp->ch_drive[0].UDMA_mode = 2; 284 if (chp->ch_drive[1].UDMA_mode > 2) 285 chp->ch_drive[1].UDMA_mode = 2; 286 } 287 } 288 289 for (drive = 0; drive < 2; drive++) { 290 drvp = &chp->ch_drive[drive]; 291 /* If no drive, skip */ 292 if (drvp->drive_type == ATA_DRIVET_NONE) 293 continue; 294 ATADEBUG_PRINT(("acer_setup_channel: old timings reg for " 295 "channel %d drive %d 0x%x\n", chp->ch_channel, drive, 296 pciide_pci_read(sc->sc_pc, sc->sc_tag, 297 ACER_IDETIM(chp->ch_channel, drive))), DEBUG_PROBE); 298 /* clear FIFO/DMA mode */ 299 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->ch_channel, drive, 0x3) | 300 ACER_UDMA_EN(chp->ch_channel, drive) | 301 ACER_UDMA_TIM(chp->ch_channel, drive, 0x7)); 302 303 /* add timing values, setup DMA if needed */ 304 if ((drvp->drive_flags & ATA_DRIVE_DMA) == 0 && 305 (drvp->drive_flags & ATA_DRIVE_UDMA) == 0) { 306 acer_fifo_udma |= 307 ACER_FTH_OPL(chp->ch_channel, drive, 0x1); 308 goto pio; 309 } 310 311 acer_fifo_udma |= ACER_FTH_OPL(chp->ch_channel, drive, 0x2); 312 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 313 /* use Ultra/DMA */ 314 s = splbio(); 315 drvp->drive_flags &= ~ATA_DRIVE_DMA; 316 splx(s); 317 acer_fifo_udma |= ACER_UDMA_EN(chp->ch_channel, drive); 318 acer_fifo_udma |= 319 ACER_UDMA_TIM(chp->ch_channel, drive, 320 acer_udma[drvp->UDMA_mode]); 321 /* XXX disable if one drive < UDMA3 ? */ 322 if (drvp->UDMA_mode >= 3) { 323 pciide_pci_write(sc->sc_pc, sc->sc_tag, 324 ACER_0x4B, 325 pciide_pci_read(sc->sc_pc, sc->sc_tag, 326 ACER_0x4B) | ACER_0x4B_UDMA66); 327 } 328 } else { 329 /* 330 * use Multiword DMA 331 * Timings will be used for both PIO and DMA, 332 * so adjust DMA mode if needed 333 */ 334 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 335 drvp->PIO_mode = drvp->DMA_mode + 2; 336 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 337 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 338 drvp->PIO_mode - 2 : 0; 339 if (drvp->DMA_mode == 0) 340 drvp->PIO_mode = 0; 341 } 342 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 343 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 344 ACER_IDETIM(chp->ch_channel, drive), 345 acer_pio[drvp->PIO_mode]); 346 } 347 ATADEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 348 acer_fifo_udma), DEBUG_PROBE); 349 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 350 if (idedma_ctl != 0) { 351 /* Add software bits in status register */ 352 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 353 idedma_ctl); 354 } 355 } 356 357 static int 358 acer_pci_intr(void *arg) 359 { 360 struct pciide_softc *sc = arg; 361 struct pciide_channel *cp; 362 struct ata_channel *wdc_cp; 363 int i, rv, crv; 364 u_int32_t chids; 365 366 rv = 0; 367 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 368 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 369 cp = &sc->pciide_channels[i]; 370 wdc_cp = &cp->ata_channel; 371 /* If a compat channel skip. */ 372 if (cp->compat) 373 continue; 374 if (chids & ACER_CHIDS_INT(i)) { 375 crv = wdcintr(wdc_cp); 376 if (crv == 0) { 377 aprint_error("%s:%d: bogus intr\n", 378 device_xname( 379 sc->sc_wdcdev.sc_atac.atac_dev), i); 380 pciide_irqack(wdc_cp); 381 } else 382 rv = 1; 383 } 384 } 385 return rv; 386 } 387 388 static int 389 acer_dma_init(void *v, int channel, int drive, void *databuf, 390 size_t datalen, int flags) 391 { 392 393 /* use PIO for LBA48 transfer */ 394 if (flags & WDC_DMA_LBA48) 395 return EINVAL; 396 397 return pciide_dma_init(v, channel, drive, databuf, datalen, flags); 398 } 399
Indexes created Wed Oct 22 06:10:02 GMT 2025