aceride.c revision 1.8
1 /* $NetBSD: aceride.c,v 1.8 2004/08/13 03:12:59 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_acer_reg.h> 40 41 static void acer_chip_map(struct pciide_softc*, struct pci_attach_args*); 42 static void acer_setup_channel(struct wdc_channel*); 43 static int acer_pci_intr(void *); 44 45 static int aceride_match(struct device *, struct cfdata *, void *); 46 static void aceride_attach(struct device *, struct device *, void *); 47 48 CFATTACH_DECL(aceride, sizeof(struct pciide_softc), 49 aceride_match, aceride_attach, NULL, NULL); 50 51 static const struct pciide_product_desc pciide_acer_products[] = { 52 { PCI_PRODUCT_ALI_M5229, 53 0, 54 "Acer Labs M5229 UDMA IDE Controller", 55 acer_chip_map, 56 }, 57 { 0, 58 0, 59 NULL, 60 NULL 61 } 62 }; 63 64 static int 65 aceride_match(struct device *parent, struct cfdata *match, void *aux) 66 { 67 struct pci_attach_args *pa = aux; 68 69 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI && 70 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 71 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 72 if (pciide_lookup_product(pa->pa_id, pciide_acer_products)) 73 return (2); 74 } 75 return (0); 76 } 77 78 static void 79 aceride_attach(struct device *parent, struct device *self, void *aux) 80 { 81 struct pci_attach_args *pa = aux; 82 struct pciide_softc *sc = (struct pciide_softc *)self; 83 84 pciide_common_attach(sc, pa, 85 pciide_lookup_product(pa->pa_id, pciide_acer_products)); 86 87 } 88 89 static void 90 acer_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 91 { 92 struct pciide_channel *cp; 93 int channel; 94 pcireg_t cr, interface; 95 bus_size_t cmdsize, ctlsize; 96 pcireg_t rev = PCI_REVISION(pa->pa_class); 97 98 if (pciide_chipen(sc, pa) == 0) 99 return; 100 101 aprint_normal("%s: bus-master DMA support present", 102 sc->sc_wdcdev.sc_dev.dv_xname); 103 pciide_mapreg_dma(sc, pa); 104 aprint_normal("\n"); 105 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32; 106 if (sc->sc_dma_ok) { 107 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 108 if (rev >= 0x20) { 109 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 110 if (rev >= 0xC4) 111 sc->sc_wdcdev.UDMA_cap = 5; 112 else if (rev >= 0xC2) 113 sc->sc_wdcdev.UDMA_cap = 4; 114 else 115 sc->sc_wdcdev.UDMA_cap = 2; 116 } 117 sc->sc_wdcdev.irqack = pciide_irqack; 118 } 119 120 sc->sc_wdcdev.PIO_cap = 4; 121 sc->sc_wdcdev.DMA_cap = 2; 122 sc->sc_wdcdev.set_modes = acer_setup_channel; 123 sc->sc_wdcdev.channels = sc->wdc_chanarray; 124 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 125 126 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 127 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 128 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 129 130 /* Enable "microsoft register bits" R/W. */ 131 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 132 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 133 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 134 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 135 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 136 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 137 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 138 ~ACER_CHANSTATUSREGS_RO); 139 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 140 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 141 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 142 /* Don't use cr, re-read the real register content instead */ 143 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 144 PCI_CLASS_REG)); 145 146 /* From linux: enable "Cable Detection" */ 147 if (rev >= 0xC2) { 148 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 149 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 150 | ACER_0x4B_CDETECT); 151 } 152 153 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 154 cp = &sc->pciide_channels[channel]; 155 if (pciide_chansetup(sc, channel, interface) == 0) 156 continue; 157 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 158 aprint_normal("%s: %s channel ignored (disabled)\n", 159 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 160 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 161 continue; 162 } 163 /* newer controllers seems to lack the ACER_CHIDS. Sigh */ 164 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 165 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 166 } 167 } 168 169 static void 170 acer_setup_channel(struct wdc_channel *chp) 171 { 172 struct ata_drive_datas *drvp; 173 int drive; 174 u_int32_t acer_fifo_udma; 175 u_int32_t idedma_ctl; 176 struct pciide_channel *cp = (struct pciide_channel*)chp; 177 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 178 179 idedma_ctl = 0; 180 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 181 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 182 acer_fifo_udma), DEBUG_PROBE); 183 /* setup DMA if needed */ 184 pciide_channel_dma_setup(cp); 185 186 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 187 DRIVE_UDMA) { /* check 80 pins cable */ 188 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 189 ACER_0x4A_80PIN(chp->ch_channel)) { 190 if (chp->ch_drive[0].UDMA_mode > 2) 191 chp->ch_drive[0].UDMA_mode = 2; 192 if (chp->ch_drive[1].UDMA_mode > 2) 193 chp->ch_drive[1].UDMA_mode = 2; 194 } 195 } 196 197 for (drive = 0; drive < 2; drive++) { 198 drvp = &chp->ch_drive[drive]; 199 /* If no drive, skip */ 200 if ((drvp->drive_flags & DRIVE) == 0) 201 continue; 202 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 203 "channel %d drive %d 0x%x\n", chp->ch_channel, drive, 204 pciide_pci_read(sc->sc_pc, sc->sc_tag, 205 ACER_IDETIM(chp->ch_channel, drive))), DEBUG_PROBE); 206 /* clear FIFO/DMA mode */ 207 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->ch_channel, drive, 0x3) | 208 ACER_UDMA_EN(chp->ch_channel, drive) | 209 ACER_UDMA_TIM(chp->ch_channel, drive, 0x7)); 210 211 /* add timing values, setup DMA if needed */ 212 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 213 (drvp->drive_flags & DRIVE_UDMA) == 0) { 214 acer_fifo_udma |= 215 ACER_FTH_OPL(chp->ch_channel, drive, 0x1); 216 goto pio; 217 } 218 219 acer_fifo_udma |= ACER_FTH_OPL(chp->ch_channel, drive, 0x2); 220 if (drvp->drive_flags & DRIVE_UDMA) { 221 /* use Ultra/DMA */ 222 drvp->drive_flags &= ~DRIVE_DMA; 223 acer_fifo_udma |= ACER_UDMA_EN(chp->ch_channel, drive); 224 acer_fifo_udma |= 225 ACER_UDMA_TIM(chp->ch_channel, drive, 226 acer_udma[drvp->UDMA_mode]); 227 /* XXX disable if one drive < UDMA3 ? */ 228 if (drvp->UDMA_mode >= 3) { 229 pciide_pci_write(sc->sc_pc, sc->sc_tag, 230 ACER_0x4B, 231 pciide_pci_read(sc->sc_pc, sc->sc_tag, 232 ACER_0x4B) | ACER_0x4B_UDMA66); 233 } 234 } else { 235 /* 236 * use Multiword DMA 237 * Timings will be used for both PIO and DMA, 238 * so adjust DMA mode if needed 239 */ 240 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 241 drvp->PIO_mode = drvp->DMA_mode + 2; 242 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 243 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 244 drvp->PIO_mode - 2 : 0; 245 if (drvp->DMA_mode == 0) 246 drvp->PIO_mode = 0; 247 } 248 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 249 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 250 ACER_IDETIM(chp->ch_channel, drive), 251 acer_pio[drvp->PIO_mode]); 252 } 253 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 254 acer_fifo_udma), DEBUG_PROBE); 255 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 256 if (idedma_ctl != 0) { 257 /* Add software bits in status register */ 258 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 259 idedma_ctl); 260 } 261 } 262 263 static int 264 acer_pci_intr(void *arg) 265 { 266 struct pciide_softc *sc = arg; 267 struct pciide_channel *cp; 268 struct wdc_channel *wdc_cp; 269 int i, rv, crv; 270 u_int32_t chids; 271 272 rv = 0; 273 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 274 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 275 cp = &sc->pciide_channels[i]; 276 wdc_cp = &cp->wdc_channel; 277 /* If a compat channel skip. */ 278 if (cp->compat) 279 continue; 280 if (chids & ACER_CHIDS_INT(i)) { 281 crv = wdcintr(wdc_cp); 282 if (crv == 0) { 283 printf("%s:%d: bogus intr\n", 284 sc->sc_wdcdev.sc_dev.dv_xname, i); 285 pciide_irqack(wdc_cp); 286 } else 287 rv = 1; 288 } 289 } 290 return rv; 291 } 292
Indexes created Wed Sep 24 05:09:52 GMT 2025