adv_pci.c revision 1.21 1 1.21 ad /* $NetBSD: adv_pci.c,v 1.21 2007/10/19 12:00:38 ad Exp $ */
2 1.2 dante
3 1.1 dante /*
4 1.1 dante * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved.
5 1.16 perry *
6 1.1 dante * Author: Baldassare Dante Profeta <dante (at) mclink.it>
7 1.16 perry *
8 1.1 dante * Redistribution and use in source and binary forms, with or without
9 1.3 dante * modification, are permitted provided that the following conditions
10 1.3 dante * are met:
11 1.3 dante * 1. Redistributions of source code must retain the above copyright
12 1.3 dante * notice, this list of conditions and the following disclaimer.
13 1.3 dante * 2. Redistributions in binary form must reproduce the above copyright
14 1.3 dante * notice, this list of conditions and the following disclaimer in the
15 1.3 dante * documentation and/or other materials provided with the distribution.
16 1.3 dante * 3. All advertising materials mentioning features or use of this software
17 1.3 dante * must display the following acknowledgement:
18 1.4 dante * This product includes software developed by the NetBSD
19 1.4 dante * Foundation, Inc. and its contributors.
20 1.3 dante * 4. Neither the name of The NetBSD Foundation nor the names of its
21 1.3 dante * contributors may be used to endorse or promote products derived
22 1.3 dante * from this software without specific prior written permission.
23 1.4 dante *
24 1.1 dante * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 1.4 dante * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 1.4 dante * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 1.4 dante * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 1.4 dante * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 1.4 dante * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 1.4 dante * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 1.4 dante * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 1.4 dante * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 1.4 dante * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 1.4 dante * POSSIBILITY OF SUCH DAMAGE.
35 1.1 dante */
36 1.1 dante /*
37 1.1 dante * Device probe and attach routines for the following
38 1.1 dante * Advanced Systems Inc. SCSI controllers:
39 1.1 dante *
40 1.1 dante * Connectivity Products:
41 1.1 dante * ABP920 - Bus-Master PCI (16 CDB)
42 1.5 dante * ABP930 - Bus-Master PCI (16 CDB) (Footnote 1)
43 1.1 dante * ABP930U - Bus-Master PCI Ultra (16 CDB)
44 1.1 dante * ABP930UA - Bus-Master PCI Ultra (16 CDB)
45 1.5 dante * ABP960 - Bus-Master PCI MAC/PC (16 CDB) (Footnote 2)
46 1.5 dante * ABP960U - Bus-Master PCI MAC/PC Ultra (16 CDB) (Footnote 2)
47 1.1 dante *
48 1.1 dante * Single Channel Products:
49 1.1 dante * ABP940 - Bus-Master PCI (240 CDB)
50 1.1 dante * ABP940U - Bus-Master PCI Ultra (240 CDB)
51 1.1 dante * ABP970 - Bus-Master PCI MAC/PC (240 CDB)
52 1.1 dante * ABP970U - Bus-Master PCI MAC/PC Ultra (240 CDB)
53 1.1 dante * ABP940UW - Bus-Master PCI Ultra-Wide (240 CDB)
54 1.1 dante *
55 1.1 dante * Multi Channel Products:
56 1.1 dante * ABP950 - Dual Channel Bus-Master PCI (240 CDB Per Channel)
57 1.1 dante * ABP980 - Four Channel Bus-Master PCI (240 CDB Per Channel)
58 1.1 dante * ABP980U - Four Channel Bus-Master PCI Ultra (240 CDB Per Channel)
59 1.1 dante *
60 1.1 dante * Footnotes:
61 1.5 dante * 1. This board has been sold by SIIG as the Fast SCSI Pro PCI.
62 1.5 dante * 2. This board has been sold by Iomega as a Jaz Jet PCI adapter.
63 1.1 dante */
64 1.9 lukem
65 1.9 lukem #include <sys/cdefs.h>
66 1.21 ad __KERNEL_RCSID(0, "$NetBSD: adv_pci.c,v 1.21 2007/10/19 12:00:38 ad Exp $");
67 1.1 dante
68 1.1 dante #include <sys/param.h>
69 1.1 dante #include <sys/systm.h>
70 1.1 dante #include <sys/malloc.h>
71 1.1 dante #include <sys/kernel.h>
72 1.1 dante #include <sys/queue.h>
73 1.1 dante #include <sys/device.h>
74 1.1 dante
75 1.21 ad #include <sys/bus.h>
76 1.21 ad #include <sys/intr.h>
77 1.1 dante
78 1.1 dante #include <dev/scsipi/scsi_all.h>
79 1.1 dante #include <dev/scsipi/scsipi_all.h>
80 1.1 dante #include <dev/scsipi/scsiconf.h>
81 1.1 dante
82 1.1 dante #include <dev/pci/pcireg.h>
83 1.1 dante #include <dev/pci/pcivar.h>
84 1.1 dante #include <dev/pci/pcidevs.h>
85 1.1 dante
86 1.6 dante #include <dev/ic/advlib.h>
87 1.1 dante #include <dev/ic/adv.h>
88 1.1 dante
89 1.1 dante /******************************************************************************/
90 1.1 dante
91 1.1 dante #define PCI_BASEADR_IO 0x10
92 1.1 dante
93 1.1 dante /******************************************************************************/
94 1.1 dante /*
95 1.1 dante * Check the slots looking for a board we recognise
96 1.1 dante * If we find one, note it's address (slot) and call
97 1.1 dante * the actual probe routine to check it out.
98 1.1 dante */
99 1.17 thorpej static int
100 1.20 christos adv_pci_match(struct device *parent, struct cfdata *match,
101 1.19 christos void *aux)
102 1.1 dante {
103 1.1 dante struct pci_attach_args *pa = aux;
104 1.1 dante
105 1.1 dante if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ADVSYS)
106 1.1 dante switch (PCI_PRODUCT(pa->pa_id)) {
107 1.1 dante case PCI_PRODUCT_ADVSYS_1200A:
108 1.1 dante case PCI_PRODUCT_ADVSYS_1200B:
109 1.1 dante case PCI_PRODUCT_ADVSYS_ULTRA:
110 1.1 dante return (1);
111 1.1 dante }
112 1.1 dante
113 1.1 dante return 0;
114 1.1 dante }
115 1.1 dante
116 1.17 thorpej static void
117 1.20 christos adv_pci_attach(struct device *parent, struct device *self, void *aux)
118 1.1 dante {
119 1.1 dante struct pci_attach_args *pa = aux;
120 1.1 dante ASC_SOFTC *sc = (void *) self;
121 1.1 dante bus_space_tag_t iot;
122 1.1 dante bus_space_handle_t ioh;
123 1.1 dante pci_intr_handle_t ih;
124 1.1 dante pci_chipset_tag_t pc = pa->pa_pc;
125 1.1 dante u_int32_t command;
126 1.1 dante const char *intrstr;
127 1.1 dante
128 1.14 thorpej aprint_naive(": SCSI controller\n");
129 1.1 dante
130 1.1 dante sc->sc_flags = 0x0;
131 1.1 dante if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ADVSYS)
132 1.1 dante switch (PCI_PRODUCT(pa->pa_id)) {
133 1.1 dante case PCI_PRODUCT_ADVSYS_1200A:
134 1.14 thorpej aprint_normal(": AdvanSys ASC1200A SCSI adapter\n");
135 1.1 dante break;
136 1.1 dante
137 1.1 dante case PCI_PRODUCT_ADVSYS_1200B:
138 1.14 thorpej aprint_normal(": AdvanSys ASC1200B SCSI adapter\n");
139 1.1 dante break;
140 1.1 dante
141 1.1 dante case PCI_PRODUCT_ADVSYS_ULTRA:
142 1.1 dante switch (PCI_REVISION(pa->pa_class)) {
143 1.1 dante case ASC_PCI_REVISION_3050:
144 1.14 thorpej aprint_normal(
145 1.14 thorpej ": AdvanSys ABP-9xxUA SCSI adapter\n");
146 1.1 dante break;
147 1.1 dante
148 1.1 dante case ASC_PCI_REVISION_3150:
149 1.14 thorpej aprint_normal(
150 1.14 thorpej ": AdvanSys ABP-9xxU SCSI adapter\n");
151 1.1 dante break;
152 1.1 dante }
153 1.1 dante break;
154 1.1 dante
155 1.1 dante default:
156 1.14 thorpej aprint_error(": unknown model!\n");
157 1.1 dante return;
158 1.1 dante }
159 1.1 dante
160 1.1 dante
161 1.1 dante /*
162 1.1 dante * Make sure IO/MEM/MASTER are enabled
163 1.1 dante */
164 1.1 dante command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
165 1.1 dante if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
166 1.1 dante PCI_COMMAND_MASTER_ENABLE)) !=
167 1.1 dante (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
168 1.1 dante PCI_COMMAND_MASTER_ENABLE)) {
169 1.1 dante pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
170 1.1 dante command | (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
171 1.1 dante PCI_COMMAND_MASTER_ENABLE));
172 1.1 dante }
173 1.1 dante /*
174 1.1 dante * Latency timer settings.
175 1.1 dante */
176 1.1 dante {
177 1.1 dante u_int32_t bhlcr;
178 1.1 dante
179 1.1 dante bhlcr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
180 1.1 dante
181 1.1 dante if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADVSYS_1200A ||
182 1.1 dante PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADVSYS_1200B) {
183 1.1 dante bhlcr &= 0xFFFF00FFul;
184 1.4 dante pci_conf_write(pa->pa_pc, pa->pa_tag,
185 1.4 dante PCI_BHLC_REG, bhlcr);
186 1.7 dante } else if ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADVSYS_ULTRA)
187 1.7 dante && (PCI_LATTIMER(bhlcr) < 0x20)) {
188 1.1 dante bhlcr &= 0xFFFF00FFul;
189 1.1 dante bhlcr |= 0x00002000ul;
190 1.4 dante pci_conf_write(pa->pa_pc, pa->pa_tag,
191 1.4 dante PCI_BHLC_REG, bhlcr);
192 1.1 dante }
193 1.1 dante }
194 1.1 dante
195 1.1 dante
196 1.1 dante /*
197 1.1 dante * Map Device Registers for I/O
198 1.1 dante */
199 1.1 dante if (pci_mapreg_map(pa, PCI_BASEADR_IO, PCI_MAPREG_TYPE_IO, 0,
200 1.1 dante &iot, &ioh, NULL, NULL)) {
201 1.14 thorpej aprint_error("%s: unable to map device registers\n",
202 1.1 dante sc->sc_dev.dv_xname);
203 1.1 dante return;
204 1.1 dante }
205 1.7 dante
206 1.7 dante ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT);
207 1.7 dante ASC_SET_CHIP_STATUS(iot, ioh, 0);
208 1.7 dante
209 1.1 dante sc->sc_iot = iot;
210 1.1 dante sc->sc_ioh = ioh;
211 1.1 dante sc->sc_dmat = pa->pa_dmat;
212 1.1 dante sc->pci_device_id = pa->pa_id;
213 1.1 dante sc->bus_type = ASC_IS_PCI;
214 1.7 dante sc->chip_version = ASC_GET_CHIP_VER_NO(iot, ioh);
215 1.1 dante
216 1.1 dante /*
217 1.1 dante * Initialize the board
218 1.1 dante */
219 1.1 dante if (adv_init(sc))
220 1.1 dante panic("adv_pci_attach: adv_init failed");
221 1.1 dante
222 1.1 dante /*
223 1.1 dante * Map Interrupt line
224 1.1 dante */
225 1.8 sommerfe if (pci_intr_map(pa, &ih)) {
226 1.14 thorpej aprint_error("%s: couldn't map interrupt\n",
227 1.14 thorpej sc->sc_dev.dv_xname);
228 1.1 dante return;
229 1.1 dante }
230 1.1 dante intrstr = pci_intr_string(pc, ih);
231 1.1 dante
232 1.1 dante /*
233 1.1 dante * Establish Interrupt handler
234 1.1 dante */
235 1.1 dante sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, adv_intr, sc);
236 1.1 dante if (sc->sc_ih == NULL) {
237 1.14 thorpej aprint_error("%s: couldn't establish interrupt",
238 1.14 thorpej sc->sc_dev.dv_xname);
239 1.1 dante if (intrstr != NULL)
240 1.14 thorpej aprint_normal(" at %s", intrstr);
241 1.14 thorpej aprint_normal("\n");
242 1.1 dante return;
243 1.1 dante }
244 1.14 thorpej aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
245 1.1 dante
246 1.1 dante /*
247 1.1 dante * Attach all the sub-devices we can find
248 1.1 dante */
249 1.1 dante adv_attach(sc);
250 1.1 dante }
251 1.17 thorpej
252 1.17 thorpej CFATTACH_DECL(adv_pci, sizeof(ASC_SOFTC),
253 1.17 thorpej adv_pci_match, adv_pci_attach, NULL, NULL);
254