adv_pci.c revision 1.3 1 1.3 dante /* $NetBSD: adv_pci.c,v 1.3 1998/08/29 13:54:50 dante Exp $ */
2 1.2 dante
3 1.1 dante /*
4 1.1 dante * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved.
5 1.1 dante *
6 1.1 dante * Author: Baldassare Dante Profeta <dante (at) mclink.it>
7 1.1 dante *
8 1.1 dante * Redistribution and use in source and binary forms, with or without
9 1.3 dante * modification, are permitted provided that the following conditions
10 1.3 dante * are met:
11 1.3 dante * 1. Redistributions of source code must retain the above copyright
12 1.3 dante * notice, this list of conditions and the following disclaimer.
13 1.3 dante * 2. Redistributions in binary form must reproduce the above copyright
14 1.3 dante * notice, this list of conditions and the following disclaimer in the
15 1.3 dante * documentation and/or other materials provided with the distribution.
16 1.3 dante * 3. All advertising materials mentioning features or use of this software
17 1.3 dante * must display the following acknowledgement:
18 1.3 dante * This product includes software developed by the NetBSD
19 1.3 dante * Foundation, Inc. and its contributors.
20 1.3 dante * 4. Neither the name of The NetBSD Foundation nor the names of its
21 1.3 dante * contributors may be used to endorse or promote products derived
22 1.3 dante * from this software without specific prior written permission.
23 1.1 dante *
24 1.1 dante * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 1.1 dante * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 1.1 dante * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
27 1.1 dante * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR
28 1.1 dante * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 1.1 dante * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 1.1 dante * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 1.1 dante * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 1.1 dante * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 1.1 dante * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 1.1 dante * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 1.1 dante */
36 1.1 dante /*
37 1.1 dante * Device probe and attach routines for the following
38 1.1 dante * Advanced Systems Inc. SCSI controllers:
39 1.1 dante *
40 1.1 dante * Connectivity Products:
41 1.1 dante * ABP510/5150 - Bus-Master ISA (240 CDB) (Footnote 1)
42 1.1 dante * ABP5140 - Bus-Master ISA PnP (16 CDB) (Footnote 1, 3)
43 1.1 dante * ABP5142 - Bus-Master ISA PnP with floppy (16 CDB) (Footnote 4)
44 1.1 dante * ABP920 - Bus-Master PCI (16 CDB)
45 1.1 dante * ABP930 - Bus-Master PCI (16 CDB) (Footnote 5)
46 1.1 dante * ABP930U - Bus-Master PCI Ultra (16 CDB)
47 1.1 dante * ABP930UA - Bus-Master PCI Ultra (16 CDB)
48 1.1 dante * ABP960 - Bus-Master PCI MAC/PC (16 CDB) (Footnote 2)
49 1.1 dante * ABP960U - Bus-Master PCI MAC/PC Ultra (16 CDB) (Footnote 2)
50 1.1 dante *
51 1.1 dante * Single Channel Products:
52 1.1 dante * ABP542 - Bus-Master ISA with floppy (240 CDB)
53 1.1 dante * ABP742 - Bus-Master EISA (240 CDB)
54 1.1 dante * ABP842 - Bus-Master VL (240 CDB)
55 1.1 dante * ABP940 - Bus-Master PCI (240 CDB)
56 1.1 dante * ABP940U - Bus-Master PCI Ultra (240 CDB)
57 1.1 dante * ABP970 - Bus-Master PCI MAC/PC (240 CDB)
58 1.1 dante * ABP970U - Bus-Master PCI MAC/PC Ultra (240 CDB)
59 1.1 dante * ABP940UW - Bus-Master PCI Ultra-Wide (240 CDB)
60 1.1 dante *
61 1.1 dante * Multi Channel Products:
62 1.1 dante * ABP752 - Dual Channel Bus-Master EISA (240 CDB Per Channel)
63 1.1 dante * ABP852 - Dual Channel Bus-Master VL (240 CDB Per Channel)
64 1.1 dante * ABP950 - Dual Channel Bus-Master PCI (240 CDB Per Channel)
65 1.1 dante * ABP980 - Four Channel Bus-Master PCI (240 CDB Per Channel)
66 1.1 dante * ABP980U - Four Channel Bus-Master PCI Ultra (240 CDB Per Channel)
67 1.1 dante *
68 1.1 dante * Footnotes:
69 1.1 dante * 1. This board has been shipped by HP with the 4020i CD-R drive.
70 1.1 dante * The board has no BIOS so it cannot control a boot device, but
71 1.1 dante * it can control any secondary SCSI device.
72 1.1 dante * 2. This board has been sold by Iomega as a Jaz Jet PCI adapter.
73 1.1 dante * 3. This board has been sold by SIIG as the i540 SpeedMaster.
74 1.1 dante * 4. This board has been sold by SIIG as the i542 SpeedMaster.
75 1.1 dante * 5. This board has been sold by SIIG as the Fast SCSI Pro PCI.
76 1.1 dante *
77 1.1 dante */
78 1.1 dante
79 1.1 dante #include <sys/types.h>
80 1.1 dante #include <sys/param.h>
81 1.1 dante #include <sys/systm.h>
82 1.1 dante #include <sys/malloc.h>
83 1.1 dante #include <sys/kernel.h>
84 1.1 dante #include <sys/queue.h>
85 1.1 dante #include <sys/device.h>
86 1.1 dante
87 1.1 dante #include <machine/bus.h>
88 1.1 dante #include <machine/intr.h>
89 1.1 dante
90 1.1 dante #include <dev/scsipi/scsi_all.h>
91 1.1 dante #include <dev/scsipi/scsipi_all.h>
92 1.1 dante #include <dev/scsipi/scsiconf.h>
93 1.1 dante
94 1.1 dante #include <dev/pci/pcireg.h>
95 1.1 dante #include <dev/pci/pcivar.h>
96 1.1 dante #include <dev/pci/pcidevs.h>
97 1.1 dante
98 1.1 dante #include <dev/ic/adv.h>
99 1.1 dante #include <dev/ic/advlib.h>
100 1.1 dante
101 1.1 dante /******************************************************************************/
102 1.1 dante
103 1.1 dante #define PCI_BASEADR_IO 0x10
104 1.1 dante
105 1.1 dante /******************************************************************************/
106 1.1 dante
107 1.1 dante #ifdef __BROKEN_INDIRECT_CONFIG
108 1.1 dante int adv_pci_probe __P((struct device *, void *, void *));
109 1.1 dante #else
110 1.1 dante int adv_pci_probe __P((struct device *, struct cfdata *, void *));
111 1.1 dante #endif
112 1.1 dante void adv_pci_attach __P((struct device *, struct device *, void *));
113 1.1 dante
114 1.1 dante struct cfattach adv_pci_ca =
115 1.1 dante {
116 1.1 dante sizeof(ASC_SOFTC), adv_pci_probe, adv_pci_attach
117 1.1 dante };
118 1.1 dante
119 1.1 dante /******************************************************************************/
120 1.1 dante /*
121 1.1 dante * Check the slots looking for a board we recognise
122 1.1 dante * If we find one, note it's address (slot) and call
123 1.1 dante * the actual probe routine to check it out.
124 1.1 dante */
125 1.1 dante #ifdef __BROKEN_INDIRECT_CONFIG
126 1.1 dante int
127 1.1 dante adv_pci_probe(struct device * parent, void *match, void *aux)
128 1.1 dante #else
129 1.1 dante int
130 1.1 dante adv_pci_probe(struct device * parent, struct cfdata * match, void *aux)
131 1.1 dante #endif
132 1.1 dante {
133 1.1 dante struct pci_attach_args *pa = aux;
134 1.1 dante
135 1.1 dante if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ADVSYS)
136 1.1 dante switch (PCI_PRODUCT(pa->pa_id)) {
137 1.1 dante case PCI_PRODUCT_ADVSYS_1200A:
138 1.1 dante case PCI_PRODUCT_ADVSYS_1200B:
139 1.1 dante case PCI_PRODUCT_ADVSYS_ULTRA:
140 1.1 dante return (1);
141 1.1 dante case PCI_PRODUCT_ADVSYS_2300:
142 1.1 dante return (0);
143 1.1 dante }
144 1.1 dante
145 1.1 dante return 0;
146 1.1 dante }
147 1.1 dante
148 1.1 dante
149 1.1 dante void
150 1.1 dante adv_pci_attach(struct device * parent, struct device * self, void *aux)
151 1.1 dante {
152 1.1 dante struct pci_attach_args *pa = aux;
153 1.1 dante ASC_SOFTC *sc = (void *) self;
154 1.1 dante bus_space_tag_t iot;
155 1.1 dante bus_space_handle_t ioh;
156 1.1 dante pci_intr_handle_t ih;
157 1.1 dante pci_chipset_tag_t pc = pa->pa_pc;
158 1.1 dante u_int32_t command;
159 1.1 dante const char *intrstr;
160 1.1 dante
161 1.1 dante
162 1.1 dante sc->sc_flags = 0x0;
163 1.1 dante if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ADVSYS)
164 1.1 dante switch (PCI_PRODUCT(pa->pa_id)) {
165 1.1 dante case PCI_PRODUCT_ADVSYS_1200A:
166 1.1 dante printf(": AdvanSys ASC1200A SCSI\n");
167 1.1 dante break;
168 1.1 dante
169 1.1 dante case PCI_PRODUCT_ADVSYS_1200B:
170 1.1 dante printf(": AdvanSys ASC1200B SCSI\n");
171 1.1 dante break;
172 1.1 dante
173 1.1 dante case PCI_PRODUCT_ADVSYS_ULTRA:
174 1.1 dante switch (PCI_REVISION(pa->pa_class)) {
175 1.1 dante case ASC_PCI_REVISION_3050:
176 1.1 dante printf(": AdvanSys ASC3150 Ultra SCSI\n");
177 1.1 dante break;
178 1.1 dante
179 1.1 dante case ASC_PCI_REVISION_3150:
180 1.1 dante printf(": AdvanSys ASC3050 Ultra SCSI\n");
181 1.1 dante break;
182 1.1 dante }
183 1.1 dante break;
184 1.1 dante
185 1.1 dante case PCI_PRODUCT_ADVSYS_2300:
186 1.1 dante sc->sc_flags |= ASC_WIDE_BOARD;
187 1.1 dante printf("adv_pci_attach: Wide boards are not"
188 1.1 dante " supported yet");
189 1.1 dante break;
190 1.1 dante
191 1.1 dante default:
192 1.1 dante printf(": unknown model!\n");
193 1.1 dante return;
194 1.1 dante }
195 1.1 dante
196 1.1 dante
197 1.1 dante /*
198 1.1 dante * Make sure IO/MEM/MASTER are enabled
199 1.1 dante */
200 1.1 dante command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
201 1.1 dante if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
202 1.1 dante PCI_COMMAND_MASTER_ENABLE)) !=
203 1.1 dante (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
204 1.1 dante PCI_COMMAND_MASTER_ENABLE)) {
205 1.1 dante pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
206 1.1 dante command | (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
207 1.1 dante PCI_COMMAND_MASTER_ENABLE));
208 1.1 dante }
209 1.1 dante /*
210 1.1 dante * Latency timer settings.
211 1.1 dante */
212 1.1 dante {
213 1.1 dante u_int32_t bhlcr;
214 1.1 dante
215 1.1 dante bhlcr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
216 1.1 dante
217 1.1 dante if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADVSYS_1200A ||
218 1.1 dante PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADVSYS_1200B) {
219 1.1 dante bhlcr &= 0xFFFF00FFul;
220 1.1 dante pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, bhlcr);
221 1.1 dante } else if ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADVSYS_ULTRA) &&
222 1.1 dante (PCI_LATTIMER(bhlcr) < 0x20)) {
223 1.1 dante bhlcr &= 0xFFFF00FFul;
224 1.1 dante bhlcr |= 0x00002000ul;
225 1.1 dante pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, bhlcr);
226 1.1 dante }
227 1.1 dante }
228 1.1 dante
229 1.1 dante
230 1.1 dante /*
231 1.1 dante * Map Device Registers for I/O
232 1.1 dante */
233 1.1 dante if (pci_mapreg_map(pa, PCI_BASEADR_IO, PCI_MAPREG_TYPE_IO, 0,
234 1.1 dante &iot, &ioh, NULL, NULL)) {
235 1.1 dante printf("%s: unable to map device registers\n",
236 1.1 dante sc->sc_dev.dv_xname);
237 1.1 dante return;
238 1.1 dante }
239 1.1 dante sc->sc_iot = iot;
240 1.1 dante sc->sc_ioh = ioh;
241 1.1 dante sc->sc_dmat = pa->pa_dmat;
242 1.1 dante sc->pci_device_id = pa->pa_id;
243 1.1 dante sc->bus_type = ASC_IS_PCI;
244 1.1 dante
245 1.1 dante /*
246 1.1 dante * Initialize the board
247 1.1 dante */
248 1.1 dante if (adv_init(sc))
249 1.1 dante panic("adv_pci_attach: adv_init failed");
250 1.1 dante
251 1.1 dante /*
252 1.1 dante * Map Interrupt line
253 1.1 dante */
254 1.1 dante if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin,
255 1.1 dante pa->pa_intrline, &ih)) {
256 1.1 dante printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname);
257 1.1 dante return;
258 1.1 dante }
259 1.1 dante intrstr = pci_intr_string(pc, ih);
260 1.1 dante
261 1.1 dante /*
262 1.1 dante * Establish Interrupt handler
263 1.1 dante */
264 1.1 dante sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, adv_intr, sc);
265 1.1 dante if (sc->sc_ih == NULL) {
266 1.1 dante printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname);
267 1.1 dante if (intrstr != NULL)
268 1.1 dante printf(" at %s", intrstr);
269 1.1 dante printf("\n");
270 1.1 dante return;
271 1.1 dante }
272 1.1 dante printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
273 1.1 dante
274 1.1 dante /*
275 1.1 dante * Attach all the sub-devices we can find
276 1.1 dante */
277 1.1 dante adv_attach(sc);
278 1.1 dante }
279 1.1 dante /******************************************************************************/
280