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adv_pci.c revision 1.9
      1  1.9     lukem /*	$NetBSD: adv_pci.c,v 1.9 2001/11/13 07:48:40 lukem Exp $	*/
      2  1.2     dante 
      3  1.1     dante /*
      4  1.1     dante  * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved.
      5  1.1     dante  *
      6  1.1     dante  * Author: Baldassare Dante Profeta <dante (at) mclink.it>
      7  1.1     dante  *
      8  1.1     dante  * Redistribution and use in source and binary forms, with or without
      9  1.3     dante  * modification, are permitted provided that the following conditions
     10  1.3     dante  * are met:
     11  1.3     dante  * 1. Redistributions of source code must retain the above copyright
     12  1.3     dante  *    notice, this list of conditions and the following disclaimer.
     13  1.3     dante  * 2. Redistributions in binary form must reproduce the above copyright
     14  1.3     dante  *    notice, this list of conditions and the following disclaimer in the
     15  1.3     dante  *    documentation and/or other materials provided with the distribution.
     16  1.3     dante  * 3. All advertising materials mentioning features or use of this software
     17  1.3     dante  *    must display the following acknowledgement:
     18  1.4     dante  *        This product includes software developed by the NetBSD
     19  1.4     dante  *        Foundation, Inc. and its contributors.
     20  1.3     dante  * 4. Neither the name of The NetBSD Foundation nor the names of its
     21  1.3     dante  *    contributors may be used to endorse or promote products derived
     22  1.3     dante  *    from this software without specific prior written permission.
     23  1.4     dante  *
     24  1.1     dante  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     25  1.4     dante  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     26  1.4     dante  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     27  1.4     dante  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     28  1.4     dante  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     29  1.4     dante  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     30  1.4     dante  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     31  1.4     dante  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     32  1.4     dante  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     33  1.4     dante  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     34  1.4     dante  * POSSIBILITY OF SUCH DAMAGE.
     35  1.1     dante  */
     36  1.1     dante /*
     37  1.1     dante  * Device probe and attach routines for the following
     38  1.1     dante  * Advanced Systems Inc. SCSI controllers:
     39  1.1     dante  *
     40  1.1     dante  *    Connectivity Products:
     41  1.1     dante  *      ABP920 - Bus-Master PCI (16 CDB)
     42  1.5     dante  *      ABP930 - Bus-Master PCI (16 CDB)		(Footnote 1)
     43  1.1     dante  *      ABP930U - Bus-Master PCI Ultra (16 CDB)
     44  1.1     dante  *      ABP930UA - Bus-Master PCI Ultra (16 CDB)
     45  1.5     dante  *      ABP960 - Bus-Master PCI MAC/PC (16 CDB)		(Footnote 2)
     46  1.5     dante  *      ABP960U - Bus-Master PCI MAC/PC Ultra (16 CDB)	(Footnote 2)
     47  1.1     dante  *
     48  1.1     dante  *   Single Channel Products:
     49  1.1     dante  *      ABP940 - Bus-Master PCI (240 CDB)
     50  1.1     dante  *      ABP940U - Bus-Master PCI Ultra (240 CDB)
     51  1.1     dante  *      ABP970 - Bus-Master PCI MAC/PC (240 CDB)
     52  1.1     dante  *      ABP970U - Bus-Master PCI MAC/PC Ultra (240 CDB)
     53  1.1     dante  *      ABP940UW - Bus-Master PCI Ultra-Wide (240 CDB)
     54  1.1     dante  *
     55  1.1     dante  *   Multi Channel Products:
     56  1.1     dante  *      ABP950 - Dual Channel Bus-Master PCI (240 CDB Per Channel)
     57  1.1     dante  *      ABP980 - Four Channel Bus-Master PCI (240 CDB Per Channel)
     58  1.1     dante  *      ABP980U - Four Channel Bus-Master PCI Ultra (240 CDB Per Channel)
     59  1.1     dante  *
     60  1.1     dante  *   Footnotes:
     61  1.5     dante  *     1. This board has been sold by SIIG as the Fast SCSI Pro PCI.
     62  1.5     dante  *     2. This board has been sold by Iomega as a Jaz Jet PCI adapter.
     63  1.1     dante  */
     64  1.9     lukem 
     65  1.9     lukem #include <sys/cdefs.h>
     66  1.9     lukem __KERNEL_RCSID(0, "$NetBSD: adv_pci.c,v 1.9 2001/11/13 07:48:40 lukem Exp $");
     67  1.1     dante 
     68  1.1     dante #include <sys/types.h>
     69  1.1     dante #include <sys/param.h>
     70  1.1     dante #include <sys/systm.h>
     71  1.1     dante #include <sys/malloc.h>
     72  1.1     dante #include <sys/kernel.h>
     73  1.1     dante #include <sys/queue.h>
     74  1.1     dante #include <sys/device.h>
     75  1.1     dante 
     76  1.1     dante #include <machine/bus.h>
     77  1.1     dante #include <machine/intr.h>
     78  1.1     dante 
     79  1.1     dante #include <dev/scsipi/scsi_all.h>
     80  1.1     dante #include <dev/scsipi/scsipi_all.h>
     81  1.1     dante #include <dev/scsipi/scsiconf.h>
     82  1.1     dante 
     83  1.1     dante #include <dev/pci/pcireg.h>
     84  1.1     dante #include <dev/pci/pcivar.h>
     85  1.1     dante #include <dev/pci/pcidevs.h>
     86  1.1     dante 
     87  1.6     dante #include <dev/ic/advlib.h>
     88  1.1     dante #include <dev/ic/adv.h>
     89  1.1     dante 
     90  1.1     dante /******************************************************************************/
     91  1.1     dante 
     92  1.1     dante #define PCI_BASEADR_IO        0x10
     93  1.1     dante 
     94  1.1     dante /******************************************************************************/
     95  1.1     dante 
     96  1.4     dante int	adv_pci_match __P((struct device *, struct cfdata *, void *));
     97  1.4     dante void	adv_pci_attach __P((struct device *, struct device *, void *));
     98  1.1     dante 
     99  1.1     dante struct cfattach adv_pci_ca =
    100  1.1     dante {
    101  1.4     dante 	sizeof(ASC_SOFTC), adv_pci_match, adv_pci_attach
    102  1.1     dante };
    103  1.1     dante 
    104  1.1     dante /******************************************************************************/
    105  1.1     dante /*
    106  1.1     dante  * Check the slots looking for a board we recognise
    107  1.1     dante  * If we find one, note it's address (slot) and call
    108  1.1     dante  * the actual probe routine to check it out.
    109  1.1     dante  */
    110  1.1     dante int
    111  1.4     dante adv_pci_match(parent, match, aux)
    112  1.4     dante 	struct device *parent;
    113  1.4     dante 	struct cfdata *match;
    114  1.4     dante 	void *aux;
    115  1.1     dante {
    116  1.1     dante 	struct pci_attach_args *pa = aux;
    117  1.1     dante 
    118  1.1     dante 	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ADVSYS)
    119  1.1     dante 		switch (PCI_PRODUCT(pa->pa_id)) {
    120  1.1     dante 		case PCI_PRODUCT_ADVSYS_1200A:
    121  1.1     dante 		case PCI_PRODUCT_ADVSYS_1200B:
    122  1.1     dante 		case PCI_PRODUCT_ADVSYS_ULTRA:
    123  1.1     dante 			return (1);
    124  1.1     dante 		}
    125  1.1     dante 
    126  1.1     dante 	return 0;
    127  1.1     dante }
    128  1.1     dante 
    129  1.1     dante 
    130  1.1     dante void
    131  1.4     dante adv_pci_attach(parent, self, aux)
    132  1.4     dante 	struct device *parent, *self;
    133  1.4     dante 	void *aux;
    134  1.1     dante {
    135  1.1     dante 	struct pci_attach_args *pa = aux;
    136  1.1     dante 	ASC_SOFTC      *sc = (void *) self;
    137  1.1     dante 	bus_space_tag_t iot;
    138  1.1     dante 	bus_space_handle_t ioh;
    139  1.1     dante 	pci_intr_handle_t ih;
    140  1.1     dante 	pci_chipset_tag_t pc = pa->pa_pc;
    141  1.1     dante 	u_int32_t       command;
    142  1.1     dante 	const char     *intrstr;
    143  1.1     dante 
    144  1.1     dante 
    145  1.1     dante 	sc->sc_flags = 0x0;
    146  1.1     dante 	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ADVSYS)
    147  1.1     dante 		switch (PCI_PRODUCT(pa->pa_id)) {
    148  1.1     dante 		case PCI_PRODUCT_ADVSYS_1200A:
    149  1.4     dante 			printf(": AdvanSys ASC1200A SCSI adapter\n");
    150  1.1     dante 			break;
    151  1.1     dante 
    152  1.1     dante 		case PCI_PRODUCT_ADVSYS_1200B:
    153  1.4     dante 			printf(": AdvanSys ASC1200B SCSI adapter\n");
    154  1.1     dante 			break;
    155  1.1     dante 
    156  1.1     dante 		case PCI_PRODUCT_ADVSYS_ULTRA:
    157  1.1     dante 			switch (PCI_REVISION(pa->pa_class)) {
    158  1.1     dante 			case ASC_PCI_REVISION_3050:
    159  1.4     dante 				printf(": AdvanSys ABP-9xxUA SCSI adapter\n");
    160  1.1     dante 				break;
    161  1.1     dante 
    162  1.1     dante 			case ASC_PCI_REVISION_3150:
    163  1.4     dante 				printf(": AdvanSys ABP-9xxU SCSI adapter\n");
    164  1.1     dante 				break;
    165  1.1     dante 			}
    166  1.1     dante 			break;
    167  1.1     dante 
    168  1.1     dante 		default:
    169  1.1     dante 			printf(": unknown model!\n");
    170  1.1     dante 			return;
    171  1.1     dante 		}
    172  1.1     dante 
    173  1.1     dante 
    174  1.1     dante 	/*
    175  1.1     dante 	 * Make sure IO/MEM/MASTER are enabled
    176  1.1     dante 	 */
    177  1.1     dante 	command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
    178  1.1     dante 	if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
    179  1.1     dante 			PCI_COMMAND_MASTER_ENABLE)) !=
    180  1.1     dante 	    (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
    181  1.1     dante 	     PCI_COMMAND_MASTER_ENABLE)) {
    182  1.1     dante 		pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
    183  1.1     dante 		 command | (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
    184  1.1     dante 			    PCI_COMMAND_MASTER_ENABLE));
    185  1.1     dante 	}
    186  1.1     dante 	/*
    187  1.1     dante 	 * Latency timer settings.
    188  1.1     dante 	 */
    189  1.1     dante 	{
    190  1.1     dante 		u_int32_t       bhlcr;
    191  1.1     dante 
    192  1.1     dante 		bhlcr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
    193  1.1     dante 
    194  1.1     dante 		if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADVSYS_1200A ||
    195  1.1     dante 		    PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADVSYS_1200B) {
    196  1.1     dante 			bhlcr &= 0xFFFF00FFul;
    197  1.4     dante 			pci_conf_write(pa->pa_pc, pa->pa_tag,
    198  1.4     dante 					PCI_BHLC_REG, bhlcr);
    199  1.7     dante 		} else if ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADVSYS_ULTRA)
    200  1.7     dante 			    && (PCI_LATTIMER(bhlcr) < 0x20)) {
    201  1.1     dante 			bhlcr &= 0xFFFF00FFul;
    202  1.1     dante 			bhlcr |= 0x00002000ul;
    203  1.4     dante 			pci_conf_write(pa->pa_pc, pa->pa_tag,
    204  1.4     dante 					PCI_BHLC_REG, bhlcr);
    205  1.1     dante 		}
    206  1.1     dante 	}
    207  1.1     dante 
    208  1.1     dante 
    209  1.1     dante 	/*
    210  1.1     dante 	 * Map Device Registers for I/O
    211  1.1     dante 	 */
    212  1.1     dante 	if (pci_mapreg_map(pa, PCI_BASEADR_IO, PCI_MAPREG_TYPE_IO, 0,
    213  1.1     dante 			&iot, &ioh, NULL, NULL)) {
    214  1.1     dante 		printf("%s: unable to map device registers\n",
    215  1.1     dante 		       sc->sc_dev.dv_xname);
    216  1.1     dante 		return;
    217  1.1     dante 	}
    218  1.7     dante 
    219  1.7     dante 	ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT);
    220  1.7     dante 	ASC_SET_CHIP_STATUS(iot, ioh, 0);
    221  1.7     dante 
    222  1.1     dante 	sc->sc_iot = iot;
    223  1.1     dante 	sc->sc_ioh = ioh;
    224  1.1     dante 	sc->sc_dmat = pa->pa_dmat;
    225  1.1     dante 	sc->pci_device_id = pa->pa_id;
    226  1.1     dante 	sc->bus_type = ASC_IS_PCI;
    227  1.7     dante 	sc->chip_version = ASC_GET_CHIP_VER_NO(iot, ioh);
    228  1.1     dante 
    229  1.1     dante 	/*
    230  1.1     dante 	 * Initialize the board
    231  1.1     dante 	 */
    232  1.1     dante 	if (adv_init(sc))
    233  1.1     dante 		panic("adv_pci_attach: adv_init failed");
    234  1.1     dante 
    235  1.1     dante 	/*
    236  1.1     dante 	 * Map Interrupt line
    237  1.1     dante 	 */
    238  1.8  sommerfe 	if (pci_intr_map(pa, &ih)) {
    239  1.1     dante 		printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname);
    240  1.1     dante 		return;
    241  1.1     dante 	}
    242  1.1     dante 	intrstr = pci_intr_string(pc, ih);
    243  1.1     dante 
    244  1.1     dante 	/*
    245  1.1     dante 	 * Establish Interrupt handler
    246  1.1     dante 	 */
    247  1.1     dante 	sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, adv_intr, sc);
    248  1.1     dante 	if (sc->sc_ih == NULL) {
    249  1.1     dante 		printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname);
    250  1.1     dante 		if (intrstr != NULL)
    251  1.1     dante 			printf(" at %s", intrstr);
    252  1.1     dante 		printf("\n");
    253  1.1     dante 		return;
    254  1.1     dante 	}
    255  1.1     dante 	printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
    256  1.1     dante 
    257  1.1     dante 	/*
    258  1.1     dante 	 * Attach all the sub-devices we can find
    259  1.1     dante 	 */
    260  1.1     dante 	adv_attach(sc);
    261  1.1     dante }
    262  1.1     dante /******************************************************************************/
    263