adw_pci.c revision 1.1 1 1.1 dante /* $NetBSD: adw_pci.c,v 1.1 1998/09/26 16:09:32 dante Exp $ */
2 1.1 dante
3 1.1 dante /*
4 1.1 dante * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved.
5 1.1 dante *
6 1.1 dante * Author: Baldassare Dante Profeta <dante (at) mclink.it>
7 1.1 dante *
8 1.1 dante * Redistribution and use in source and binary forms, with or without
9 1.1 dante * modification, are permitted provided that the following conditions
10 1.1 dante * are met:
11 1.1 dante * 1. Redistributions of source code must retain the above copyright
12 1.1 dante * notice, this list of conditions and the following disclaimer.
13 1.1 dante * 2. Redistributions in binary form must reproduce the above copyright
14 1.1 dante * notice, this list of conditions and the following disclaimer in the
15 1.1 dante * documentation and/or other materials provided with the distribution.
16 1.1 dante * 3. All advertising materials mentioning features or use of this software
17 1.1 dante * must display the following acknowledgement:
18 1.1 dante * This product includes software developed by the NetBSD
19 1.1 dante * Foundation, Inc. and its contributors.
20 1.1 dante * 4. Neither the name of The NetBSD Foundation nor the names of its
21 1.1 dante * contributors may be used to endorse or promote products derived
22 1.1 dante * from this software without specific prior written permission.
23 1.1 dante *
24 1.1 dante * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 1.1 dante * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 1.1 dante * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 1.1 dante * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 1.1 dante * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 1.1 dante * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 1.1 dante * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 1.1 dante * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 1.1 dante * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 1.1 dante * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 1.1 dante * POSSIBILITY OF SUCH DAMAGE.
35 1.1 dante */
36 1.1 dante /*
37 1.1 dante * Device probe and attach routines for the following
38 1.1 dante * Advanced Systems Inc. SCSI controllers:
39 1.1 dante *
40 1.1 dante * Single Channel Products:
41 1.1 dante * ABP940UW - Bus-Master PCI Ultra-Wide (240 CDB)
42 1.1 dante */
43 1.1 dante
44 1.1 dante #include <sys/types.h>
45 1.1 dante #include <sys/param.h>
46 1.1 dante #include <sys/systm.h>
47 1.1 dante #include <sys/malloc.h>
48 1.1 dante #include <sys/kernel.h>
49 1.1 dante #include <sys/queue.h>
50 1.1 dante #include <sys/device.h>
51 1.1 dante
52 1.1 dante #include <machine/bus.h>
53 1.1 dante #include <machine/intr.h>
54 1.1 dante
55 1.1 dante #include <dev/scsipi/scsi_all.h>
56 1.1 dante #include <dev/scsipi/scsipi_all.h>
57 1.1 dante #include <dev/scsipi/scsiconf.h>
58 1.1 dante
59 1.1 dante #include <dev/pci/pcireg.h>
60 1.1 dante #include <dev/pci/pcivar.h>
61 1.1 dante #include <dev/pci/pcidevs.h>
62 1.1 dante
63 1.1 dante #include <dev/ic/adwlib.h>
64 1.1 dante #include <dev/ic/adw.h>
65 1.1 dante
66 1.1 dante /******************************************************************************/
67 1.1 dante
68 1.1 dante #define PCI_BASEADR_IO 0x10
69 1.1 dante
70 1.1 dante /******************************************************************************/
71 1.1 dante
72 1.1 dante int adw_pci_match __P((struct device *, struct cfdata *, void *));
73 1.1 dante void adw_pci_attach __P((struct device *, struct device *, void *));
74 1.1 dante
75 1.1 dante struct cfattach adw_pci_ca =
76 1.1 dante {
77 1.1 dante sizeof(ADW_SOFTC), adw_pci_match, adw_pci_attach
78 1.1 dante };
79 1.1 dante
80 1.1 dante /******************************************************************************/
81 1.1 dante /*
82 1.1 dante * Check the slots looking for a board we recognise
83 1.1 dante * If we find one, note it's address (slot) and call
84 1.1 dante * the actual probe routine to check it out.
85 1.1 dante */
86 1.1 dante int
87 1.1 dante adw_pci_match(parent, match, aux)
88 1.1 dante struct device *parent;
89 1.1 dante struct cfdata *match;
90 1.1 dante void *aux;
91 1.1 dante {
92 1.1 dante struct pci_attach_args *pa = aux;
93 1.1 dante
94 1.1 dante if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ADVSYS)
95 1.1 dante switch (PCI_PRODUCT(pa->pa_id)) {
96 1.1 dante case PCI_PRODUCT_ADVSYS_WIDE:
97 1.1 dante return (1);
98 1.1 dante }
99 1.1 dante
100 1.1 dante return 0;
101 1.1 dante }
102 1.1 dante
103 1.1 dante
104 1.1 dante void
105 1.1 dante adw_pci_attach(parent, self, aux)
106 1.1 dante struct device *parent, *self;
107 1.1 dante void *aux;
108 1.1 dante {
109 1.1 dante struct pci_attach_args *pa = aux;
110 1.1 dante ADW_SOFTC *sc = (void *) self;
111 1.1 dante bus_space_tag_t iot;
112 1.1 dante bus_space_handle_t ioh;
113 1.1 dante pci_intr_handle_t ih;
114 1.1 dante pci_chipset_tag_t pc = pa->pa_pc;
115 1.1 dante u_int32_t command;
116 1.1 dante const char *intrstr;
117 1.1 dante
118 1.1 dante
119 1.1 dante sc->sc_flags = 0x0;
120 1.1 dante if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ADVSYS)
121 1.1 dante switch (PCI_PRODUCT(pa->pa_id)) {
122 1.1 dante case PCI_PRODUCT_ADVSYS_WIDE:
123 1.1 dante sc->sc_flags |= ADW_WIDE_BOARD;
124 1.1 dante printf(": AdvanSys ABP-9xxUW SCSI adapter\n");
125 1.1 dante break;
126 1.1 dante
127 1.1 dante default:
128 1.1 dante printf(": unknown model!\n");
129 1.1 dante return;
130 1.1 dante }
131 1.1 dante
132 1.1 dante
133 1.1 dante /*
134 1.1 dante * Make sure IO/MEM/MASTER are enabled
135 1.1 dante */
136 1.1 dante command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
137 1.1 dante if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
138 1.1 dante PCI_COMMAND_MASTER_ENABLE)) !=
139 1.1 dante (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
140 1.1 dante PCI_COMMAND_MASTER_ENABLE)) {
141 1.1 dante pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
142 1.1 dante command | (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
143 1.1 dante PCI_COMMAND_MASTER_ENABLE));
144 1.1 dante }
145 1.1 dante
146 1.1 dante /*
147 1.1 dante * Latency timer settings.
148 1.1 dante */
149 1.1 dante {
150 1.1 dante u_int32_t bhlcr;
151 1.1 dante
152 1.1 dante bhlcr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
153 1.1 dante
154 1.1 dante if ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADVSYS_WIDE) &&
155 1.1 dante (PCI_LATTIMER(bhlcr) < 0x20)) {
156 1.1 dante bhlcr &= 0xFFFF00FFul;
157 1.1 dante bhlcr |= 0x00002000ul;
158 1.1 dante pci_conf_write(pa->pa_pc, pa->pa_tag,
159 1.1 dante PCI_BHLC_REG, bhlcr);
160 1.1 dante }
161 1.1 dante }
162 1.1 dante
163 1.1 dante
164 1.1 dante if((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADVSYS_WIDE) &&
165 1.1 dante (command & PCI_COMMAND_PARITY_ENABLE) == 0) {
166 1.1 dante sc->cfg.control_flag |= CONTROL_FLAG_IGNORE_PERR;
167 1.1 dante }
168 1.1 dante
169 1.1 dante
170 1.1 dante
171 1.1 dante /*
172 1.1 dante * Map Device Registers for I/O
173 1.1 dante */
174 1.1 dante if (pci_mapreg_map(pa, PCI_BASEADR_IO, PCI_MAPREG_TYPE_IO, 0,
175 1.1 dante &iot, &ioh, NULL, NULL)) {
176 1.1 dante printf("%s: unable to map device registers\n",
177 1.1 dante sc->sc_dev.dv_xname);
178 1.1 dante return;
179 1.1 dante }
180 1.1 dante sc->sc_iot = iot;
181 1.1 dante sc->sc_ioh = ioh;
182 1.1 dante sc->sc_dmat = pa->pa_dmat;
183 1.1 dante
184 1.1 dante /*
185 1.1 dante * Initialize the board
186 1.1 dante */
187 1.1 dante if (adw_init(sc))
188 1.1 dante panic("adw_pci_attach: adw_init failed");
189 1.1 dante
190 1.1 dante /*
191 1.1 dante * Map Interrupt line
192 1.1 dante */
193 1.1 dante if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin,
194 1.1 dante pa->pa_intrline, &ih)) {
195 1.1 dante printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname);
196 1.1 dante return;
197 1.1 dante }
198 1.1 dante intrstr = pci_intr_string(pc, ih);
199 1.1 dante
200 1.1 dante /*
201 1.1 dante * Establish Interrupt handler
202 1.1 dante */
203 1.1 dante sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, adw_intr, sc);
204 1.1 dante if (sc->sc_ih == NULL) {
205 1.1 dante printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname);
206 1.1 dante if (intrstr != NULL)
207 1.1 dante printf(" at %s", intrstr);
208 1.1 dante printf("\n");
209 1.1 dante return;
210 1.1 dante }
211 1.1 dante printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
212 1.1 dante
213 1.1 dante /*
214 1.1 dante * Attach all the sub-devices we can find
215 1.1 dante */
216 1.1 dante adw_attach(sc);
217 1.1 dante }
218 1.1 dante /******************************************************************************/
219