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adw_pci.c revision 1.20
      1  1.20        ad /* $NetBSD: adw_pci.c,v 1.20 2007/10/19 12:00:38 ad Exp $	 */
      2   1.1     dante 
      3   1.1     dante /*
      4   1.3     dante  * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
      5   1.3     dante  * All rights reserved.
      6   1.2     dante  *
      7   1.1     dante  * Author: Baldassare Dante Profeta <dante (at) mclink.it>
      8   1.2     dante  *
      9   1.1     dante  * Redistribution and use in source and binary forms, with or without
     10   1.1     dante  * modification, are permitted provided that the following conditions
     11   1.1     dante  * are met:
     12   1.1     dante  * 1. Redistributions of source code must retain the above copyright
     13   1.1     dante  *    notice, this list of conditions and the following disclaimer.
     14   1.1     dante  * 2. Redistributions in binary form must reproduce the above copyright
     15   1.1     dante  *    notice, this list of conditions and the following disclaimer in the
     16   1.1     dante  *    documentation and/or other materials provided with the distribution.
     17   1.1     dante  * 3. All advertising materials mentioning features or use of this software
     18   1.1     dante  *    must display the following acknowledgement:
     19   1.1     dante  *        This product includes software developed by the NetBSD
     20   1.1     dante  *        Foundation, Inc. and its contributors.
     21   1.1     dante  * 4. Neither the name of The NetBSD Foundation nor the names of its
     22   1.1     dante  *    contributors may be used to endorse or promote products derived
     23   1.1     dante  *    from this software without specific prior written permission.
     24   1.1     dante  *
     25   1.1     dante  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     26   1.1     dante  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     27   1.1     dante  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     28   1.1     dante  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     29   1.1     dante  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     30   1.1     dante  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     31   1.1     dante  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     32   1.1     dante  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     33   1.1     dante  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     34   1.1     dante  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     35   1.1     dante  * POSSIBILITY OF SUCH DAMAGE.
     36   1.1     dante  */
     37   1.1     dante /*
     38   1.1     dante  * Device probe and attach routines for the following
     39   1.1     dante  * Advanced Systems Inc. SCSI controllers:
     40   1.1     dante  *
     41   1.5     dante  *      ABP-940UW	- Bus-Master PCI Ultra-Wide (253 CDB)
     42   1.5     dante  *	ABP-940UW (68)	- Bus-Master PCI Ultra-Wide (253 CDB)
     43   1.5     dante  *	ABP-940UWD	- Bus-Master PCI Ultra-Wide (253 CDB)
     44   1.5     dante  *	ABP-970UW	- Bus-Master PCI Ultra-Wide (253 CDB)
     45   1.5     dante  *	ASB-3940UW	- Bus-Master PCI Ultra-Wide (253 CDB)
     46   1.5     dante  *	ASB-3940U2W-00	- Bus-Master PCI Ultra2-Wide (253 CDB)
     47   1.5     dante  *	ASB-3940U3W-00	- Bus-Master PCI Ultra3-Wide (253 CDB)
     48   1.1     dante  */
     49   1.9     lukem 
     50   1.9     lukem #include <sys/cdefs.h>
     51  1.20        ad __KERNEL_RCSID(0, "$NetBSD: adw_pci.c,v 1.20 2007/10/19 12:00:38 ad Exp $");
     52   1.1     dante 
     53   1.1     dante #include <sys/param.h>
     54   1.1     dante #include <sys/systm.h>
     55   1.1     dante #include <sys/malloc.h>
     56   1.1     dante #include <sys/kernel.h>
     57   1.1     dante #include <sys/queue.h>
     58   1.1     dante #include <sys/device.h>
     59   1.1     dante 
     60  1.20        ad #include <sys/bus.h>
     61  1.20        ad #include <sys/intr.h>
     62   1.1     dante 
     63   1.1     dante #include <dev/scsipi/scsi_all.h>
     64   1.1     dante #include <dev/scsipi/scsipi_all.h>
     65   1.1     dante #include <dev/scsipi/scsiconf.h>
     66   1.1     dante 
     67   1.1     dante #include <dev/pci/pcireg.h>
     68   1.1     dante #include <dev/pci/pcivar.h>
     69   1.1     dante #include <dev/pci/pcidevs.h>
     70   1.1     dante 
     71   1.1     dante #include <dev/ic/adwlib.h>
     72   1.7     dante #include <dev/ic/adwmcode.h>
     73   1.1     dante #include <dev/ic/adw.h>
     74   1.1     dante 
     75   1.1     dante /******************************************************************************/
     76   1.1     dante 
     77   1.1     dante #define PCI_BASEADR_IO        0x10
     78   1.1     dante 
     79   1.1     dante /******************************************************************************/
     80   1.1     dante /*
     81   1.1     dante  * Check the slots looking for a board we recognise
     82   1.1     dante  * If we find one, note it's address (slot) and call
     83   1.1     dante  * the actual probe routine to check it out.
     84   1.1     dante  */
     85   1.6     dante static int
     86  1.19  christos adw_pci_match(struct device *parent, struct cfdata *match,
     87  1.18  christos     void *aux)
     88   1.1     dante {
     89   1.1     dante 	struct pci_attach_args *pa = aux;
     90   1.1     dante 
     91   1.1     dante 	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ADVSYS)
     92   1.1     dante 		switch (PCI_PRODUCT(pa->pa_id)) {
     93   1.1     dante 		case PCI_PRODUCT_ADVSYS_WIDE:
     94   1.3     dante 		case PCI_PRODUCT_ADVSYS_U2W:
     95   1.5     dante 		case PCI_PRODUCT_ADVSYS_U3W:
     96   1.5     dante 			return (1);
     97   1.1     dante 		}
     98   1.1     dante 
     99   1.1     dante 	return 0;
    100   1.1     dante }
    101   1.1     dante 
    102   1.1     dante 
    103   1.6     dante static void
    104  1.19  christos adw_pci_attach(struct device *parent, struct device *self, void *aux)
    105   1.1     dante {
    106   1.1     dante 	struct pci_attach_args *pa = aux;
    107   1.1     dante 	ADW_SOFTC      *sc = (void *) self;
    108   1.1     dante 	bus_space_tag_t iot;
    109   1.1     dante 	bus_space_handle_t ioh;
    110   1.1     dante 	pci_intr_handle_t ih;
    111   1.1     dante 	pci_chipset_tag_t pc = pa->pa_pc;
    112   1.1     dante 	u_int32_t       command;
    113   1.1     dante 	const char     *intrstr;
    114   1.1     dante 
    115  1.14   thorpej 	aprint_naive(": SCSI controller\n");
    116   1.1     dante 
    117   1.1     dante 	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ADVSYS)
    118   1.1     dante 		switch (PCI_PRODUCT(pa->pa_id)) {
    119   1.1     dante 		case PCI_PRODUCT_ADVSYS_WIDE:
    120   1.7     dante 			sc->chip_type = ADW_CHIP_ASC3550;
    121  1.14   thorpej 			aprint_normal(
    122  1.14   thorpej 			    ": AdvanSys ASB-3940UW-00 SCSI adapter\n");
    123   1.3     dante 			break;
    124   1.3     dante 
    125   1.3     dante 		case PCI_PRODUCT_ADVSYS_U2W:
    126   1.7     dante 			sc->chip_type = ADW_CHIP_ASC38C0800;
    127  1.14   thorpej 			aprint_normal(
    128  1.14   thorpej 			    ": AdvanSys ASB-3940U2W-00 SCSI adapter\n");
    129   1.1     dante 			break;
    130   1.1     dante 
    131   1.5     dante 		case PCI_PRODUCT_ADVSYS_U3W:
    132   1.7     dante 			sc->chip_type = ADW_CHIP_ASC38C1600;
    133  1.14   thorpej 			aprint_normal(
    134  1.14   thorpej 			    ": AdvanSys ASB-3940U3W-00 SCSI adapter\n");
    135   1.5     dante 			break;
    136   1.5     dante 
    137   1.1     dante 		default:
    138  1.14   thorpej 			aprint_error(": unknown model!\n");
    139   1.1     dante 			return;
    140   1.1     dante 		}
    141   1.1     dante 
    142   1.1     dante 
    143   1.1     dante 	/*
    144   1.1     dante 	 * Make sure IO/MEM/MASTER are enabled
    145   1.1     dante 	 */
    146   1.1     dante 	command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
    147   1.6     dante 	command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
    148   1.6     dante 			PCI_COMMAND_MASTER_ENABLE;
    149   1.6     dante 	pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command);
    150   1.1     dante 
    151   1.6     dante 	if ( (command & PCI_COMMAND_PARITY_ENABLE) == 0) {
    152   1.1     dante 		sc->cfg.control_flag |= CONTROL_FLAG_IGNORE_PERR;
    153   1.1     dante 	}
    154   1.1     dante 	/*
    155   1.1     dante 	 * Map Device Registers for I/O
    156   1.1     dante 	 */
    157   1.1     dante 	if (pci_mapreg_map(pa, PCI_BASEADR_IO, PCI_MAPREG_TYPE_IO, 0,
    158   1.2     dante 			   &iot, &ioh, NULL, NULL)) {
    159  1.14   thorpej 		aprint_error("%s: unable to map device registers\n",
    160   1.1     dante 		       sc->sc_dev.dv_xname);
    161   1.1     dante 		return;
    162   1.1     dante 	}
    163   1.1     dante 	sc->sc_iot = iot;
    164   1.1     dante 	sc->sc_ioh = ioh;
    165   1.1     dante 	sc->sc_dmat = pa->pa_dmat;
    166   1.1     dante 
    167   1.1     dante 	/*
    168   1.1     dante 	 * Initialize the board
    169   1.1     dante 	 */
    170   1.6     dante 	if (adw_init(sc)) {
    171  1.14   thorpej 		aprint_error("%s: adw_init failed", sc->sc_dev.dv_xname);
    172   1.6     dante 		return;
    173   1.6     dante 	}
    174   1.1     dante 
    175   1.1     dante 	/*
    176   1.1     dante 	 * Map Interrupt line
    177   1.1     dante 	 */
    178   1.8  sommerfe 	if (pci_intr_map(pa, &ih)) {
    179  1.14   thorpej 		aprint_error("%s: couldn't map interrupt\n",
    180  1.14   thorpej 		    sc->sc_dev.dv_xname);
    181   1.1     dante 		return;
    182   1.1     dante 	}
    183   1.1     dante 	intrstr = pci_intr_string(pc, ih);
    184   1.1     dante 
    185   1.1     dante 	/*
    186   1.1     dante 	 * Establish Interrupt handler
    187   1.1     dante 	 */
    188   1.1     dante 	sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, adw_intr, sc);
    189   1.1     dante 	if (sc->sc_ih == NULL) {
    190  1.14   thorpej 		aprint_error("%s: couldn't establish interrupt",
    191  1.14   thorpej 		    sc->sc_dev.dv_xname);
    192   1.1     dante 		if (intrstr != NULL)
    193  1.14   thorpej 			aprint_normal(" at %s", intrstr);
    194  1.14   thorpej 		aprint_normal("\n");
    195   1.1     dante 		return;
    196   1.1     dante 	}
    197  1.14   thorpej 	aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
    198   1.1     dante 
    199   1.1     dante 	/*
    200   1.1     dante 	 * Attach all the sub-devices we can find
    201   1.1     dante 	 */
    202   1.1     dante 	adw_attach(sc);
    203   1.1     dante }
    204  1.16   thorpej 
    205  1.16   thorpej CFATTACH_DECL(adw_pci, sizeof(ADW_SOFTC),
    206  1.16   thorpej     adw_pci_match, adw_pci_attach, NULL, NULL);
    207