adw_pci.c revision 1.25.12.1 1 1.25.12.1 yamt /* $NetBSD: adw_pci.c,v 1.25.12.1 2012/10/30 17:21:22 yamt Exp $ */
2 1.1 dante
3 1.1 dante /*
4 1.3 dante * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
5 1.3 dante * All rights reserved.
6 1.2 dante *
7 1.1 dante * Author: Baldassare Dante Profeta <dante (at) mclink.it>
8 1.2 dante *
9 1.1 dante * Redistribution and use in source and binary forms, with or without
10 1.1 dante * modification, are permitted provided that the following conditions
11 1.1 dante * are met:
12 1.1 dante * 1. Redistributions of source code must retain the above copyright
13 1.1 dante * notice, this list of conditions and the following disclaimer.
14 1.1 dante * 2. Redistributions in binary form must reproduce the above copyright
15 1.1 dante * notice, this list of conditions and the following disclaimer in the
16 1.1 dante * documentation and/or other materials provided with the distribution.
17 1.1 dante *
18 1.1 dante * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
19 1.1 dante * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
20 1.1 dante * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
21 1.1 dante * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
22 1.1 dante * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 1.1 dante * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 1.1 dante * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 1.1 dante * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 1.1 dante * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 1.1 dante * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 1.1 dante * POSSIBILITY OF SUCH DAMAGE.
29 1.1 dante */
30 1.1 dante /*
31 1.1 dante * Device probe and attach routines for the following
32 1.1 dante * Advanced Systems Inc. SCSI controllers:
33 1.1 dante *
34 1.5 dante * ABP-940UW - Bus-Master PCI Ultra-Wide (253 CDB)
35 1.5 dante * ABP-940UW (68) - Bus-Master PCI Ultra-Wide (253 CDB)
36 1.5 dante * ABP-940UWD - Bus-Master PCI Ultra-Wide (253 CDB)
37 1.5 dante * ABP-970UW - Bus-Master PCI Ultra-Wide (253 CDB)
38 1.5 dante * ASB-3940UW - Bus-Master PCI Ultra-Wide (253 CDB)
39 1.5 dante * ASB-3940U2W-00 - Bus-Master PCI Ultra2-Wide (253 CDB)
40 1.5 dante * ASB-3940U3W-00 - Bus-Master PCI Ultra3-Wide (253 CDB)
41 1.1 dante */
42 1.9 lukem
43 1.9 lukem #include <sys/cdefs.h>
44 1.25.12.1 yamt __KERNEL_RCSID(0, "$NetBSD: adw_pci.c,v 1.25.12.1 2012/10/30 17:21:22 yamt Exp $");
45 1.1 dante
46 1.1 dante #include <sys/param.h>
47 1.1 dante #include <sys/systm.h>
48 1.1 dante #include <sys/malloc.h>
49 1.1 dante #include <sys/kernel.h>
50 1.1 dante #include <sys/queue.h>
51 1.1 dante #include <sys/device.h>
52 1.1 dante
53 1.20 ad #include <sys/bus.h>
54 1.20 ad #include <sys/intr.h>
55 1.1 dante
56 1.1 dante #include <dev/scsipi/scsi_all.h>
57 1.1 dante #include <dev/scsipi/scsipi_all.h>
58 1.1 dante #include <dev/scsipi/scsiconf.h>
59 1.1 dante
60 1.1 dante #include <dev/pci/pcireg.h>
61 1.1 dante #include <dev/pci/pcivar.h>
62 1.1 dante #include <dev/pci/pcidevs.h>
63 1.1 dante
64 1.1 dante #include <dev/ic/adwlib.h>
65 1.7 dante #include <dev/ic/adwmcode.h>
66 1.1 dante #include <dev/ic/adw.h>
67 1.1 dante
68 1.1 dante /******************************************************************************/
69 1.1 dante
70 1.1 dante #define PCI_BASEADR_IO 0x10
71 1.1 dante
72 1.1 dante /******************************************************************************/
73 1.1 dante /*
74 1.1 dante * Check the slots looking for a board we recognise
75 1.1 dante * If we find one, note it's address (slot) and call
76 1.1 dante * the actual probe routine to check it out.
77 1.1 dante */
78 1.6 dante static int
79 1.24 cegger adw_pci_match(device_t parent, cfdata_t match, void *aux)
80 1.1 dante {
81 1.1 dante struct pci_attach_args *pa = aux;
82 1.1 dante
83 1.1 dante if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ADVSYS)
84 1.1 dante switch (PCI_PRODUCT(pa->pa_id)) {
85 1.1 dante case PCI_PRODUCT_ADVSYS_WIDE:
86 1.3 dante case PCI_PRODUCT_ADVSYS_U2W:
87 1.5 dante case PCI_PRODUCT_ADVSYS_U3W:
88 1.5 dante return (1);
89 1.1 dante }
90 1.1 dante
91 1.1 dante return 0;
92 1.1 dante }
93 1.1 dante
94 1.1 dante
95 1.6 dante static void
96 1.24 cegger adw_pci_attach(device_t parent, device_t self, void *aux)
97 1.1 dante {
98 1.1 dante struct pci_attach_args *pa = aux;
99 1.25.12.1 yamt ADW_SOFTC *sc = device_private(self);
100 1.1 dante bus_space_tag_t iot;
101 1.1 dante bus_space_handle_t ioh;
102 1.1 dante pci_intr_handle_t ih;
103 1.1 dante pci_chipset_tag_t pc = pa->pa_pc;
104 1.1 dante u_int32_t command;
105 1.1 dante const char *intrstr;
106 1.1 dante
107 1.25.12.1 yamt sc->sc_dev = self;
108 1.25.12.1 yamt
109 1.14 thorpej aprint_naive(": SCSI controller\n");
110 1.1 dante
111 1.1 dante if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ADVSYS)
112 1.1 dante switch (PCI_PRODUCT(pa->pa_id)) {
113 1.1 dante case PCI_PRODUCT_ADVSYS_WIDE:
114 1.7 dante sc->chip_type = ADW_CHIP_ASC3550;
115 1.14 thorpej aprint_normal(
116 1.14 thorpej ": AdvanSys ASB-3940UW-00 SCSI adapter\n");
117 1.3 dante break;
118 1.3 dante
119 1.3 dante case PCI_PRODUCT_ADVSYS_U2W:
120 1.7 dante sc->chip_type = ADW_CHIP_ASC38C0800;
121 1.14 thorpej aprint_normal(
122 1.14 thorpej ": AdvanSys ASB-3940U2W-00 SCSI adapter\n");
123 1.1 dante break;
124 1.1 dante
125 1.5 dante case PCI_PRODUCT_ADVSYS_U3W:
126 1.7 dante sc->chip_type = ADW_CHIP_ASC38C1600;
127 1.14 thorpej aprint_normal(
128 1.14 thorpej ": AdvanSys ASB-3940U3W-00 SCSI adapter\n");
129 1.5 dante break;
130 1.5 dante
131 1.1 dante default:
132 1.14 thorpej aprint_error(": unknown model!\n");
133 1.1 dante return;
134 1.1 dante }
135 1.1 dante
136 1.1 dante
137 1.1 dante /*
138 1.1 dante * Make sure IO/MEM/MASTER are enabled
139 1.1 dante */
140 1.1 dante command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
141 1.6 dante command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
142 1.6 dante PCI_COMMAND_MASTER_ENABLE;
143 1.6 dante pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command);
144 1.1 dante
145 1.6 dante if ( (command & PCI_COMMAND_PARITY_ENABLE) == 0) {
146 1.1 dante sc->cfg.control_flag |= CONTROL_FLAG_IGNORE_PERR;
147 1.1 dante }
148 1.1 dante /*
149 1.1 dante * Map Device Registers for I/O
150 1.1 dante */
151 1.1 dante if (pci_mapreg_map(pa, PCI_BASEADR_IO, PCI_MAPREG_TYPE_IO, 0,
152 1.2 dante &iot, &ioh, NULL, NULL)) {
153 1.25.12.1 yamt aprint_error_dev(self, "unable to map device registers\n");
154 1.1 dante return;
155 1.1 dante }
156 1.1 dante sc->sc_iot = iot;
157 1.1 dante sc->sc_ioh = ioh;
158 1.1 dante sc->sc_dmat = pa->pa_dmat;
159 1.1 dante
160 1.1 dante /*
161 1.1 dante * Initialize the board
162 1.1 dante */
163 1.6 dante if (adw_init(sc)) {
164 1.25.12.1 yamt aprint_error_dev(self, "adw_init failed");
165 1.6 dante return;
166 1.6 dante }
167 1.1 dante
168 1.1 dante /*
169 1.1 dante * Map Interrupt line
170 1.1 dante */
171 1.8 sommerfe if (pci_intr_map(pa, &ih)) {
172 1.25.12.1 yamt aprint_error_dev(self, "couldn't map interrupt\n");
173 1.1 dante return;
174 1.1 dante }
175 1.1 dante intrstr = pci_intr_string(pc, ih);
176 1.1 dante
177 1.1 dante /*
178 1.1 dante * Establish Interrupt handler
179 1.1 dante */
180 1.1 dante sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, adw_intr, sc);
181 1.1 dante if (sc->sc_ih == NULL) {
182 1.25.12.1 yamt aprint_error_dev(self, "couldn't establish interrupt");
183 1.1 dante if (intrstr != NULL)
184 1.25 njoly aprint_error(" at %s", intrstr);
185 1.25 njoly aprint_error("\n");
186 1.1 dante return;
187 1.1 dante }
188 1.25.12.1 yamt aprint_normal_dev(self, "interrupting at %s\n", intrstr);
189 1.1 dante
190 1.1 dante /*
191 1.1 dante * Attach all the sub-devices we can find
192 1.1 dante */
193 1.1 dante adw_attach(sc);
194 1.1 dante }
195 1.16 thorpej
196 1.25.12.1 yamt CFATTACH_DECL_NEW(adw_pci, sizeof(ADW_SOFTC),
197 1.16 thorpej adw_pci_match, adw_pci_attach, NULL, NULL);
198