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adw_pci.c revision 1.5
      1  1.5  dante /* $NetBSD: adw_pci.c,v 1.5 2000/04/30 18:52:14 dante Exp $	 */
      2  1.1  dante 
      3  1.1  dante /*
      4  1.3  dante  * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
      5  1.3  dante  * All rights reserved.
      6  1.2  dante  *
      7  1.1  dante  * Author: Baldassare Dante Profeta <dante (at) mclink.it>
      8  1.2  dante  *
      9  1.1  dante  * Redistribution and use in source and binary forms, with or without
     10  1.1  dante  * modification, are permitted provided that the following conditions
     11  1.1  dante  * are met:
     12  1.1  dante  * 1. Redistributions of source code must retain the above copyright
     13  1.1  dante  *    notice, this list of conditions and the following disclaimer.
     14  1.1  dante  * 2. Redistributions in binary form must reproduce the above copyright
     15  1.1  dante  *    notice, this list of conditions and the following disclaimer in the
     16  1.1  dante  *    documentation and/or other materials provided with the distribution.
     17  1.1  dante  * 3. All advertising materials mentioning features or use of this software
     18  1.1  dante  *    must display the following acknowledgement:
     19  1.1  dante  *        This product includes software developed by the NetBSD
     20  1.1  dante  *        Foundation, Inc. and its contributors.
     21  1.1  dante  * 4. Neither the name of The NetBSD Foundation nor the names of its
     22  1.1  dante  *    contributors may be used to endorse or promote products derived
     23  1.1  dante  *    from this software without specific prior written permission.
     24  1.1  dante  *
     25  1.1  dante  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     26  1.1  dante  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     27  1.1  dante  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     28  1.1  dante  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     29  1.1  dante  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     30  1.1  dante  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     31  1.1  dante  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     32  1.1  dante  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     33  1.1  dante  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     34  1.1  dante  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     35  1.1  dante  * POSSIBILITY OF SUCH DAMAGE.
     36  1.1  dante  */
     37  1.1  dante /*
     38  1.1  dante  * Device probe and attach routines for the following
     39  1.1  dante  * Advanced Systems Inc. SCSI controllers:
     40  1.1  dante  *
     41  1.5  dante  *      ABP-940UW	- Bus-Master PCI Ultra-Wide (253 CDB)
     42  1.5  dante  *	ABP-940UW (68)	- Bus-Master PCI Ultra-Wide (253 CDB)
     43  1.5  dante  *	ABP-940UWD	- Bus-Master PCI Ultra-Wide (253 CDB)
     44  1.5  dante  *	ABP-970UW	- Bus-Master PCI Ultra-Wide (253 CDB)
     45  1.5  dante  *	ASB-3940UW	- Bus-Master PCI Ultra-Wide (253 CDB)
     46  1.5  dante  *	ASB-3940U2W-00	- Bus-Master PCI Ultra2-Wide (253 CDB)
     47  1.5  dante  *	ASB-3940U3W-00	- Bus-Master PCI Ultra3-Wide (253 CDB)
     48  1.1  dante  */
     49  1.1  dante 
     50  1.1  dante #include <sys/types.h>
     51  1.1  dante #include <sys/param.h>
     52  1.1  dante #include <sys/systm.h>
     53  1.1  dante #include <sys/malloc.h>
     54  1.1  dante #include <sys/kernel.h>
     55  1.1  dante #include <sys/queue.h>
     56  1.1  dante #include <sys/device.h>
     57  1.1  dante 
     58  1.1  dante #include <machine/bus.h>
     59  1.1  dante #include <machine/intr.h>
     60  1.1  dante 
     61  1.1  dante #include <dev/scsipi/scsi_all.h>
     62  1.1  dante #include <dev/scsipi/scsipi_all.h>
     63  1.1  dante #include <dev/scsipi/scsiconf.h>
     64  1.1  dante 
     65  1.1  dante #include <dev/pci/pcireg.h>
     66  1.1  dante #include <dev/pci/pcivar.h>
     67  1.1  dante #include <dev/pci/pcidevs.h>
     68  1.1  dante 
     69  1.1  dante #include <dev/ic/adwlib.h>
     70  1.1  dante #include <dev/ic/adw.h>
     71  1.1  dante 
     72  1.1  dante /******************************************************************************/
     73  1.1  dante 
     74  1.1  dante #define PCI_BASEADR_IO        0x10
     75  1.1  dante 
     76  1.1  dante /******************************************************************************/
     77  1.1  dante 
     78  1.2  dante int adw_pci_match __P((struct device *, struct cfdata *, void *));
     79  1.2  dante void adw_pci_attach __P((struct device *, struct device *, void *));
     80  1.1  dante 
     81  1.1  dante struct cfattach adw_pci_ca =
     82  1.1  dante {
     83  1.1  dante 	sizeof(ADW_SOFTC), adw_pci_match, adw_pci_attach
     84  1.1  dante };
     85  1.1  dante 
     86  1.1  dante /******************************************************************************/
     87  1.1  dante /*
     88  1.1  dante  * Check the slots looking for a board we recognise
     89  1.1  dante  * If we find one, note it's address (slot) and call
     90  1.1  dante  * the actual probe routine to check it out.
     91  1.1  dante  */
     92  1.2  dante int
     93  1.1  dante adw_pci_match(parent, match, aux)
     94  1.2  dante 	struct device  *parent;
     95  1.2  dante 	struct cfdata  *match;
     96  1.2  dante 	void           *aux;
     97  1.1  dante {
     98  1.1  dante 	struct pci_attach_args *pa = aux;
     99  1.1  dante 
    100  1.1  dante 	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ADVSYS)
    101  1.1  dante 		switch (PCI_PRODUCT(pa->pa_id)) {
    102  1.1  dante 		case PCI_PRODUCT_ADVSYS_WIDE:
    103  1.1  dante 			return (1);
    104  1.3  dante 		case PCI_PRODUCT_ADVSYS_U2W:
    105  1.3  dante 			return (1);
    106  1.5  dante 		case PCI_PRODUCT_ADVSYS_U3W:
    107  1.5  dante 			return (1);
    108  1.1  dante 		}
    109  1.1  dante 
    110  1.1  dante 	return 0;
    111  1.1  dante }
    112  1.1  dante 
    113  1.1  dante 
    114  1.2  dante void
    115  1.1  dante adw_pci_attach(parent, self, aux)
    116  1.2  dante 	struct device  *parent, *self;
    117  1.2  dante 	void           *aux;
    118  1.1  dante {
    119  1.1  dante 	struct pci_attach_args *pa = aux;
    120  1.1  dante 	ADW_SOFTC      *sc = (void *) self;
    121  1.1  dante 	bus_space_tag_t iot;
    122  1.1  dante 	bus_space_handle_t ioh;
    123  1.1  dante 	pci_intr_handle_t ih;
    124  1.1  dante 	pci_chipset_tag_t pc = pa->pa_pc;
    125  1.1  dante 	u_int32_t       command;
    126  1.1  dante 	const char     *intrstr;
    127  1.1  dante 
    128  1.1  dante 
    129  1.1  dante 	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ADVSYS)
    130  1.1  dante 		switch (PCI_PRODUCT(pa->pa_id)) {
    131  1.1  dante 		case PCI_PRODUCT_ADVSYS_WIDE:
    132  1.3  dante 			sc->chip_type = ADV_CHIP_ASC3550;
    133  1.3  dante 			printf(": AdvanSys ASB-3940UW-00 SCSI adapter\n");
    134  1.3  dante 			break;
    135  1.3  dante 
    136  1.3  dante 		case PCI_PRODUCT_ADVSYS_U2W:
    137  1.3  dante 			sc->chip_type = ADV_CHIP_ASC38C0800;
    138  1.3  dante 			printf(": AdvanSys ASB-3940U2W SCSI adapter\n");
    139  1.1  dante 			break;
    140  1.1  dante 
    141  1.5  dante 		case PCI_PRODUCT_ADVSYS_U3W:
    142  1.5  dante 			sc->chip_type = ADV_CHIP_ASC38C1600;
    143  1.5  dante 			printf(": AdvanSys ASB-3940U3W SCSI adapter\n");
    144  1.5  dante 			break;
    145  1.5  dante 
    146  1.1  dante 		default:
    147  1.1  dante 			printf(": unknown model!\n");
    148  1.1  dante 			return;
    149  1.1  dante 		}
    150  1.1  dante 
    151  1.1  dante 
    152  1.1  dante 	/*
    153  1.1  dante 	 * Make sure IO/MEM/MASTER are enabled
    154  1.1  dante 	 */
    155  1.1  dante 	command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
    156  1.1  dante 	if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
    157  1.1  dante 			PCI_COMMAND_MASTER_ENABLE)) !=
    158  1.1  dante 	    (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
    159  1.1  dante 	     PCI_COMMAND_MASTER_ENABLE)) {
    160  1.1  dante 		pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
    161  1.1  dante 		 command | (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
    162  1.1  dante 			    PCI_COMMAND_MASTER_ENABLE));
    163  1.1  dante 	}
    164  1.1  dante 	/*
    165  1.1  dante 	 * Latency timer settings.
    166  1.1  dante 	 */
    167  1.1  dante 	{
    168  1.1  dante 		u_int32_t       bhlcr;
    169  1.1  dante 
    170  1.1  dante 		bhlcr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
    171  1.1  dante 
    172  1.3  dante 		if( ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADVSYS_WIDE) ||
    173  1.5  dante 		     (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADVSYS_U2W) ||
    174  1.5  dante 		     (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADVSYS_U3W)) &&
    175  1.3  dante 		     (PCI_LATTIMER(bhlcr) < 0x20)) {
    176  1.2  dante 			bhlcr &= 0xFFFF00FFUL;
    177  1.2  dante 			bhlcr |= 0x00002000UL;
    178  1.1  dante 			pci_conf_write(pa->pa_pc, pa->pa_tag,
    179  1.2  dante 				       PCI_BHLC_REG, bhlcr);
    180  1.1  dante 		}
    181  1.1  dante 	}
    182  1.1  dante 
    183  1.1  dante 
    184  1.3  dante 	if (((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADVSYS_WIDE) ||
    185  1.5  dante 	     (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADVSYS_U2W) ||
    186  1.5  dante 	     (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADVSYS_U3W)) &&
    187  1.3  dante 	     (command & PCI_COMMAND_PARITY_ENABLE) == 0) {
    188  1.1  dante 		sc->cfg.control_flag |= CONTROL_FLAG_IGNORE_PERR;
    189  1.1  dante 	}
    190  1.1  dante 	/*
    191  1.1  dante 	 * Map Device Registers for I/O
    192  1.1  dante 	 */
    193  1.1  dante 	if (pci_mapreg_map(pa, PCI_BASEADR_IO, PCI_MAPREG_TYPE_IO, 0,
    194  1.2  dante 			   &iot, &ioh, NULL, NULL)) {
    195  1.1  dante 		printf("%s: unable to map device registers\n",
    196  1.1  dante 		       sc->sc_dev.dv_xname);
    197  1.1  dante 		return;
    198  1.1  dante 	}
    199  1.1  dante 	sc->sc_iot = iot;
    200  1.1  dante 	sc->sc_ioh = ioh;
    201  1.1  dante 	sc->sc_dmat = pa->pa_dmat;
    202  1.1  dante 
    203  1.1  dante 	/*
    204  1.1  dante 	 * Initialize the board
    205  1.1  dante 	 */
    206  1.1  dante 	if (adw_init(sc))
    207  1.1  dante 		panic("adw_pci_attach: adw_init failed");
    208  1.1  dante 
    209  1.1  dante 	/*
    210  1.1  dante 	 * Map Interrupt line
    211  1.1  dante 	 */
    212  1.1  dante 	if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin,
    213  1.1  dante 			 pa->pa_intrline, &ih)) {
    214  1.1  dante 		printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname);
    215  1.1  dante 		return;
    216  1.1  dante 	}
    217  1.1  dante 	intrstr = pci_intr_string(pc, ih);
    218  1.1  dante 
    219  1.1  dante 	/*
    220  1.1  dante 	 * Establish Interrupt handler
    221  1.1  dante 	 */
    222  1.1  dante 	sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, adw_intr, sc);
    223  1.1  dante 	if (sc->sc_ih == NULL) {
    224  1.1  dante 		printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname);
    225  1.1  dante 		if (intrstr != NULL)
    226  1.1  dante 			printf(" at %s", intrstr);
    227  1.1  dante 		printf("\n");
    228  1.1  dante 		return;
    229  1.1  dante 	}
    230  1.1  dante 	printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
    231  1.1  dante 
    232  1.1  dante 	/*
    233  1.1  dante 	 * Attach all the sub-devices we can find
    234  1.1  dante 	 */
    235  1.1  dante 	adw_attach(sc);
    236  1.1  dante }
    237  1.1  dante /******************************************************************************/
    238