adw_pci.c revision 1.8.2.1 1 1.8.2.1 nathanw /* $NetBSD: adw_pci.c,v 1.8.2.1 2001/11/14 19:15:06 nathanw Exp $ */
2 1.1 dante
3 1.1 dante /*
4 1.3 dante * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
5 1.3 dante * All rights reserved.
6 1.2 dante *
7 1.1 dante * Author: Baldassare Dante Profeta <dante (at) mclink.it>
8 1.2 dante *
9 1.1 dante * Redistribution and use in source and binary forms, with or without
10 1.1 dante * modification, are permitted provided that the following conditions
11 1.1 dante * are met:
12 1.1 dante * 1. Redistributions of source code must retain the above copyright
13 1.1 dante * notice, this list of conditions and the following disclaimer.
14 1.1 dante * 2. Redistributions in binary form must reproduce the above copyright
15 1.1 dante * notice, this list of conditions and the following disclaimer in the
16 1.1 dante * documentation and/or other materials provided with the distribution.
17 1.1 dante * 3. All advertising materials mentioning features or use of this software
18 1.1 dante * must display the following acknowledgement:
19 1.1 dante * This product includes software developed by the NetBSD
20 1.1 dante * Foundation, Inc. and its contributors.
21 1.1 dante * 4. Neither the name of The NetBSD Foundation nor the names of its
22 1.1 dante * contributors may be used to endorse or promote products derived
23 1.1 dante * from this software without specific prior written permission.
24 1.1 dante *
25 1.1 dante * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
26 1.1 dante * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 1.1 dante * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 1.1 dante * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
29 1.1 dante * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 1.1 dante * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 1.1 dante * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 1.1 dante * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 1.1 dante * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 1.1 dante * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 1.1 dante * POSSIBILITY OF SUCH DAMAGE.
36 1.1 dante */
37 1.1 dante /*
38 1.1 dante * Device probe and attach routines for the following
39 1.1 dante * Advanced Systems Inc. SCSI controllers:
40 1.1 dante *
41 1.5 dante * ABP-940UW - Bus-Master PCI Ultra-Wide (253 CDB)
42 1.5 dante * ABP-940UW (68) - Bus-Master PCI Ultra-Wide (253 CDB)
43 1.5 dante * ABP-940UWD - Bus-Master PCI Ultra-Wide (253 CDB)
44 1.5 dante * ABP-970UW - Bus-Master PCI Ultra-Wide (253 CDB)
45 1.5 dante * ASB-3940UW - Bus-Master PCI Ultra-Wide (253 CDB)
46 1.5 dante * ASB-3940U2W-00 - Bus-Master PCI Ultra2-Wide (253 CDB)
47 1.5 dante * ASB-3940U3W-00 - Bus-Master PCI Ultra3-Wide (253 CDB)
48 1.1 dante */
49 1.8.2.1 nathanw
50 1.8.2.1 nathanw #include <sys/cdefs.h>
51 1.8.2.1 nathanw __KERNEL_RCSID(0, "$NetBSD: adw_pci.c,v 1.8.2.1 2001/11/14 19:15:06 nathanw Exp $");
52 1.1 dante
53 1.1 dante #include <sys/types.h>
54 1.1 dante #include <sys/param.h>
55 1.1 dante #include <sys/systm.h>
56 1.1 dante #include <sys/malloc.h>
57 1.1 dante #include <sys/kernel.h>
58 1.1 dante #include <sys/queue.h>
59 1.1 dante #include <sys/device.h>
60 1.1 dante
61 1.1 dante #include <machine/bus.h>
62 1.1 dante #include <machine/intr.h>
63 1.1 dante
64 1.1 dante #include <dev/scsipi/scsi_all.h>
65 1.1 dante #include <dev/scsipi/scsipi_all.h>
66 1.1 dante #include <dev/scsipi/scsiconf.h>
67 1.1 dante
68 1.1 dante #include <dev/pci/pcireg.h>
69 1.1 dante #include <dev/pci/pcivar.h>
70 1.1 dante #include <dev/pci/pcidevs.h>
71 1.1 dante
72 1.1 dante #include <dev/ic/adwlib.h>
73 1.7 dante #include <dev/ic/adwmcode.h>
74 1.1 dante #include <dev/ic/adw.h>
75 1.1 dante
76 1.1 dante /******************************************************************************/
77 1.1 dante
78 1.1 dante #define PCI_BASEADR_IO 0x10
79 1.1 dante
80 1.1 dante /******************************************************************************/
81 1.1 dante
82 1.6 dante static int adw_pci_match __P((struct device *, struct cfdata *, void *));
83 1.6 dante static void adw_pci_attach __P((struct device *, struct device *, void *));
84 1.1 dante
85 1.1 dante struct cfattach adw_pci_ca =
86 1.1 dante {
87 1.1 dante sizeof(ADW_SOFTC), adw_pci_match, adw_pci_attach
88 1.1 dante };
89 1.1 dante
90 1.1 dante /******************************************************************************/
91 1.1 dante /*
92 1.1 dante * Check the slots looking for a board we recognise
93 1.1 dante * If we find one, note it's address (slot) and call
94 1.1 dante * the actual probe routine to check it out.
95 1.1 dante */
96 1.6 dante static int
97 1.1 dante adw_pci_match(parent, match, aux)
98 1.2 dante struct device *parent;
99 1.2 dante struct cfdata *match;
100 1.2 dante void *aux;
101 1.1 dante {
102 1.1 dante struct pci_attach_args *pa = aux;
103 1.1 dante
104 1.1 dante if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ADVSYS)
105 1.1 dante switch (PCI_PRODUCT(pa->pa_id)) {
106 1.1 dante case PCI_PRODUCT_ADVSYS_WIDE:
107 1.3 dante case PCI_PRODUCT_ADVSYS_U2W:
108 1.5 dante case PCI_PRODUCT_ADVSYS_U3W:
109 1.5 dante return (1);
110 1.1 dante }
111 1.1 dante
112 1.1 dante return 0;
113 1.1 dante }
114 1.1 dante
115 1.1 dante
116 1.6 dante static void
117 1.1 dante adw_pci_attach(parent, self, aux)
118 1.2 dante struct device *parent, *self;
119 1.2 dante void *aux;
120 1.1 dante {
121 1.1 dante struct pci_attach_args *pa = aux;
122 1.1 dante ADW_SOFTC *sc = (void *) self;
123 1.1 dante bus_space_tag_t iot;
124 1.1 dante bus_space_handle_t ioh;
125 1.1 dante pci_intr_handle_t ih;
126 1.1 dante pci_chipset_tag_t pc = pa->pa_pc;
127 1.1 dante u_int32_t command;
128 1.1 dante const char *intrstr;
129 1.1 dante
130 1.1 dante
131 1.1 dante if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ADVSYS)
132 1.1 dante switch (PCI_PRODUCT(pa->pa_id)) {
133 1.1 dante case PCI_PRODUCT_ADVSYS_WIDE:
134 1.7 dante sc->chip_type = ADW_CHIP_ASC3550;
135 1.3 dante printf(": AdvanSys ASB-3940UW-00 SCSI adapter\n");
136 1.3 dante break;
137 1.3 dante
138 1.3 dante case PCI_PRODUCT_ADVSYS_U2W:
139 1.7 dante sc->chip_type = ADW_CHIP_ASC38C0800;
140 1.6 dante printf(": AdvanSys ASB-3940U2W-00 SCSI adapter\n");
141 1.1 dante break;
142 1.1 dante
143 1.5 dante case PCI_PRODUCT_ADVSYS_U3W:
144 1.7 dante sc->chip_type = ADW_CHIP_ASC38C1600;
145 1.6 dante printf(": AdvanSys ASB-3940U3W-00 SCSI adapter\n");
146 1.5 dante break;
147 1.5 dante
148 1.1 dante default:
149 1.1 dante printf(": unknown model!\n");
150 1.1 dante return;
151 1.1 dante }
152 1.1 dante
153 1.1 dante
154 1.1 dante /*
155 1.1 dante * Make sure IO/MEM/MASTER are enabled
156 1.1 dante */
157 1.1 dante command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
158 1.6 dante command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
159 1.6 dante PCI_COMMAND_MASTER_ENABLE;
160 1.6 dante pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command);
161 1.1 dante
162 1.6 dante if ( (command & PCI_COMMAND_PARITY_ENABLE) == 0) {
163 1.1 dante sc->cfg.control_flag |= CONTROL_FLAG_IGNORE_PERR;
164 1.1 dante }
165 1.1 dante /*
166 1.1 dante * Map Device Registers for I/O
167 1.1 dante */
168 1.1 dante if (pci_mapreg_map(pa, PCI_BASEADR_IO, PCI_MAPREG_TYPE_IO, 0,
169 1.2 dante &iot, &ioh, NULL, NULL)) {
170 1.1 dante printf("%s: unable to map device registers\n",
171 1.1 dante sc->sc_dev.dv_xname);
172 1.1 dante return;
173 1.1 dante }
174 1.1 dante sc->sc_iot = iot;
175 1.1 dante sc->sc_ioh = ioh;
176 1.1 dante sc->sc_dmat = pa->pa_dmat;
177 1.1 dante
178 1.1 dante /*
179 1.1 dante * Initialize the board
180 1.1 dante */
181 1.6 dante if (adw_init(sc)) {
182 1.6 dante printf("%s: adw_init failed", sc->sc_dev.dv_xname);
183 1.6 dante return;
184 1.6 dante }
185 1.1 dante
186 1.1 dante /*
187 1.1 dante * Map Interrupt line
188 1.1 dante */
189 1.8 sommerfe if (pci_intr_map(pa, &ih)) {
190 1.1 dante printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname);
191 1.1 dante return;
192 1.1 dante }
193 1.1 dante intrstr = pci_intr_string(pc, ih);
194 1.1 dante
195 1.1 dante /*
196 1.1 dante * Establish Interrupt handler
197 1.1 dante */
198 1.1 dante sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, adw_intr, sc);
199 1.1 dante if (sc->sc_ih == NULL) {
200 1.1 dante printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname);
201 1.1 dante if (intrstr != NULL)
202 1.1 dante printf(" at %s", intrstr);
203 1.1 dante printf("\n");
204 1.1 dante return;
205 1.1 dante }
206 1.1 dante printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
207 1.1 dante
208 1.1 dante /*
209 1.1 dante * Attach all the sub-devices we can find
210 1.1 dante */
211 1.1 dante adw_attach(sc);
212 1.1 dante }
213 1.1 dante /******************************************************************************/
214