agp_amd64.c revision 1.6 1 /*-
2 * Copyright (c) 2004, 2005 Jung-uk Kim <jkim (at) FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: agp_amd64.c,v 1.6 2010/11/13 13:52:04 uebayasi Exp $");
29
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/malloc.h>
33 #include <sys/kernel.h>
34 #include <sys/proc.h>
35 #include <sys/conf.h>
36 #include <sys/device.h>
37 #include <sys/agpio.h>
38
39 #include <dev/pci/pcivar.h>
40 #include <dev/pci/pcireg.h>
41 #include <dev/pci/agpvar.h>
42 #include <dev/pci/agpreg.h>
43
44 #include <dev/pci/pcidevs.h>
45
46 #include <sys/bus.h>
47
48
49 #define AMD64_MAX_MCTRL 8
50
51 /* XXX nForce3 requires secondary AGP bridge at 0:11:0. */
52 #define AGP_AMD64_NVIDIA_PCITAG(pc) pci_make_tag(pc, 0, 11, 0)
53 /* XXX Some VIA bridge requires secondary AGP bridge at 0:1:0. */
54 #define AGP_AMD64_VIA_PCITAG(pc) pci_make_tag(pc, 0, 1, 0)
55
56
57 static uint32_t agp_amd64_get_aperture(struct agp_softc *);
58 static int agp_amd64_set_aperture(struct agp_softc *, uint32_t);
59 static int agp_amd64_bind_page(struct agp_softc *, off_t, bus_addr_t);
60 static int agp_amd64_unbind_page(struct agp_softc *, off_t);
61 static void agp_amd64_flush_tlb(struct agp_softc *);
62
63 static void agp_amd64_apbase_fixup(struct agp_softc *);
64
65 static void agp_amd64_uli_init(struct agp_softc *);
66 static int agp_amd64_uli_set_aperture(struct agp_softc *, uint32_t);
67
68 static int agp_amd64_nvidia_match(const struct pci_attach_args *, uint16_t);
69 static void agp_amd64_nvidia_init(struct agp_softc *);
70 static int agp_amd64_nvidia_set_aperture(struct agp_softc *, uint32_t);
71
72 static int agp_amd64_via_match(const struct pci_attach_args *);
73 static void agp_amd64_via_init(struct agp_softc *);
74 static int agp_amd64_via_set_aperture(struct agp_softc *, uint32_t);
75
76
77 struct agp_amd64_softc {
78 uint32_t initial_aperture;
79 struct agp_gatt *gatt;
80 uint32_t apbase;
81 pcitag_t ctrl_tag; /* use NVIDIA and VIA */
82 pcitag_t mctrl_tag[AMD64_MAX_MCTRL];
83 int n_mctrl;
84 int via_agp;
85 };
86
87 static struct agp_methods agp_amd64_methods = {
88 agp_amd64_get_aperture,
89 agp_amd64_set_aperture,
90 agp_amd64_bind_page,
91 agp_amd64_unbind_page,
92 agp_amd64_flush_tlb,
93 agp_generic_enable,
94 agp_generic_alloc_memory,
95 agp_generic_free_memory,
96 agp_generic_bind_memory,
97 agp_generic_unbind_memory,
98 };
99
100
101 int
102 agp_amd64_match(const struct pci_attach_args *pa)
103 {
104
105 switch (PCI_VENDOR(pa->pa_id)) {
106 case PCI_VENDOR_AMD:
107 switch (PCI_PRODUCT(pa->pa_id)) {
108 case PCI_PRODUCT_AMD_AGP8151_DEV:
109 return 1;
110 }
111 break;
112
113 case PCI_VENDOR_SIS:
114 switch (PCI_PRODUCT(pa->pa_id)) {
115 case PCI_PRODUCT_SIS_755:
116 case PCI_PRODUCT_SIS_760:
117 return 1;
118 }
119 break;
120
121 case PCI_VENDOR_ALI:
122 switch (PCI_PRODUCT(pa->pa_id)) {
123 case PCI_PRODUCT_ALI_M1689:
124 return 1;
125 }
126 break;
127
128 case PCI_VENDOR_NVIDIA:
129 switch (PCI_PRODUCT(pa->pa_id)) {
130 case PCI_PRODUCT_NVIDIA_NFORCE3_PCHB:
131 return agp_amd64_nvidia_match(pa,
132 PCI_PRODUCT_NVIDIA_NFORCE3_PPB2);
133
134 /* NOTREACHED */
135
136 case PCI_PRODUCT_NVIDIA_NFORCE3_250_PCHB:
137 return agp_amd64_nvidia_match(pa,
138 PCI_PRODUCT_NVIDIA_NFORCE3_250_AGP);
139
140 /* NOTREACHED */
141 }
142 break;
143
144 case PCI_VENDOR_VIATECH:
145 switch (PCI_PRODUCT(pa->pa_id)) {
146 case PCI_PRODUCT_VIATECH_K8M800_0:
147 case PCI_PRODUCT_VIATECH_K8T890_0:
148 case PCI_PRODUCT_VIATECH_K8HTB_0:
149 case PCI_PRODUCT_VIATECH_K8HTB:
150 return 1;
151 }
152 break;
153 }
154
155 return 0;
156 }
157
158 static int
159 agp_amd64_nvidia_match(const struct pci_attach_args *pa, uint16_t devid)
160 {
161 pcitag_t tag;
162 pcireg_t reg;
163
164 tag = AGP_AMD64_NVIDIA_PCITAG(pa->pa_pc);
165
166 reg = pci_conf_read(pa->pa_pc, tag, PCI_CLASS_REG);
167 if (PCI_CLASS(reg) != PCI_CLASS_BRIDGE ||
168 PCI_SUBCLASS(reg) != PCI_SUBCLASS_BRIDGE_PCI)
169 return 0;
170
171 reg = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG);
172 if (PCI_VENDOR(reg) != PCI_VENDOR_NVIDIA || PCI_PRODUCT(reg) != devid)
173 return 0;
174
175 return 1;
176 }
177
178 static int
179 agp_amd64_via_match(const struct pci_attach_args *pa)
180 {
181 pcitag_t tag;
182 pcireg_t reg;
183
184 tag = AGP_AMD64_VIA_PCITAG(pa->pa_pc);
185
186 reg = pci_conf_read(pa->pa_pc, tag, PCI_CLASS_REG);
187 if (PCI_CLASS(reg) != PCI_CLASS_BRIDGE ||
188 PCI_SUBCLASS(reg) != PCI_SUBCLASS_BRIDGE_PCI)
189 return 0;
190
191 reg = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG);
192 if (PCI_VENDOR(reg) != PCI_VENDOR_VIATECH ||
193 PCI_PRODUCT(reg) != PCI_PRODUCT_VIATECH_K8HTB_AGP)
194 return 0;
195
196 return 1;
197 }
198
199 int
200 agp_amd64_attach(device_t parent, device_t self, void *aux)
201 {
202 struct agp_softc *sc = device_private(self);
203 struct agp_amd64_softc *asc;
204 struct pci_attach_args *pa = aux;
205 struct agp_gatt *gatt;
206 pcitag_t tag;
207 pcireg_t id, attbase, apctrl;
208 int maxdevs, i, n;
209
210 asc = malloc(sizeof(struct agp_amd64_softc), M_AGP, M_NOWAIT | M_ZERO);
211 if (asc == NULL) {
212 aprint_error(": can't allocate softc\n");
213 return ENOMEM;
214 }
215
216 if (agp_map_aperture(pa, sc, AGP_APBASE) != 0) {
217 aprint_error(": can't map aperture\n");
218 free(asc, M_AGP);
219 return ENXIO;
220 }
221
222 maxdevs = pci_bus_maxdevs(pa->pa_pc, 0);
223 for (i = 0, n = 0; i < maxdevs && n < AMD64_MAX_MCTRL; i++) {
224 tag = pci_make_tag(pa->pa_pc, 0, i, 3);
225 id = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG);
226 if (PCI_VENDOR(id) == PCI_VENDOR_AMD &&
227 PCI_PRODUCT(id) == PCI_PRODUCT_AMD_AMD64_MISC) {
228 asc->mctrl_tag[n] = tag;
229 n++;
230 }
231 }
232 if (n == 0)
233 return ENXIO;
234 asc->n_mctrl = n;
235
236 aprint_normal(": %d Miscellaneous Control unit(s) found.\n",
237 asc->n_mctrl);
238 aprint_normal("%s", device_xname(self));
239
240 sc->as_chipc = asc;
241 sc->as_methods = &agp_amd64_methods;
242 pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, &sc->as_capoff,
243 NULL);
244 asc->initial_aperture = AGP_GET_APERTURE(sc);
245
246 for (;;) {
247 gatt = agp_alloc_gatt(sc);
248 if (gatt)
249 break;
250
251 /*
252 * Probably contigmalloc failure. Try reducing the
253 * aperture so that the gatt size reduces.
254 */
255 if (AGP_SET_APERTURE(sc, AGP_GET_APERTURE(sc) / 2)) {
256 agp_generic_detach(sc);
257 return ENOMEM;
258 }
259 }
260 asc->gatt = gatt;
261
262 switch (PCI_VENDOR(sc->as_id)) {
263 case PCI_VENDOR_ALI:
264 agp_amd64_uli_init(sc);
265 if (agp_amd64_uli_set_aperture(sc, asc->initial_aperture))
266 return ENXIO;
267 break;
268
269 case PCI_VENDOR_NVIDIA:
270 asc->ctrl_tag = AGP_AMD64_NVIDIA_PCITAG(pa->pa_pc);
271 agp_amd64_nvidia_init(sc);
272 if (agp_amd64_nvidia_set_aperture(sc, asc->initial_aperture))
273 return ENXIO;
274 break;
275
276 case PCI_VENDOR_VIATECH:
277 asc->via_agp = agp_amd64_via_match(pa);
278 if (asc->via_agp) {
279 asc->ctrl_tag = AGP_AMD64_VIA_PCITAG(pa->pa_pc);
280 agp_amd64_via_init(sc);
281 if (agp_amd64_via_set_aperture(sc,
282 asc->initial_aperture))
283 return ENXIO;
284 }
285 break;
286 }
287
288 /* Install the gatt and enable aperture. */
289 attbase = (uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK;
290 for (i = 0; i < asc->n_mctrl; i++) {
291 pci_conf_write(pa->pa_pc, asc->mctrl_tag[i], AGP_AMD64_ATTBASE,
292 attbase);
293 apctrl = pci_conf_read(pa->pa_pc, asc->mctrl_tag[i],
294 AGP_AMD64_APCTRL);
295 apctrl |= AGP_AMD64_APCTRL_GARTEN;
296 apctrl &=
297 ~(AGP_AMD64_APCTRL_DISGARTCPU | AGP_AMD64_APCTRL_DISGARTIO);
298 pci_conf_write(pa->pa_pc, asc->mctrl_tag[i], AGP_AMD64_APCTRL,
299 apctrl);
300 }
301
302 agp_flush_cache();
303
304 return 0;
305 }
306
307
308 static uint32_t agp_amd64_table[] = {
309 0x02000000, /* 32 MB */
310 0x04000000, /* 64 MB */
311 0x08000000, /* 128 MB */
312 0x10000000, /* 256 MB */
313 0x20000000, /* 512 MB */
314 0x40000000, /* 1024 MB */
315 0x80000000, /* 2048 MB */
316 };
317
318 #define AGP_AMD64_TABLE_SIZE \
319 (sizeof(agp_amd64_table) / sizeof(agp_amd64_table[0]))
320
321 static uint32_t
322 agp_amd64_get_aperture(struct agp_softc *sc)
323 {
324 struct agp_amd64_softc *asc = sc->as_chipc;
325 uint32_t i;
326
327 i = (pci_conf_read(sc->as_pc, asc->mctrl_tag[0], AGP_AMD64_APCTRL) &
328 AGP_AMD64_APCTRL_SIZE_MASK) >> 1;
329
330 if (i >= AGP_AMD64_TABLE_SIZE)
331 return 0;
332
333 return agp_amd64_table[i];
334 }
335
336 static int
337 agp_amd64_set_aperture(struct agp_softc *sc, uint32_t aperture)
338 {
339 struct agp_amd64_softc *asc = sc->as_chipc;
340 uint32_t i;
341 pcireg_t apctrl;
342 int j;
343
344 for (i = 0; i < AGP_AMD64_TABLE_SIZE; i++)
345 if (agp_amd64_table[i] == aperture)
346 break;
347 if (i >= AGP_AMD64_TABLE_SIZE)
348 return EINVAL;
349
350 for (j = 0; j < asc->n_mctrl; j++) {
351 apctrl = pci_conf_read(sc->as_pc, asc->mctrl_tag[0],
352 AGP_AMD64_APCTRL);
353 pci_conf_write(sc->as_pc, asc->mctrl_tag[0], AGP_AMD64_APCTRL,
354 (apctrl & ~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1));
355 }
356
357 switch (PCI_VENDOR(sc->as_id)) {
358 case PCI_VENDOR_ALI:
359 return agp_amd64_uli_set_aperture(sc, aperture);
360 break;
361
362 case PCI_VENDOR_NVIDIA:
363 return agp_amd64_nvidia_set_aperture(sc, aperture);
364 break;
365
366 case PCI_VENDOR_VIATECH:
367 if (asc->via_agp)
368 return agp_amd64_via_set_aperture(sc, aperture);
369 break;
370 }
371
372 return 0;
373 }
374
375 static int
376 agp_amd64_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical)
377 {
378 struct agp_amd64_softc *asc = sc->as_chipc;
379
380 if (offset < 0 || offset >= (asc->gatt->ag_entries << AGP_PAGE_SHIFT))
381 return EINVAL;
382
383 asc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] =
384 (physical & 0xfffff000) | ((physical >> 28) & 0x00000ff0) | 3;
385
386 return 0;
387 }
388
389 static int
390 agp_amd64_unbind_page(struct agp_softc *sc, off_t offset)
391 {
392 struct agp_amd64_softc *asc = sc->as_chipc;
393
394 if (offset < 0 || offset >= (asc->gatt->ag_entries << AGP_PAGE_SHIFT))
395 return EINVAL;
396
397 asc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
398
399 return 0;
400 }
401
402 static void
403 agp_amd64_flush_tlb(struct agp_softc *sc)
404 {
405 struct agp_amd64_softc *asc = sc->as_chipc;
406 pcireg_t cachectrl;
407 int i;
408
409 for (i = 0; i < asc->n_mctrl; i++) {
410 cachectrl = pci_conf_read(sc->as_pc, asc->mctrl_tag[i],
411 AGP_AMD64_CACHECTRL);
412 pci_conf_write(sc->as_pc, asc->mctrl_tag[i],
413 AGP_AMD64_CACHECTRL,
414 cachectrl | AGP_AMD64_CACHECTRL_INVGART);
415 }
416 }
417
418 static void
419 agp_amd64_apbase_fixup(struct agp_softc *sc)
420 {
421 struct agp_amd64_softc *asc = sc->as_chipc;
422 uint32_t apbase;
423 int i;
424
425 apbase = pci_conf_read(sc->as_pc, sc->as_tag, AGP_APBASE);
426 asc->apbase = PCI_MAPREG_MEM_ADDR(apbase);
427 apbase = (asc->apbase >> 25) & AGP_AMD64_APBASE_MASK;
428 for (i = 0; i < asc->n_mctrl; i++)
429 pci_conf_write(sc->as_pc, asc->mctrl_tag[i], AGP_AMD64_APBASE,
430 apbase);
431 }
432
433 static void
434 agp_amd64_uli_init(struct agp_softc *sc)
435 {
436 struct agp_amd64_softc *asc = sc->as_chipc;
437 pcireg_t apbase;
438
439 agp_amd64_apbase_fixup(sc);
440 apbase = pci_conf_read(sc->as_pc, sc->as_tag, AGP_AMD64_ULI_APBASE);
441 pci_conf_write(sc->as_pc, sc->as_tag, AGP_AMD64_ULI_APBASE,
442 (apbase & 0x0000000f) | asc->apbase);
443 pci_conf_write(sc->as_pc, sc->as_tag, AGP_AMD64_ULI_HTT_FEATURE,
444 asc->apbase);
445 }
446
447 static int
448 agp_amd64_uli_set_aperture(struct agp_softc *sc, uint32_t aperture)
449 {
450 struct agp_amd64_softc *asc = sc->as_chipc;
451
452 switch (aperture) {
453 case 0x02000000: /* 32 MB */
454 case 0x04000000: /* 64 MB */
455 case 0x08000000: /* 128 MB */
456 case 0x10000000: /* 256 MB */
457 break;
458 default:
459 return EINVAL;
460 }
461
462 pci_conf_write(sc->as_pc, sc->as_tag, AGP_AMD64_ULI_ENU_SCR,
463 asc->apbase + aperture - 1);
464
465 return 0;
466 }
467
468 static void
469 agp_amd64_nvidia_init(struct agp_softc *sc)
470 {
471 struct agp_amd64_softc *asc = sc->as_chipc;
472 pcireg_t apbase;
473
474 agp_amd64_apbase_fixup(sc);
475 apbase =
476 pci_conf_read(sc->as_pc, sc->as_tag, AGP_AMD64_NVIDIA_0_APBASE);
477 pci_conf_write(sc->as_pc, sc->as_tag, AGP_AMD64_NVIDIA_0_APBASE,
478 (apbase & 0x0000000f) | asc->apbase);
479 pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APBASE1,
480 asc->apbase);
481 pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APBASE2,
482 asc->apbase);
483 }
484
485 static int
486 agp_amd64_nvidia_set_aperture(struct agp_softc *sc, uint32_t aperture)
487 {
488 struct agp_amd64_softc *asc = sc->as_chipc;
489 uint32_t apsize;
490
491 switch (aperture) {
492 case 0x02000000: apsize = 0x0f; break; /* 32 MB */
493 case 0x04000000: apsize = 0x0e; break; /* 64 MB */
494 case 0x08000000: apsize = 0x0c; break; /* 128 MB */
495 case 0x10000000: apsize = 0x08; break; /* 256 MB */
496 case 0x20000000: apsize = 0x00; break; /* 512 MB */
497 default:
498 return EINVAL;
499 }
500
501 pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APSIZE,
502 (pci_conf_read(sc->as_pc, asc->ctrl_tag,
503 AGP_AMD64_NVIDIA_1_APSIZE) & 0xfffffff0) | apsize);
504 pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APLIMIT1,
505 asc->apbase + aperture - 1);
506 pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APLIMIT2,
507 asc->apbase + aperture - 1);
508
509 return 0;
510 }
511
512 static void
513 agp_amd64_via_init(struct agp_softc *sc)
514 {
515 struct agp_amd64_softc *asc = sc->as_chipc;
516
517 agp_amd64_apbase_fixup(sc);
518 pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP3_VIA_ATTBASE,
519 asc->gatt->ag_physical);
520 pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP3_VIA_GARTCTRL,
521 pci_conf_read(sc->as_pc, asc->ctrl_tag, AGP3_VIA_ATTBASE) | 0x180);
522 }
523
524 static int
525 agp_amd64_via_set_aperture(struct agp_softc *sc, uint32_t aperture)
526 {
527 struct agp_amd64_softc *asc = sc->as_chipc;
528 uint32_t apsize;
529
530 apsize = ((aperture - 1) >> 20) ^ 0xff;
531 if ((((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1 != aperture)
532 return EINVAL;
533 pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP3_VIA_APSIZE,
534 (pci_conf_read(sc->as_pc, asc->ctrl_tag, AGP3_VIA_APSIZE) & ~0xff) |
535 apsize);
536
537 return 0;
538 }
539