agp_amd64.c revision 1.8
1 /*- 2 * Copyright (c) 2004, 2005 Jung-uk Kim <jkim (at) FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: agp_amd64.c,v 1.8 2015/04/04 15:08:40 riastradh Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/malloc.h> 33 #include <sys/kernel.h> 34 #include <sys/proc.h> 35 #include <sys/conf.h> 36 #include <sys/device.h> 37 #include <sys/agpio.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcireg.h> 41 #include <dev/pci/agpvar.h> 42 #include <dev/pci/agpreg.h> 43 44 #include <dev/pci/pcidevs.h> 45 46 #include <sys/bus.h> 47 48 49 #define AMD64_MAX_MCTRL 8 50 51 /* XXX nForce3 requires secondary AGP bridge at 0:11:0. */ 52 #define AGP_AMD64_NVIDIA_PCITAG(pc) pci_make_tag(pc, 0, 11, 0) 53 /* XXX Some VIA bridge requires secondary AGP bridge at 0:1:0. */ 54 #define AGP_AMD64_VIA_PCITAG(pc) pci_make_tag(pc, 0, 1, 0) 55 56 57 static uint32_t agp_amd64_get_aperture(struct agp_softc *); 58 static int agp_amd64_set_aperture(struct agp_softc *, uint32_t); 59 static int agp_amd64_bind_page(struct agp_softc *, off_t, bus_addr_t); 60 static int agp_amd64_unbind_page(struct agp_softc *, off_t); 61 static void agp_amd64_flush_tlb(struct agp_softc *); 62 63 static void agp_amd64_apbase_fixup(struct agp_softc *); 64 65 static void agp_amd64_uli_init(struct agp_softc *); 66 static int agp_amd64_uli_set_aperture(struct agp_softc *, uint32_t); 67 68 static int agp_amd64_nvidia_match(const struct pci_attach_args *, uint16_t); 69 static void agp_amd64_nvidia_init(struct agp_softc *); 70 static int agp_amd64_nvidia_set_aperture(struct agp_softc *, uint32_t); 71 72 static int agp_amd64_via_match(const struct pci_attach_args *); 73 static void agp_amd64_via_init(struct agp_softc *); 74 static int agp_amd64_via_set_aperture(struct agp_softc *, uint32_t); 75 76 77 struct agp_amd64_softc { 78 uint32_t initial_aperture; 79 struct agp_gatt *gatt; 80 uint32_t apbase; 81 pcitag_t ctrl_tag; /* use NVIDIA and VIA */ 82 pcitag_t mctrl_tag[AMD64_MAX_MCTRL]; 83 int n_mctrl; 84 int via_agp; 85 }; 86 87 static struct agp_methods agp_amd64_methods = { 88 agp_amd64_get_aperture, 89 agp_amd64_set_aperture, 90 agp_amd64_bind_page, 91 agp_amd64_unbind_page, 92 agp_amd64_flush_tlb, 93 agp_generic_enable, 94 agp_generic_alloc_memory, 95 agp_generic_free_memory, 96 agp_generic_bind_memory, 97 agp_generic_unbind_memory, 98 }; 99 100 101 int 102 agp_amd64_match(const struct pci_attach_args *pa) 103 { 104 105 switch (PCI_VENDOR(pa->pa_id)) { 106 case PCI_VENDOR_AMD: 107 switch (PCI_PRODUCT(pa->pa_id)) { 108 case PCI_PRODUCT_AMD_AGP8151_DEV: 109 return 1; 110 } 111 break; 112 113 case PCI_VENDOR_SIS: 114 switch (PCI_PRODUCT(pa->pa_id)) { 115 case PCI_PRODUCT_SIS_755: 116 case PCI_PRODUCT_SIS_760: 117 return 1; 118 } 119 break; 120 121 case PCI_VENDOR_ALI: 122 switch (PCI_PRODUCT(pa->pa_id)) { 123 case PCI_PRODUCT_ALI_M1689: 124 return 1; 125 } 126 break; 127 128 case PCI_VENDOR_NVIDIA: 129 switch (PCI_PRODUCT(pa->pa_id)) { 130 case PCI_PRODUCT_NVIDIA_NFORCE3_PCHB: 131 return agp_amd64_nvidia_match(pa, 132 PCI_PRODUCT_NVIDIA_NFORCE3_PPB2); 133 134 /* NOTREACHED */ 135 136 case PCI_PRODUCT_NVIDIA_NFORCE3_250_PCHB: 137 return agp_amd64_nvidia_match(pa, 138 PCI_PRODUCT_NVIDIA_NFORCE3_250_AGP); 139 140 /* NOTREACHED */ 141 } 142 break; 143 144 case PCI_VENDOR_VIATECH: 145 switch (PCI_PRODUCT(pa->pa_id)) { 146 case PCI_PRODUCT_VIATECH_K8M800_0: 147 case PCI_PRODUCT_VIATECH_K8T890_0: 148 case PCI_PRODUCT_VIATECH_K8HTB_0: 149 case PCI_PRODUCT_VIATECH_K8HTB: 150 return 1; 151 } 152 break; 153 } 154 155 return 0; 156 } 157 158 static int 159 agp_amd64_nvidia_match(const struct pci_attach_args *pa, uint16_t devid) 160 { 161 pcitag_t tag; 162 pcireg_t reg; 163 164 tag = AGP_AMD64_NVIDIA_PCITAG(pa->pa_pc); 165 166 reg = pci_conf_read(pa->pa_pc, tag, PCI_CLASS_REG); 167 if (PCI_CLASS(reg) != PCI_CLASS_BRIDGE || 168 PCI_SUBCLASS(reg) != PCI_SUBCLASS_BRIDGE_PCI) 169 return 0; 170 171 reg = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG); 172 if (PCI_VENDOR(reg) != PCI_VENDOR_NVIDIA || PCI_PRODUCT(reg) != devid) 173 return 0; 174 175 return 1; 176 } 177 178 static int 179 agp_amd64_via_match(const struct pci_attach_args *pa) 180 { 181 pcitag_t tag; 182 pcireg_t reg; 183 184 tag = AGP_AMD64_VIA_PCITAG(pa->pa_pc); 185 186 reg = pci_conf_read(pa->pa_pc, tag, PCI_CLASS_REG); 187 if (PCI_CLASS(reg) != PCI_CLASS_BRIDGE || 188 PCI_SUBCLASS(reg) != PCI_SUBCLASS_BRIDGE_PCI) 189 return 0; 190 191 reg = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG); 192 if (PCI_VENDOR(reg) != PCI_VENDOR_VIATECH || 193 PCI_PRODUCT(reg) != PCI_PRODUCT_VIATECH_K8HTB_AGP) 194 return 0; 195 196 return 1; 197 } 198 199 int 200 agp_amd64_attach(device_t parent, device_t self, void *aux) 201 { 202 struct agp_softc *sc = device_private(self); 203 struct agp_amd64_softc *asc; 204 struct pci_attach_args *pa = aux; 205 struct agp_gatt *gatt; 206 pcitag_t tag; 207 pcireg_t id, attbase, apctrl; 208 int maxdevs, i, n; 209 int error; 210 211 asc = malloc(sizeof(struct agp_amd64_softc), M_AGP, M_NOWAIT | M_ZERO); 212 if (asc == NULL) { 213 aprint_error(": can't allocate softc\n"); 214 error = ENOMEM; 215 goto fail0; 216 } 217 218 if (agp_map_aperture(pa, sc, AGP_APBASE) != 0) { 219 aprint_error(": can't map aperture\n"); 220 error = ENXIO; 221 goto fail1; 222 } 223 224 maxdevs = pci_bus_maxdevs(pa->pa_pc, 0); 225 for (i = 0, n = 0; i < maxdevs && n < AMD64_MAX_MCTRL; i++) { 226 tag = pci_make_tag(pa->pa_pc, 0, i, 3); 227 id = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG); 228 if (PCI_VENDOR(id) == PCI_VENDOR_AMD && 229 (PCI_PRODUCT(id) == PCI_PRODUCT_AMD_AMD64_MISC || 230 PCI_PRODUCT(id) == PCI_PRODUCT_AMD_AMD64_F10_MISC)) { 231 asc->mctrl_tag[n] = tag; 232 n++; 233 } 234 } 235 if (n == 0) { 236 aprint_error(": No Miscellaneous Control unit found.\n"); 237 error = ENXIO; 238 goto fail1; 239 } 240 asc->n_mctrl = n; 241 242 aprint_normal(": %d Miscellaneous Control unit(s) found.\n", 243 asc->n_mctrl); 244 aprint_normal("%s", device_xname(self)); 245 246 sc->as_chipc = asc; 247 sc->as_methods = &agp_amd64_methods; 248 pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, &sc->as_capoff, 249 NULL); 250 asc->initial_aperture = AGP_GET_APERTURE(sc); 251 252 for (;;) { 253 gatt = agp_alloc_gatt(sc); 254 if (gatt) 255 break; 256 257 /* 258 * Probably contigmalloc failure. Try reducing the 259 * aperture so that the gatt size reduces. 260 */ 261 if (AGP_SET_APERTURE(sc, AGP_GET_APERTURE(sc) / 2)) { 262 error = ENOMEM; 263 goto fail1; 264 } 265 } 266 asc->gatt = gatt; 267 268 switch (PCI_VENDOR(sc->as_id)) { 269 case PCI_VENDOR_ALI: 270 agp_amd64_uli_init(sc); 271 if (agp_amd64_uli_set_aperture(sc, asc->initial_aperture)) { 272 /* XXX Back out agp_amd64_uli_init? */ 273 error = ENXIO; 274 goto fail2; 275 } 276 break; 277 278 case PCI_VENDOR_NVIDIA: 279 asc->ctrl_tag = AGP_AMD64_NVIDIA_PCITAG(pa->pa_pc); 280 agp_amd64_nvidia_init(sc); 281 if (agp_amd64_nvidia_set_aperture(sc, asc->initial_aperture)) { 282 /* XXX Back out agp_amd64_nvidia_init? */ 283 error = ENXIO; 284 goto fail2; 285 } 286 break; 287 288 case PCI_VENDOR_VIATECH: 289 asc->via_agp = agp_amd64_via_match(pa); 290 if (asc->via_agp) { 291 asc->ctrl_tag = AGP_AMD64_VIA_PCITAG(pa->pa_pc); 292 agp_amd64_via_init(sc); 293 if (agp_amd64_via_set_aperture(sc, 294 asc->initial_aperture)) { 295 /* XXX Back out agp_amd64_via_init? */ 296 error = ENXIO; 297 goto fail2; 298 } 299 } 300 break; 301 } 302 303 /* Install the gatt and enable aperture. */ 304 attbase = (uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK; 305 for (i = 0; i < asc->n_mctrl; i++) { 306 pci_conf_write(pa->pa_pc, asc->mctrl_tag[i], AGP_AMD64_ATTBASE, 307 attbase); 308 apctrl = pci_conf_read(pa->pa_pc, asc->mctrl_tag[i], 309 AGP_AMD64_APCTRL); 310 apctrl |= AGP_AMD64_APCTRL_GARTEN; 311 apctrl &= 312 ~(AGP_AMD64_APCTRL_DISGARTCPU | AGP_AMD64_APCTRL_DISGARTIO); 313 pci_conf_write(pa->pa_pc, asc->mctrl_tag[i], AGP_AMD64_APCTRL, 314 apctrl); 315 } 316 317 agp_flush_cache(); 318 319 /* Success! */ 320 return 0; 321 322 fail2: agp_free_gatt(sc, gatt); 323 fail1: free(asc, M_AGP); 324 fail0: agp_generic_detach(sc); 325 KASSERT(error); 326 return error; 327 } 328 329 330 static uint32_t agp_amd64_table[] = { 331 0x02000000, /* 32 MB */ 332 0x04000000, /* 64 MB */ 333 0x08000000, /* 128 MB */ 334 0x10000000, /* 256 MB */ 335 0x20000000, /* 512 MB */ 336 0x40000000, /* 1024 MB */ 337 0x80000000, /* 2048 MB */ 338 }; 339 340 #define AGP_AMD64_TABLE_SIZE \ 341 (sizeof(agp_amd64_table) / sizeof(agp_amd64_table[0])) 342 343 static uint32_t 344 agp_amd64_get_aperture(struct agp_softc *sc) 345 { 346 struct agp_amd64_softc *asc = sc->as_chipc; 347 uint32_t i; 348 349 i = (pci_conf_read(sc->as_pc, asc->mctrl_tag[0], AGP_AMD64_APCTRL) & 350 AGP_AMD64_APCTRL_SIZE_MASK) >> 1; 351 352 if (i >= AGP_AMD64_TABLE_SIZE) 353 return 0; 354 355 return agp_amd64_table[i]; 356 } 357 358 static int 359 agp_amd64_set_aperture(struct agp_softc *sc, uint32_t aperture) 360 { 361 struct agp_amd64_softc *asc = sc->as_chipc; 362 uint32_t i; 363 pcireg_t apctrl; 364 int j; 365 366 for (i = 0; i < AGP_AMD64_TABLE_SIZE; i++) 367 if (agp_amd64_table[i] == aperture) 368 break; 369 if (i >= AGP_AMD64_TABLE_SIZE) 370 return EINVAL; 371 372 for (j = 0; j < asc->n_mctrl; j++) { 373 apctrl = pci_conf_read(sc->as_pc, asc->mctrl_tag[0], 374 AGP_AMD64_APCTRL); 375 pci_conf_write(sc->as_pc, asc->mctrl_tag[0], AGP_AMD64_APCTRL, 376 (apctrl & ~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1)); 377 } 378 379 switch (PCI_VENDOR(sc->as_id)) { 380 case PCI_VENDOR_ALI: 381 return agp_amd64_uli_set_aperture(sc, aperture); 382 break; 383 384 case PCI_VENDOR_NVIDIA: 385 return agp_amd64_nvidia_set_aperture(sc, aperture); 386 break; 387 388 case PCI_VENDOR_VIATECH: 389 if (asc->via_agp) 390 return agp_amd64_via_set_aperture(sc, aperture); 391 break; 392 } 393 394 return 0; 395 } 396 397 static int 398 agp_amd64_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 399 { 400 struct agp_amd64_softc *asc = sc->as_chipc; 401 402 if (offset < 0 || offset >= (asc->gatt->ag_entries << AGP_PAGE_SHIFT)) 403 return EINVAL; 404 405 asc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 406 (physical & 0xfffff000) | ((physical >> 28) & 0x00000ff0) | 3; 407 408 return 0; 409 } 410 411 static int 412 agp_amd64_unbind_page(struct agp_softc *sc, off_t offset) 413 { 414 struct agp_amd64_softc *asc = sc->as_chipc; 415 416 if (offset < 0 || offset >= (asc->gatt->ag_entries << AGP_PAGE_SHIFT)) 417 return EINVAL; 418 419 asc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 420 421 return 0; 422 } 423 424 static void 425 agp_amd64_flush_tlb(struct agp_softc *sc) 426 { 427 struct agp_amd64_softc *asc = sc->as_chipc; 428 pcireg_t cachectrl; 429 int i; 430 431 for (i = 0; i < asc->n_mctrl; i++) { 432 cachectrl = pci_conf_read(sc->as_pc, asc->mctrl_tag[i], 433 AGP_AMD64_CACHECTRL); 434 pci_conf_write(sc->as_pc, asc->mctrl_tag[i], 435 AGP_AMD64_CACHECTRL, 436 cachectrl | AGP_AMD64_CACHECTRL_INVGART); 437 } 438 } 439 440 static void 441 agp_amd64_apbase_fixup(struct agp_softc *sc) 442 { 443 struct agp_amd64_softc *asc = sc->as_chipc; 444 uint32_t apbase; 445 int i; 446 447 apbase = pci_conf_read(sc->as_pc, sc->as_tag, AGP_APBASE); 448 asc->apbase = PCI_MAPREG_MEM_ADDR(apbase); 449 apbase = (asc->apbase >> 25) & AGP_AMD64_APBASE_MASK; 450 for (i = 0; i < asc->n_mctrl; i++) 451 pci_conf_write(sc->as_pc, asc->mctrl_tag[i], AGP_AMD64_APBASE, 452 apbase); 453 } 454 455 static void 456 agp_amd64_uli_init(struct agp_softc *sc) 457 { 458 struct agp_amd64_softc *asc = sc->as_chipc; 459 pcireg_t apbase; 460 461 agp_amd64_apbase_fixup(sc); 462 apbase = pci_conf_read(sc->as_pc, sc->as_tag, AGP_AMD64_ULI_APBASE); 463 pci_conf_write(sc->as_pc, sc->as_tag, AGP_AMD64_ULI_APBASE, 464 (apbase & 0x0000000f) | asc->apbase); 465 pci_conf_write(sc->as_pc, sc->as_tag, AGP_AMD64_ULI_HTT_FEATURE, 466 asc->apbase); 467 } 468 469 static int 470 agp_amd64_uli_set_aperture(struct agp_softc *sc, uint32_t aperture) 471 { 472 struct agp_amd64_softc *asc = sc->as_chipc; 473 474 switch (aperture) { 475 case 0x02000000: /* 32 MB */ 476 case 0x04000000: /* 64 MB */ 477 case 0x08000000: /* 128 MB */ 478 case 0x10000000: /* 256 MB */ 479 break; 480 default: 481 return EINVAL; 482 } 483 484 pci_conf_write(sc->as_pc, sc->as_tag, AGP_AMD64_ULI_ENU_SCR, 485 asc->apbase + aperture - 1); 486 487 return 0; 488 } 489 490 static void 491 agp_amd64_nvidia_init(struct agp_softc *sc) 492 { 493 struct agp_amd64_softc *asc = sc->as_chipc; 494 pcireg_t apbase; 495 496 agp_amd64_apbase_fixup(sc); 497 apbase = 498 pci_conf_read(sc->as_pc, sc->as_tag, AGP_AMD64_NVIDIA_0_APBASE); 499 pci_conf_write(sc->as_pc, sc->as_tag, AGP_AMD64_NVIDIA_0_APBASE, 500 (apbase & 0x0000000f) | asc->apbase); 501 pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APBASE1, 502 asc->apbase); 503 pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APBASE2, 504 asc->apbase); 505 } 506 507 static int 508 agp_amd64_nvidia_set_aperture(struct agp_softc *sc, uint32_t aperture) 509 { 510 struct agp_amd64_softc *asc = sc->as_chipc; 511 uint32_t apsize; 512 513 switch (aperture) { 514 case 0x02000000: apsize = 0x0f; break; /* 32 MB */ 515 case 0x04000000: apsize = 0x0e; break; /* 64 MB */ 516 case 0x08000000: apsize = 0x0c; break; /* 128 MB */ 517 case 0x10000000: apsize = 0x08; break; /* 256 MB */ 518 case 0x20000000: apsize = 0x00; break; /* 512 MB */ 519 default: 520 return EINVAL; 521 } 522 523 pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APSIZE, 524 (pci_conf_read(sc->as_pc, asc->ctrl_tag, 525 AGP_AMD64_NVIDIA_1_APSIZE) & 0xfffffff0) | apsize); 526 pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APLIMIT1, 527 asc->apbase + aperture - 1); 528 pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APLIMIT2, 529 asc->apbase + aperture - 1); 530 531 return 0; 532 } 533 534 static void 535 agp_amd64_via_init(struct agp_softc *sc) 536 { 537 struct agp_amd64_softc *asc = sc->as_chipc; 538 539 agp_amd64_apbase_fixup(sc); 540 pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP3_VIA_ATTBASE, 541 asc->gatt->ag_physical); 542 pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP3_VIA_GARTCTRL, 543 pci_conf_read(sc->as_pc, asc->ctrl_tag, AGP3_VIA_ATTBASE) | 0x180); 544 } 545 546 static int 547 agp_amd64_via_set_aperture(struct agp_softc *sc, uint32_t aperture) 548 { 549 struct agp_amd64_softc *asc = sc->as_chipc; 550 uint32_t apsize; 551 552 apsize = ((aperture - 1) >> 20) ^ 0xff; 553 if ((((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1 != aperture) 554 return EINVAL; 555 pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP3_VIA_APSIZE, 556 (pci_conf_read(sc->as_pc, asc->ctrl_tag, AGP3_VIA_APSIZE) & ~0xff) | 557 apsize); 558 559 return 0; 560 } 561
Indexes created Sun Sep 28 16:09:52 GMT 2025