agp_i810.c revision 1.80 1 1.80 riastrad /* $NetBSD: agp_i810.c,v 1.80 2014/05/27 12:51:04 riastradh Exp $ */
2 1.1 fvdl
3 1.1 fvdl /*-
4 1.1 fvdl * Copyright (c) 2000 Doug Rabson
5 1.1 fvdl * Copyright (c) 2000 Ruslan Ermilov
6 1.1 fvdl * All rights reserved.
7 1.1 fvdl *
8 1.1 fvdl * Redistribution and use in source and binary forms, with or without
9 1.1 fvdl * modification, are permitted provided that the following conditions
10 1.1 fvdl * are met:
11 1.1 fvdl * 1. Redistributions of source code must retain the above copyright
12 1.1 fvdl * notice, this list of conditions and the following disclaimer.
13 1.1 fvdl * 2. Redistributions in binary form must reproduce the above copyright
14 1.1 fvdl * notice, this list of conditions and the following disclaimer in the
15 1.1 fvdl * documentation and/or other materials provided with the distribution.
16 1.1 fvdl *
17 1.1 fvdl * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 1.1 fvdl * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 1.1 fvdl * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 1.1 fvdl * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 1.1 fvdl * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 1.1 fvdl * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 1.1 fvdl * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 1.1 fvdl * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 1.1 fvdl * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 1.1 fvdl * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 1.1 fvdl * SUCH DAMAGE.
28 1.1 fvdl *
29 1.74 riastrad * $FreeBSD$
30 1.1 fvdl */
31 1.9 lukem
32 1.9 lukem #include <sys/cdefs.h>
33 1.80 riastrad __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.80 2014/05/27 12:51:04 riastradh Exp $");
34 1.1 fvdl
35 1.1 fvdl #include <sys/param.h>
36 1.1 fvdl #include <sys/systm.h>
37 1.1 fvdl #include <sys/malloc.h>
38 1.1 fvdl #include <sys/kernel.h>
39 1.1 fvdl #include <sys/proc.h>
40 1.1 fvdl #include <sys/device.h>
41 1.1 fvdl #include <sys/conf.h>
42 1.75 riastrad #include <sys/xcall.h>
43 1.1 fvdl
44 1.1 fvdl #include <dev/pci/pcivar.h>
45 1.1 fvdl #include <dev/pci/pcireg.h>
46 1.1 fvdl #include <dev/pci/pcidevs.h>
47 1.1 fvdl #include <dev/pci/agpvar.h>
48 1.1 fvdl #include <dev/pci/agpreg.h>
49 1.74 riastrad #include <dev/pci/agp_i810var.h>
50 1.1 fvdl
51 1.1 fvdl #include <sys/agpio.h>
52 1.1 fvdl
53 1.43 ad #include <sys/bus.h>
54 1.1 fvdl
55 1.20 tron #include "agp_intel.h"
56 1.20 tron
57 1.74 riastrad struct agp_softc *agp_i810_sc = NULL;
58 1.74 riastrad
59 1.1 fvdl #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off)
60 1.14 scw #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off)
61 1.1 fvdl #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v)
62 1.1 fvdl
63 1.14 scw #define CHIP_I810 0 /* i810/i815 */
64 1.17 hannken #define CHIP_I830 1 /* 830M/845G */
65 1.17 hannken #define CHIP_I855 2 /* 852GM/855GM/865G */
66 1.56 tnn #define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */
67 1.45 joerg #define CHIP_I965 4 /* 965Q/965PM */
68 1.45 joerg #define CHIP_G33 5 /* G33/Q33/Q35 */
69 1.58 christos #define CHIP_G4X 6 /* G45/Q45 */
70 1.14 scw
71 1.49 drochner /* XXX hack, see below */
72 1.50 drochner static bus_addr_t agp_i810_vga_regbase;
73 1.50 drochner static bus_space_handle_t agp_i810_vga_bsh;
74 1.49 drochner
75 1.1 fvdl static u_int32_t agp_i810_get_aperture(struct agp_softc *);
76 1.1 fvdl static int agp_i810_set_aperture(struct agp_softc *, u_int32_t);
77 1.1 fvdl static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t);
78 1.1 fvdl static int agp_i810_unbind_page(struct agp_softc *, off_t);
79 1.1 fvdl static void agp_i810_flush_tlb(struct agp_softc *);
80 1.1 fvdl static int agp_i810_enable(struct agp_softc *, u_int32_t mode);
81 1.1 fvdl static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int,
82 1.1 fvdl vsize_t);
83 1.1 fvdl static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *);
84 1.1 fvdl static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, off_t);
85 1.1 fvdl static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *);
86 1.47 jmcneill
87 1.66 dyoung static bool agp_i810_resume(device_t, const pmf_qual_t *);
88 1.47 jmcneill static int agp_i810_init(struct agp_softc *);
89 1.1 fvdl
90 1.75 riastrad static int agp_i810_setup_chipset_flush_page(struct agp_softc *);
91 1.79 riastrad static void agp_i810_teardown_chipset_flush_page(struct agp_softc *);
92 1.45 joerg static int agp_i810_init(struct agp_softc *);
93 1.45 joerg
94 1.26 thorpej static struct agp_methods agp_i810_methods = {
95 1.1 fvdl agp_i810_get_aperture,
96 1.1 fvdl agp_i810_set_aperture,
97 1.1 fvdl agp_i810_bind_page,
98 1.1 fvdl agp_i810_unbind_page,
99 1.1 fvdl agp_i810_flush_tlb,
100 1.1 fvdl agp_i810_enable,
101 1.1 fvdl agp_i810_alloc_memory,
102 1.1 fvdl agp_i810_free_memory,
103 1.1 fvdl agp_i810_bind_memory,
104 1.1 fvdl agp_i810_unbind_memory,
105 1.1 fvdl };
106 1.1 fvdl
107 1.74 riastrad int
108 1.71 gsutre agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, bus_addr_t v)
109 1.58 christos {
110 1.71 gsutre u_int32_t pte;
111 1.71 gsutre
112 1.71 gsutre /* Bits 11:4 (physical start address extension) should be zero. */
113 1.71 gsutre if ((v & 0xff0) != 0)
114 1.71 gsutre return EINVAL;
115 1.71 gsutre
116 1.71 gsutre pte = (u_int32_t)v;
117 1.71 gsutre /*
118 1.71 gsutre * We need to massage the pte if bus_addr_t is wider than 32 bits.
119 1.71 gsutre * The compiler isn't smart enough, hence the casts to uintmax_t.
120 1.71 gsutre */
121 1.71 gsutre if (sizeof(bus_addr_t) > sizeof(u_int32_t)) {
122 1.71 gsutre /* 965+ can do 36-bit addressing, add in the extra bits. */
123 1.71 gsutre if (isc->chiptype == CHIP_I965 ||
124 1.71 gsutre isc->chiptype == CHIP_G33 ||
125 1.71 gsutre isc->chiptype == CHIP_G4X) {
126 1.71 gsutre if (((uintmax_t)v >> 36) != 0)
127 1.71 gsutre return EINVAL;
128 1.71 gsutre pte |= (v >> 28) & 0xf0;
129 1.71 gsutre } else {
130 1.71 gsutre if (((uintmax_t)v >> 32) != 0)
131 1.71 gsutre return EINVAL;
132 1.71 gsutre }
133 1.71 gsutre }
134 1.58 christos
135 1.79 riastrad bus_space_write_4(isc->gtt_bst, isc->gtt_bsh,
136 1.79 riastrad 4*(off >> AGP_PAGE_SHIFT), pte);
137 1.58 christos
138 1.71 gsutre return 0;
139 1.58 christos }
140 1.58 christos
141 1.74 riastrad void
142 1.74 riastrad agp_i810_post_gtt_entry(struct agp_i810_softc *isc, off_t off)
143 1.74 riastrad {
144 1.74 riastrad
145 1.79 riastrad (void)bus_space_read_4(isc->gtt_bst, isc->gtt_bsh,
146 1.79 riastrad 4*(off >> AGP_PAGE_SHIFT));
147 1.74 riastrad }
148 1.74 riastrad
149 1.75 riastrad static void
150 1.75 riastrad agp_flush_cache_xc(void *a __unused, void *b __unused)
151 1.75 riastrad {
152 1.75 riastrad
153 1.75 riastrad agp_flush_cache();
154 1.75 riastrad }
155 1.75 riastrad
156 1.75 riastrad void
157 1.75 riastrad agp_i810_chipset_flush(struct agp_i810_softc *isc)
158 1.75 riastrad {
159 1.75 riastrad unsigned int timo = 20000; /* * 50 us = 1 s */
160 1.75 riastrad
161 1.75 riastrad switch (isc->chiptype) {
162 1.75 riastrad case CHIP_I810:
163 1.75 riastrad break;
164 1.75 riastrad case CHIP_I830:
165 1.75 riastrad case CHIP_I855:
166 1.77 riastrad /*
167 1.77 riastrad * Flush all CPU caches. If we're cold, we can't run
168 1.77 riastrad * xcalls, but there should be only one CPU up, so
169 1.77 riastrad * flushing only the local CPU's cache should suffice.
170 1.77 riastrad *
171 1.77 riastrad * XXX Come to think of it, do these chipsets appear in
172 1.77 riastrad * any multi-CPU systems?
173 1.77 riastrad */
174 1.77 riastrad if (cold)
175 1.77 riastrad agp_flush_cache();
176 1.77 riastrad else
177 1.77 riastrad xc_wait(xc_broadcast(0, &agp_flush_cache_xc,
178 1.77 riastrad NULL, NULL));
179 1.75 riastrad WRITE4(AGP_I830_HIC, READ4(AGP_I830_HIC) | __BIT(31));
180 1.75 riastrad while (ISSET(READ4(AGP_I830_HIC), __BIT(31))) {
181 1.75 riastrad if (timo-- == 0)
182 1.75 riastrad break;
183 1.75 riastrad DELAY(50);
184 1.75 riastrad }
185 1.75 riastrad break;
186 1.75 riastrad case CHIP_I915:
187 1.75 riastrad case CHIP_I965:
188 1.75 riastrad case CHIP_G33:
189 1.75 riastrad case CHIP_G4X:
190 1.75 riastrad bus_space_write_4(isc->flush_bst, isc->flush_bsh, 0, 1);
191 1.75 riastrad break;
192 1.75 riastrad }
193 1.75 riastrad }
194 1.75 riastrad
195 1.55 matthias /* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */
196 1.1 fvdl static int
197 1.73 dyoung agp_i810_vgamatch(const struct pci_attach_args *pa)
198 1.1 fvdl {
199 1.6 thorpej
200 1.2 fvdl if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY ||
201 1.2 fvdl PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA)
202 1.6 thorpej return (0);
203 1.6 thorpej
204 1.1 fvdl switch (PCI_PRODUCT(pa->pa_id)) {
205 1.1 fvdl case PCI_PRODUCT_INTEL_82810_GC:
206 1.1 fvdl case PCI_PRODUCT_INTEL_82810_DC100_GC:
207 1.1 fvdl case PCI_PRODUCT_INTEL_82810E_GC:
208 1.1 fvdl case PCI_PRODUCT_INTEL_82815_FULL_GRAPH:
209 1.14 scw case PCI_PRODUCT_INTEL_82830MP_IV:
210 1.14 scw case PCI_PRODUCT_INTEL_82845G_IGD:
211 1.17 hannken case PCI_PRODUCT_INTEL_82855GM_IGD:
212 1.18 tron case PCI_PRODUCT_INTEL_82865_IGD:
213 1.28 christos case PCI_PRODUCT_INTEL_82915G_IGD:
214 1.28 christos case PCI_PRODUCT_INTEL_82915GM_IGD:
215 1.32 simonb case PCI_PRODUCT_INTEL_82945P_IGD:
216 1.32 simonb case PCI_PRODUCT_INTEL_82945GM_IGD:
217 1.32 simonb case PCI_PRODUCT_INTEL_82945GM_IGD_1:
218 1.56 tnn case PCI_PRODUCT_INTEL_82945GME_IGD:
219 1.68 riz case PCI_PRODUCT_INTEL_E7221_IGD:
220 1.42 markd case PCI_PRODUCT_INTEL_82965Q_IGD:
221 1.42 markd case PCI_PRODUCT_INTEL_82965Q_IGD_1:
222 1.45 joerg case PCI_PRODUCT_INTEL_82965PM_IGD:
223 1.45 joerg case PCI_PRODUCT_INTEL_82965PM_IGD_1:
224 1.45 joerg case PCI_PRODUCT_INTEL_82G33_IGD:
225 1.45 joerg case PCI_PRODUCT_INTEL_82G33_IGD_1:
226 1.44 jnemeth case PCI_PRODUCT_INTEL_82965G_IGD:
227 1.44 jnemeth case PCI_PRODUCT_INTEL_82965G_IGD_1:
228 1.68 riz case PCI_PRODUCT_INTEL_82965GME_IGD:
229 1.46 markd case PCI_PRODUCT_INTEL_82Q35_IGD:
230 1.46 markd case PCI_PRODUCT_INTEL_82Q35_IGD_1:
231 1.46 markd case PCI_PRODUCT_INTEL_82Q33_IGD:
232 1.46 markd case PCI_PRODUCT_INTEL_82Q33_IGD_1:
233 1.57 christos case PCI_PRODUCT_INTEL_82G35_IGD:
234 1.57 christos case PCI_PRODUCT_INTEL_82G35_IGD_1:
235 1.55 matthias case PCI_PRODUCT_INTEL_82946GZ_IGD:
236 1.58 christos case PCI_PRODUCT_INTEL_82GM45_IGD:
237 1.58 christos case PCI_PRODUCT_INTEL_82GM45_IGD_1:
238 1.62 markd case PCI_PRODUCT_INTEL_82IGD_E_IGD:
239 1.62 markd case PCI_PRODUCT_INTEL_82Q45_IGD:
240 1.62 markd case PCI_PRODUCT_INTEL_82G45_IGD:
241 1.68 riz case PCI_PRODUCT_INTEL_82G41_IGD:
242 1.68 riz case PCI_PRODUCT_INTEL_82B43_IGD:
243 1.68 riz case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD:
244 1.68 riz case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD:
245 1.72 matt case PCI_PRODUCT_INTEL_PINEVIEW_IGD:
246 1.72 matt case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD:
247 1.6 thorpej return (1);
248 1.1 fvdl }
249 1.1 fvdl
250 1.6 thorpej return (0);
251 1.1 fvdl }
252 1.1 fvdl
253 1.42 markd static int
254 1.42 markd agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg)
255 1.42 markd {
256 1.42 markd /*
257 1.42 markd * Find the aperture. Don't map it (yet), this would
258 1.42 markd * eat KVA.
259 1.42 markd */
260 1.42 markd if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg,
261 1.42 markd PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize,
262 1.42 markd &sc->as_apflags) != 0)
263 1.42 markd return ENXIO;
264 1.42 markd
265 1.42 markd sc->as_apt = pa->pa_memt;
266 1.42 markd
267 1.42 markd return 0;
268 1.42 markd }
269 1.42 markd
270 1.1 fvdl int
271 1.54 freza agp_i810_attach(device_t parent, device_t self, void *aux)
272 1.1 fvdl {
273 1.54 freza struct agp_softc *sc = device_private(self);
274 1.1 fvdl struct agp_i810_softc *isc;
275 1.1 fvdl struct agp_gatt *gatt;
276 1.79 riastrad int apbase, mmadr_bar, gtt_bar;
277 1.79 riastrad int mmadr_type, mmadr_flags;
278 1.79 riastrad bus_addr_t mmadr, gtt_off;
279 1.79 riastrad bus_size_t mmadr_size;
280 1.79 riastrad int error;
281 1.1 fvdl
282 1.10 tsutsui isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO);
283 1.1 fvdl if (isc == NULL) {
284 1.15 thorpej aprint_error(": can't allocate chipset-specific softc\n");
285 1.79 riastrad error = ENOMEM;
286 1.79 riastrad goto fail0;
287 1.1 fvdl }
288 1.1 fvdl sc->as_chipc = isc;
289 1.1 fvdl sc->as_methods = &agp_i810_methods;
290 1.1 fvdl
291 1.1 fvdl if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) {
292 1.20 tron #if NAGP_INTEL > 0
293 1.19 tron const struct pci_attach_args *pa = aux;
294 1.19 tron
295 1.19 tron switch (PCI_PRODUCT(pa->pa_id)) {
296 1.19 tron case PCI_PRODUCT_INTEL_82840_HB:
297 1.19 tron case PCI_PRODUCT_INTEL_82865_HB:
298 1.21 tron case PCI_PRODUCT_INTEL_82845G_DRAM:
299 1.23 xtraeme case PCI_PRODUCT_INTEL_82815_FULL_HUB:
300 1.67 jakllsch case PCI_PRODUCT_INTEL_82855GM_MCH:
301 1.79 riastrad free(isc, M_AGP);
302 1.19 tron return agp_intel_attach(parent, self, aux);
303 1.20 tron }
304 1.20 tron #endif
305 1.15 thorpej aprint_error(": can't find internal VGA device config space\n");
306 1.79 riastrad error = ENOENT;
307 1.79 riastrad goto fail1;
308 1.1 fvdl }
309 1.1 fvdl
310 1.1 fvdl /* XXXfvdl */
311 1.1 fvdl sc->as_dmat = isc->vga_pa.pa_dmat;
312 1.1 fvdl
313 1.14 scw switch (PCI_PRODUCT(isc->vga_pa.pa_id)) {
314 1.14 scw case PCI_PRODUCT_INTEL_82810_GC:
315 1.14 scw case PCI_PRODUCT_INTEL_82810_DC100_GC:
316 1.14 scw case PCI_PRODUCT_INTEL_82810E_GC:
317 1.14 scw case PCI_PRODUCT_INTEL_82815_FULL_GRAPH:
318 1.14 scw isc->chiptype = CHIP_I810;
319 1.14 scw break;
320 1.14 scw case PCI_PRODUCT_INTEL_82830MP_IV:
321 1.14 scw case PCI_PRODUCT_INTEL_82845G_IGD:
322 1.14 scw isc->chiptype = CHIP_I830;
323 1.14 scw break;
324 1.17 hannken case PCI_PRODUCT_INTEL_82855GM_IGD:
325 1.18 tron case PCI_PRODUCT_INTEL_82865_IGD:
326 1.17 hannken isc->chiptype = CHIP_I855;
327 1.17 hannken break;
328 1.28 christos case PCI_PRODUCT_INTEL_82915G_IGD:
329 1.28 christos case PCI_PRODUCT_INTEL_82915GM_IGD:
330 1.32 simonb case PCI_PRODUCT_INTEL_82945P_IGD:
331 1.32 simonb case PCI_PRODUCT_INTEL_82945GM_IGD:
332 1.32 simonb case PCI_PRODUCT_INTEL_82945GM_IGD_1:
333 1.56 tnn case PCI_PRODUCT_INTEL_82945GME_IGD:
334 1.68 riz case PCI_PRODUCT_INTEL_E7221_IGD:
335 1.72 matt case PCI_PRODUCT_INTEL_PINEVIEW_IGD:
336 1.72 matt case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD:
337 1.28 christos isc->chiptype = CHIP_I915;
338 1.28 christos break;
339 1.42 markd case PCI_PRODUCT_INTEL_82965Q_IGD:
340 1.42 markd case PCI_PRODUCT_INTEL_82965Q_IGD_1:
341 1.45 joerg case PCI_PRODUCT_INTEL_82965PM_IGD:
342 1.45 joerg case PCI_PRODUCT_INTEL_82965PM_IGD_1:
343 1.44 jnemeth case PCI_PRODUCT_INTEL_82965G_IGD:
344 1.44 jnemeth case PCI_PRODUCT_INTEL_82965G_IGD_1:
345 1.68 riz case PCI_PRODUCT_INTEL_82965GME_IGD:
346 1.55 matthias case PCI_PRODUCT_INTEL_82946GZ_IGD:
347 1.57 christos case PCI_PRODUCT_INTEL_82G35_IGD:
348 1.57 christos case PCI_PRODUCT_INTEL_82G35_IGD_1:
349 1.42 markd isc->chiptype = CHIP_I965;
350 1.42 markd break;
351 1.46 markd case PCI_PRODUCT_INTEL_82Q35_IGD:
352 1.46 markd case PCI_PRODUCT_INTEL_82Q35_IGD_1:
353 1.45 joerg case PCI_PRODUCT_INTEL_82G33_IGD:
354 1.45 joerg case PCI_PRODUCT_INTEL_82G33_IGD_1:
355 1.46 markd case PCI_PRODUCT_INTEL_82Q33_IGD:
356 1.46 markd case PCI_PRODUCT_INTEL_82Q33_IGD_1:
357 1.45 joerg isc->chiptype = CHIP_G33;
358 1.63 markd break;
359 1.58 christos case PCI_PRODUCT_INTEL_82GM45_IGD:
360 1.58 christos case PCI_PRODUCT_INTEL_82GM45_IGD_1:
361 1.62 markd case PCI_PRODUCT_INTEL_82IGD_E_IGD:
362 1.62 markd case PCI_PRODUCT_INTEL_82Q45_IGD:
363 1.62 markd case PCI_PRODUCT_INTEL_82G45_IGD:
364 1.68 riz case PCI_PRODUCT_INTEL_82G41_IGD:
365 1.68 riz case PCI_PRODUCT_INTEL_82B43_IGD:
366 1.68 riz case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD:
367 1.68 riz case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD:
368 1.58 christos isc->chiptype = CHIP_G4X;
369 1.45 joerg break;
370 1.14 scw }
371 1.14 scw
372 1.79 riastrad mmadr_type = PCI_MAPREG_TYPE_MEM;
373 1.45 joerg switch (isc->chiptype) {
374 1.45 joerg case CHIP_I915:
375 1.45 joerg case CHIP_G33:
376 1.45 joerg apbase = AGP_I915_GMADR;
377 1.79 riastrad mmadr_bar = AGP_I915_MMADR;
378 1.79 riastrad gtt_bar = AGP_I915_GTTADR;
379 1.80 riastrad gtt_off = ~(bus_addr_t)0; /* XXXGCC */
380 1.45 joerg break;
381 1.58 christos case CHIP_I965:
382 1.79 riastrad apbase = AGP_I965_GMADR;
383 1.79 riastrad mmadr_bar = AGP_I965_MMADR;
384 1.79 riastrad mmadr_type |= PCI_MAPREG_MEM_TYPE_64BIT;
385 1.79 riastrad gtt_bar = 0;
386 1.79 riastrad gtt_off = AGP_I965_GTT;
387 1.79 riastrad break;
388 1.58 christos case CHIP_G4X:
389 1.58 christos apbase = AGP_I965_GMADR;
390 1.79 riastrad mmadr_bar = AGP_I965_MMADR;
391 1.79 riastrad mmadr_type |= PCI_MAPREG_MEM_TYPE_64BIT;
392 1.79 riastrad gtt_bar = 0;
393 1.79 riastrad gtt_off = AGP_G4X_GTT;
394 1.58 christos break;
395 1.45 joerg default:
396 1.45 joerg apbase = AGP_I810_GMADR;
397 1.79 riastrad mmadr_bar = AGP_I810_MMADR;
398 1.79 riastrad gtt_bar = 0;
399 1.79 riastrad gtt_off = AGP_I810_GTT;
400 1.45 joerg break;
401 1.45 joerg }
402 1.58 christos
403 1.79 riastrad /* Map (or, rather, find the address and size of) the aperture. */
404 1.79 riastrad if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X)
405 1.58 christos error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase);
406 1.79 riastrad else
407 1.42 markd error = agp_map_aperture(&isc->vga_pa, sc, apbase);
408 1.79 riastrad if (error) {
409 1.28 christos aprint_error(": can't map aperture\n");
410 1.79 riastrad goto fail1;
411 1.1 fvdl }
412 1.1 fvdl
413 1.79 riastrad /* Map the memory-mapped I/O registers, or the non-GTT part. */
414 1.79 riastrad if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, mmadr_bar,
415 1.79 riastrad mmadr_type, &mmadr, &mmadr_size, &mmadr_flags)) {
416 1.79 riastrad aprint_error_dev(self, "can't find MMIO registers\n");
417 1.79 riastrad error = ENXIO;
418 1.79 riastrad goto fail1;
419 1.79 riastrad }
420 1.79 riastrad if (gtt_bar == 0) {
421 1.79 riastrad if (mmadr_size < gtt_off) {
422 1.79 riastrad aprint_error_dev(self, "MMIO registers too small"
423 1.79 riastrad ": %"PRIuMAX" < %"PRIuMAX"\n",
424 1.79 riastrad (uintmax_t)mmadr_size, (uintmax_t)gtt_off);
425 1.79 riastrad error = ENXIO;
426 1.79 riastrad goto fail1;
427 1.28 christos }
428 1.79 riastrad isc->size = gtt_off;
429 1.79 riastrad } else {
430 1.79 riastrad isc->size = mmadr_size;
431 1.79 riastrad }
432 1.79 riastrad isc->bst = isc->vga_pa.pa_memt;
433 1.79 riastrad error = bus_space_map(isc->bst, mmadr, isc->size, mmadr_flags,
434 1.79 riastrad &isc->bsh);
435 1.79 riastrad if (error) {
436 1.79 riastrad aprint_error_dev(self, "can't map MMIO registers: %d\n",
437 1.79 riastrad error);
438 1.79 riastrad error = ENXIO;
439 1.79 riastrad goto fail1;
440 1.79 riastrad }
441 1.79 riastrad
442 1.79 riastrad /* Map the GTT, from either part of the MMIO region or its own BAR. */
443 1.79 riastrad if (gtt_bar == 0) {
444 1.79 riastrad isc->gtt_bst = isc->bst;
445 1.79 riastrad isc->gtt_size = (mmadr_size - gtt_off);
446 1.79 riastrad error = bus_space_map(isc->gtt_bst, gtt_off, isc->gtt_size,
447 1.79 riastrad mmadr_flags, &isc->gtt_bsh);
448 1.79 riastrad if (error) {
449 1.79 riastrad aprint_error_dev(self, "can't map GTT: %d\n", error);
450 1.79 riastrad error = ENXIO;
451 1.79 riastrad goto fail2;
452 1.28 christos }
453 1.79 riastrad } else {
454 1.79 riastrad /*
455 1.79 riastrad * All chipsets with a separate BAR for the GTT, namely
456 1.79 riastrad * the i915 and G33 families, have 32-bit GTT BARs.
457 1.79 riastrad *
458 1.79 riastrad * XXX [citation needed]
459 1.79 riastrad */
460 1.79 riastrad if (pci_mapreg_map(&isc->vga_pa, gtt_bar, PCI_MAPREG_TYPE_MEM,
461 1.79 riastrad 0,
462 1.79 riastrad &isc->gtt_bst, &isc->gtt_bsh, NULL, &isc->gtt_size)) {
463 1.79 riastrad aprint_error_dev(self, "can't map GTT\n");
464 1.79 riastrad error = ENXIO;
465 1.79 riastrad goto fail2;
466 1.42 markd }
467 1.79 riastrad }
468 1.79 riastrad
469 1.79 riastrad /* Set up a chipset flush page if necessary. */
470 1.79 riastrad switch (isc->chiptype) {
471 1.79 riastrad case CHIP_I915:
472 1.79 riastrad case CHIP_I965:
473 1.79 riastrad case CHIP_G33:
474 1.79 riastrad case CHIP_G4X:
475 1.79 riastrad error = agp_i810_setup_chipset_flush_page(sc);
476 1.79 riastrad if (error) {
477 1.79 riastrad aprint_error_dev(self,
478 1.79 riastrad "failed to set up chipset flush page: %d\n",
479 1.79 riastrad error);
480 1.79 riastrad goto fail3;
481 1.28 christos }
482 1.79 riastrad break;
483 1.28 christos }
484 1.28 christos
485 1.79 riastrad /* Set up the generic AGP GATT record. */
486 1.1 fvdl isc->initial_aperture = AGP_GET_APERTURE(sc);
487 1.14 scw gatt = malloc(sizeof(struct agp_gatt), M_AGP, M_NOWAIT);
488 1.14 scw if (!gatt) {
489 1.79 riastrad error = ENOMEM;
490 1.79 riastrad goto fail4;
491 1.14 scw }
492 1.14 scw isc->gatt = gatt;
493 1.14 scw gatt->ag_entries = AGP_GET_APERTURE(sc) >> AGP_PAGE_SHIFT;
494 1.1 fvdl
495 1.79 riastrad /* Power management. (XXX Nothing to save on suspend? Fishy...) */
496 1.47 jmcneill if (!pmf_device_register(self, NULL, agp_i810_resume))
497 1.47 jmcneill aprint_error_dev(self, "couldn't establish power handler\n");
498 1.47 jmcneill
499 1.49 drochner /*
500 1.49 drochner * XXX horrible hack to allow drm code to use our mapping
501 1.49 drochner * of VGA chip registers
502 1.49 drochner */
503 1.49 drochner agp_i810_vga_regbase = mmadr;
504 1.49 drochner agp_i810_vga_bsh = isc->bsh;
505 1.49 drochner
506 1.79 riastrad /* Initialize the chipset. */
507 1.79 riastrad error = agp_i810_init(sc);
508 1.79 riastrad if (error)
509 1.79 riastrad goto fail5;
510 1.79 riastrad
511 1.79 riastrad /* Success! */
512 1.79 riastrad return 0;
513 1.79 riastrad
514 1.79 riastrad #if notyet
515 1.79 riastrad fail6: __unused
516 1.79 riastrad agp_i810_fini(sc);
517 1.79 riastrad #endif
518 1.79 riastrad fail5: pmf_device_deregister(self);
519 1.79 riastrad free(gatt, M_AGP);
520 1.79 riastrad isc->gatt = NULL;
521 1.79 riastrad fail4: switch (isc->chiptype) {
522 1.75 riastrad case CHIP_I915:
523 1.75 riastrad case CHIP_I965:
524 1.75 riastrad case CHIP_G33:
525 1.75 riastrad case CHIP_G4X:
526 1.79 riastrad agp_i810_teardown_chipset_flush_page(sc);
527 1.75 riastrad break;
528 1.75 riastrad }
529 1.79 riastrad fail3: bus_space_unmap(isc->gtt_bst, isc->gtt_bsh, isc->gtt_size);
530 1.79 riastrad isc->gtt_size = 0;
531 1.79 riastrad fail2: bus_space_unmap(isc->bst, isc->bsh, isc->size);
532 1.79 riastrad isc->size = 0;
533 1.79 riastrad fail1: free(isc, M_AGP);
534 1.79 riastrad sc->as_chipc = NULL;
535 1.79 riastrad fail0: agp_generic_detach(sc);
536 1.79 riastrad KASSERT(error);
537 1.79 riastrad return error;
538 1.45 joerg }
539 1.45 joerg
540 1.75 riastrad static int
541 1.75 riastrad agp_i810_setup_chipset_flush_page(struct agp_softc *sc)
542 1.75 riastrad {
543 1.75 riastrad struct agp_i810_softc *const isc = sc->as_chipc;
544 1.75 riastrad pcireg_t reg, lo, hi;
545 1.75 riastrad bus_addr_t addr, minaddr, maxaddr;
546 1.75 riastrad int error;
547 1.75 riastrad
548 1.75 riastrad /* We always use memory-mapped I/O. */
549 1.75 riastrad isc->flush_bst = isc->vga_pa.pa_memt;
550 1.75 riastrad
551 1.75 riastrad /* No page allocated yet. */
552 1.75 riastrad isc->flush_addr = 0;
553 1.75 riastrad
554 1.75 riastrad /* Read the PCI config register: 4-byte on gen3, 8-byte on gen>=4. */
555 1.75 riastrad if (isc->chiptype == CHIP_I915) {
556 1.75 riastrad reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR);
557 1.75 riastrad addr = reg;
558 1.75 riastrad minaddr = PAGE_SIZE; /* XXX PCIBIOS_MIN_MEM? */
559 1.75 riastrad maxaddr = UINT32_MAX;
560 1.75 riastrad } else {
561 1.75 riastrad hi = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I965_IFPADDR+4);
562 1.75 riastrad lo = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I965_IFPADDR);
563 1.76 riastrad /*
564 1.76 riastrad * Convert to uint64_t, rather than bus_addr_t which
565 1.76 riastrad * may be 32-bit, to avoid undefined behaviour with a
566 1.76 riastrad * too-wide shift. Since the BIOS doesn't know whether
567 1.76 riastrad * the OS will run 64-bit or with PAE, it ought to
568 1.76 riastrad * configure at most a 32-bit physical address, so
569 1.76 riastrad * let's print a warning in case that happens.
570 1.76 riastrad */
571 1.76 riastrad addr = ((uint64_t)hi << 32) | lo;
572 1.76 riastrad if (hi) {
573 1.76 riastrad aprint_error_dev(sc->as_dev,
574 1.76 riastrad "BIOS configured >32-bit flush page address"
575 1.76 riastrad ": %"PRIx64"\n", ((uint64_t)hi << 32) | lo);
576 1.76 riastrad #if __i386__ && !PAE
577 1.76 riastrad return EIO;
578 1.76 riastrad #endif
579 1.76 riastrad }
580 1.75 riastrad minaddr = PAGE_SIZE; /* XXX PCIBIOS_MIN_MEM? */
581 1.76 riastrad maxaddr = MIN(UINT64_MAX, ~(bus_addr_t)0);
582 1.75 riastrad }
583 1.75 riastrad
584 1.75 riastrad /* Allocate or map a pre-allocated a page for it. */
585 1.75 riastrad if (ISSET(addr, 1)) {
586 1.75 riastrad /* BIOS allocated it for us. Use that. */
587 1.75 riastrad error = bus_space_map(isc->flush_bst, addr & ~1, PAGE_SIZE, 0,
588 1.75 riastrad &isc->flush_bsh);
589 1.75 riastrad if (error)
590 1.75 riastrad return error;
591 1.75 riastrad } else {
592 1.75 riastrad /* None allocated. Allocate one. */
593 1.75 riastrad error = bus_space_alloc(isc->flush_bst, minaddr, maxaddr,
594 1.75 riastrad PAGE_SIZE, PAGE_SIZE, 0, 0,
595 1.75 riastrad &isc->flush_addr, &isc->flush_bsh);
596 1.75 riastrad if (error)
597 1.75 riastrad return error;
598 1.75 riastrad KASSERT(isc->flush_addr != 0);
599 1.75 riastrad /* Write it into the PCI config register. */
600 1.75 riastrad addr = isc->flush_addr | 1;
601 1.75 riastrad if (isc->chiptype == CHIP_I915) {
602 1.75 riastrad pci_conf_write(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR,
603 1.75 riastrad addr);
604 1.75 riastrad } else {
605 1.75 riastrad pci_conf_write(sc->as_pc, sc->as_tag,
606 1.75 riastrad AGP_I965_IFPADDR + 4,
607 1.75 riastrad __SHIFTOUT(addr, __BITS(63, 32)));
608 1.75 riastrad pci_conf_write(sc->as_pc, sc->as_tag,
609 1.75 riastrad AGP_I965_IFPADDR,
610 1.75 riastrad __SHIFTOUT(addr, __BITS(31, 0)));
611 1.75 riastrad }
612 1.75 riastrad }
613 1.75 riastrad
614 1.75 riastrad /* Success! */
615 1.75 riastrad return 0;
616 1.75 riastrad }
617 1.75 riastrad
618 1.79 riastrad static void
619 1.79 riastrad agp_i810_teardown_chipset_flush_page(struct agp_softc *sc)
620 1.79 riastrad {
621 1.79 riastrad struct agp_i810_softc *const isc = sc->as_chipc;
622 1.79 riastrad
623 1.79 riastrad if (isc->flush_addr) {
624 1.79 riastrad /* If we allocated a page, clear it. */
625 1.79 riastrad if (isc->chiptype == CHIP_I915) {
626 1.79 riastrad pci_conf_write(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR,
627 1.79 riastrad 0);
628 1.79 riastrad } else {
629 1.79 riastrad pci_conf_write(sc->as_pc, sc->as_tag,
630 1.79 riastrad AGP_I965_IFPADDR, 0);
631 1.79 riastrad pci_conf_write(sc->as_pc, sc->as_tag,
632 1.79 riastrad AGP_I965_IFPADDR + 4, 0);
633 1.79 riastrad }
634 1.79 riastrad isc->flush_addr = 0;
635 1.79 riastrad bus_space_free(isc->flush_bst, isc->flush_bsh,
636 1.79 riastrad PAGE_SIZE);
637 1.79 riastrad } else {
638 1.79 riastrad /* Otherwise, just unmap the pre-allocated page. */
639 1.79 riastrad bus_space_unmap(isc->flush_bst, isc->flush_bsh, PAGE_SIZE);
640 1.79 riastrad }
641 1.79 riastrad }
642 1.79 riastrad
643 1.49 drochner /*
644 1.49 drochner * XXX horrible hack to allow drm code to use our mapping
645 1.49 drochner * of VGA chip registers
646 1.49 drochner */
647 1.49 drochner int
648 1.49 drochner agp_i810_borrow(bus_addr_t base, bus_space_handle_t *hdlp)
649 1.49 drochner {
650 1.49 drochner
651 1.49 drochner if (!agp_i810_vga_regbase || base != agp_i810_vga_regbase)
652 1.49 drochner return 0;
653 1.49 drochner *hdlp = agp_i810_vga_bsh;
654 1.49 drochner return 1;
655 1.49 drochner }
656 1.49 drochner
657 1.45 joerg static int agp_i810_init(struct agp_softc *sc)
658 1.45 joerg {
659 1.45 joerg struct agp_i810_softc *isc;
660 1.45 joerg struct agp_gatt *gatt;
661 1.45 joerg
662 1.45 joerg isc = sc->as_chipc;
663 1.45 joerg gatt = isc->gatt;
664 1.45 joerg
665 1.14 scw if (isc->chiptype == CHIP_I810) {
666 1.36 christos void *virtual;
667 1.14 scw int dummyseg;
668 1.31 tron
669 1.14 scw /* Some i810s have on-chip memory called dcache */
670 1.14 scw if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED)
671 1.14 scw isc->dcache_size = 4 * 1024 * 1024;
672 1.14 scw else
673 1.14 scw isc->dcache_size = 0;
674 1.14 scw
675 1.14 scw /* According to the specs the gatt on the i810 must be 64k */
676 1.14 scw if (agp_alloc_dmamem(sc->as_dmat, 64 * 1024,
677 1.31 tron 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical,
678 1.31 tron &gatt->ag_dmaseg, 1, &dummyseg) != 0) {
679 1.14 scw free(gatt, M_AGP);
680 1.1 fvdl agp_generic_detach(sc);
681 1.1 fvdl return ENOMEM;
682 1.1 fvdl }
683 1.31 tron gatt->ag_virtual = (uint32_t *)virtual;
684 1.14 scw gatt->ag_size = gatt->ag_entries * sizeof(u_int32_t);
685 1.14 scw memset(gatt->ag_virtual, 0, gatt->ag_size);
686 1.25 perry
687 1.14 scw agp_flush_cache();
688 1.14 scw /* Install the GATT. */
689 1.14 scw WRITE4(AGP_I810_PGTBL_CTL, gatt->ag_physical | 1);
690 1.17 hannken } else if (isc->chiptype == CHIP_I830) {
691 1.14 scw /* The i830 automatically initializes the 128k gatt on boot. */
692 1.14 scw pcireg_t reg;
693 1.14 scw u_int32_t pgtblctl;
694 1.14 scw u_int16_t gcc1;
695 1.14 scw
696 1.14 scw reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0);
697 1.14 scw gcc1 = (u_int16_t)(reg >> 16);
698 1.14 scw switch (gcc1 & AGP_I830_GCC1_GMS) {
699 1.14 scw case AGP_I830_GCC1_GMS_STOLEN_512:
700 1.14 scw isc->stolen = (512 - 132) * 1024 / 4096;
701 1.14 scw break;
702 1.25 perry case AGP_I830_GCC1_GMS_STOLEN_1024:
703 1.14 scw isc->stolen = (1024 - 132) * 1024 / 4096;
704 1.14 scw break;
705 1.25 perry case AGP_I830_GCC1_GMS_STOLEN_8192:
706 1.14 scw isc->stolen = (8192 - 132) * 1024 / 4096;
707 1.14 scw break;
708 1.14 scw default:
709 1.14 scw isc->stolen = 0;
710 1.15 thorpej aprint_error(
711 1.15 thorpej ": unknown memory configuration, disabling\n");
712 1.14 scw agp_generic_detach(sc);
713 1.14 scw return EINVAL;
714 1.14 scw }
715 1.45 joerg
716 1.14 scw if (isc->stolen > 0) {
717 1.53 jmcneill aprint_normal(": detected %dk stolen memory\n%s",
718 1.54 freza isc->stolen * 4, device_xname(sc->as_dev));
719 1.14 scw }
720 1.17 hannken
721 1.17 hannken /* GATT address is already in there, make sure it's enabled */
722 1.17 hannken pgtblctl = READ4(AGP_I810_PGTBL_CTL);
723 1.17 hannken pgtblctl |= 1;
724 1.17 hannken WRITE4(AGP_I810_PGTBL_CTL, pgtblctl);
725 1.17 hannken
726 1.17 hannken gatt->ag_physical = pgtblctl & ~1;
727 1.42 markd } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 ||
728 1.58 christos isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 ||
729 1.58 christos isc->chiptype == CHIP_G4X) {
730 1.17 hannken pcireg_t reg;
731 1.58 christos u_int32_t pgtblctl, gtt_size, stolen;
732 1.17 hannken u_int16_t gcc1;
733 1.17 hannken
734 1.45 joerg reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1);
735 1.45 joerg gcc1 = (u_int16_t)(reg >> 16);
736 1.45 joerg
737 1.58 christos pgtblctl = READ4(AGP_I810_PGTBL_CTL);
738 1.58 christos
739 1.42 markd /* Stolen memory is set up at the beginning of the aperture by
740 1.42 markd * the BIOS, consisting of the GATT followed by 4kb for the
741 1.42 markd * BIOS display.
742 1.42 markd */
743 1.42 markd switch (isc->chiptype) {
744 1.42 markd case CHIP_I855:
745 1.58 christos gtt_size = 128;
746 1.42 markd break;
747 1.42 markd case CHIP_I915:
748 1.58 christos gtt_size = 256;
749 1.42 markd break;
750 1.42 markd case CHIP_I965:
751 1.60 christos switch (pgtblctl & AGP_I810_PGTBL_SIZE_MASK) {
752 1.58 christos case AGP_I810_PGTBL_SIZE_128KB:
753 1.58 christos case AGP_I810_PGTBL_SIZE_512KB:
754 1.58 christos gtt_size = 512;
755 1.58 christos break;
756 1.58 christos case AGP_I965_PGTBL_SIZE_1MB:
757 1.58 christos gtt_size = 1024;
758 1.58 christos break;
759 1.58 christos case AGP_I965_PGTBL_SIZE_2MB:
760 1.61 sketch gtt_size = 2048;
761 1.58 christos break;
762 1.58 christos case AGP_I965_PGTBL_SIZE_1_5MB:
763 1.61 sketch gtt_size = 1024 + 512;
764 1.58 christos break;
765 1.58 christos default:
766 1.58 christos aprint_error("Bad PGTBL size\n");
767 1.58 christos agp_generic_detach(sc);
768 1.58 christos return EINVAL;
769 1.58 christos }
770 1.42 markd break;
771 1.45 joerg case CHIP_G33:
772 1.45 joerg switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) {
773 1.45 joerg case AGP_G33_PGTBL_SIZE_1M:
774 1.58 christos gtt_size = 1024;
775 1.45 joerg break;
776 1.45 joerg case AGP_G33_PGTBL_SIZE_2M:
777 1.58 christos gtt_size = 2048;
778 1.45 joerg break;
779 1.45 joerg default:
780 1.58 christos aprint_error(": Bad PGTBL size\n");
781 1.45 joerg agp_generic_detach(sc);
782 1.45 joerg return EINVAL;
783 1.45 joerg }
784 1.45 joerg break;
785 1.58 christos case CHIP_G4X:
786 1.58 christos gtt_size = 0;
787 1.58 christos break;
788 1.42 markd default:
789 1.42 markd aprint_error(": bad chiptype\n");
790 1.42 markd agp_generic_detach(sc);
791 1.42 markd return EINVAL;
792 1.58 christos }
793 1.42 markd
794 1.17 hannken switch (gcc1 & AGP_I855_GCC1_GMS) {
795 1.17 hannken case AGP_I855_GCC1_GMS_STOLEN_1M:
796 1.58 christos stolen = 1024;
797 1.17 hannken break;
798 1.17 hannken case AGP_I855_GCC1_GMS_STOLEN_4M:
799 1.58 christos stolen = 4 * 1024;
800 1.17 hannken break;
801 1.17 hannken case AGP_I855_GCC1_GMS_STOLEN_8M:
802 1.58 christos stolen = 8 * 1024;
803 1.17 hannken break;
804 1.17 hannken case AGP_I855_GCC1_GMS_STOLEN_16M:
805 1.58 christos stolen = 16 * 1024;
806 1.17 hannken break;
807 1.17 hannken case AGP_I855_GCC1_GMS_STOLEN_32M:
808 1.58 christos stolen = 32 * 1024;
809 1.41 sborrill break;
810 1.41 sborrill case AGP_I915_GCC1_GMS_STOLEN_48M:
811 1.58 christos stolen = 48 * 1024;
812 1.41 sborrill break;
813 1.41 sborrill case AGP_I915_GCC1_GMS_STOLEN_64M:
814 1.58 christos stolen = 64 * 1024;
815 1.41 sborrill break;
816 1.46 markd case AGP_G33_GCC1_GMS_STOLEN_128M:
817 1.58 christos stolen = 128 * 1024;
818 1.46 markd break;
819 1.46 markd case AGP_G33_GCC1_GMS_STOLEN_256M:
820 1.58 christos stolen = 256 * 1024;
821 1.58 christos break;
822 1.58 christos case AGP_G4X_GCC1_GMS_STOLEN_96M:
823 1.58 christos stolen = 96 * 1024;
824 1.58 christos break;
825 1.58 christos case AGP_G4X_GCC1_GMS_STOLEN_160M:
826 1.58 christos stolen = 160 * 1024;
827 1.58 christos break;
828 1.58 christos case AGP_G4X_GCC1_GMS_STOLEN_224M:
829 1.58 christos stolen = 224 * 1024;
830 1.58 christos break;
831 1.58 christos case AGP_G4X_GCC1_GMS_STOLEN_352M:
832 1.58 christos stolen = 352 * 1024;
833 1.46 markd break;
834 1.28 christos default:
835 1.28 christos aprint_error(
836 1.28 christos ": unknown memory configuration, disabling\n");
837 1.28 christos agp_generic_detach(sc);
838 1.28 christos return EINVAL;
839 1.28 christos }
840 1.58 christos
841 1.58 christos switch (gcc1 & AGP_I855_GCC1_GMS) {
842 1.58 christos case AGP_I915_GCC1_GMS_STOLEN_48M:
843 1.58 christos case AGP_I915_GCC1_GMS_STOLEN_64M:
844 1.58 christos if (isc->chiptype != CHIP_I915 &&
845 1.58 christos isc->chiptype != CHIP_I965 &&
846 1.58 christos isc->chiptype != CHIP_G33 &&
847 1.58 christos isc->chiptype != CHIP_G4X)
848 1.58 christos stolen = 0;
849 1.58 christos break;
850 1.58 christos case AGP_G33_GCC1_GMS_STOLEN_128M:
851 1.58 christos case AGP_G33_GCC1_GMS_STOLEN_256M:
852 1.58 christos if (isc->chiptype != CHIP_I965 &&
853 1.58 christos isc->chiptype != CHIP_G33 &&
854 1.58 christos isc->chiptype != CHIP_G4X)
855 1.58 christos stolen = 0;
856 1.58 christos break;
857 1.58 christos case AGP_G4X_GCC1_GMS_STOLEN_96M:
858 1.58 christos case AGP_G4X_GCC1_GMS_STOLEN_160M:
859 1.58 christos case AGP_G4X_GCC1_GMS_STOLEN_224M:
860 1.58 christos case AGP_G4X_GCC1_GMS_STOLEN_352M:
861 1.58 christos if (isc->chiptype != CHIP_I965 &&
862 1.58 christos isc->chiptype != CHIP_G4X)
863 1.58 christos stolen = 0;
864 1.58 christos break;
865 1.58 christos }
866 1.58 christos
867 1.58 christos /* BIOS space */
868 1.62 markd gtt_size += 4;
869 1.58 christos
870 1.58 christos isc->stolen = (stolen - gtt_size) * 1024 / 4096;
871 1.58 christos
872 1.28 christos if (isc->stolen > 0) {
873 1.53 jmcneill aprint_normal(": detected %dk stolen memory\n%s",
874 1.54 freza isc->stolen * 4, device_xname(sc->as_dev));
875 1.28 christos }
876 1.28 christos
877 1.28 christos /* GATT address is already in there, make sure it's enabled */
878 1.28 christos pgtblctl |= 1;
879 1.28 christos WRITE4(AGP_I810_PGTBL_CTL, pgtblctl);
880 1.28 christos
881 1.28 christos gatt->ag_physical = pgtblctl & ~1;
882 1.1 fvdl }
883 1.1 fvdl
884 1.1 fvdl /*
885 1.1 fvdl * Make sure the chipset can see everything.
886 1.1 fvdl */
887 1.1 fvdl agp_flush_cache();
888 1.14 scw
889 1.74 riastrad /*
890 1.74 riastrad * Publish what we found for kludgey drivers (I'm looking at
891 1.74 riastrad * you, drm).
892 1.74 riastrad */
893 1.74 riastrad if (agp_i810_sc == NULL)
894 1.74 riastrad agp_i810_sc = sc;
895 1.74 riastrad else
896 1.74 riastrad aprint_error_dev(sc->as_dev, "i810 agp already attached\n");
897 1.74 riastrad
898 1.1 fvdl return 0;
899 1.1 fvdl }
900 1.1 fvdl
901 1.1 fvdl #if 0
902 1.1 fvdl static int
903 1.1 fvdl agp_i810_detach(struct agp_softc *sc)
904 1.1 fvdl {
905 1.1 fvdl int error;
906 1.1 fvdl struct agp_i810_softc *isc = sc->as_chipc;
907 1.1 fvdl
908 1.1 fvdl error = agp_generic_detach(sc);
909 1.1 fvdl if (error)
910 1.1 fvdl return error;
911 1.1 fvdl
912 1.75 riastrad switch (isc->chiptype) {
913 1.75 riastrad case CHIP_I915:
914 1.75 riastrad case CHIP_I965:
915 1.75 riastrad case CHIP_G33:
916 1.75 riastrad case CHIP_G4X:
917 1.79 riastrad agp_i810_teardown_chipset_flush_page(sc);
918 1.75 riastrad break;
919 1.75 riastrad }
920 1.75 riastrad
921 1.1 fvdl /* Clear the GATT base. */
922 1.14 scw if (sc->chiptype == CHIP_I810) {
923 1.14 scw WRITE4(AGP_I810_PGTBL_CTL, 0);
924 1.14 scw } else {
925 1.14 scw unsigned int pgtblctl;
926 1.14 scw pgtblctl = READ4(AGP_I810_PGTBL_CTL);
927 1.14 scw pgtblctl &= ~1;
928 1.14 scw WRITE4(AGP_I810_PGTBL_CTL, pgtblctl);
929 1.14 scw }
930 1.1 fvdl
931 1.1 fvdl /* Put the aperture back the way it started. */
932 1.1 fvdl AGP_SET_APERTURE(sc, isc->initial_aperture);
933 1.1 fvdl
934 1.14 scw if (sc->chiptype == CHIP_I810) {
935 1.14 scw agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap,
936 1.36 christos (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1);
937 1.14 scw }
938 1.14 scw free(sc->gatt, M_AGP);
939 1.1 fvdl
940 1.1 fvdl return 0;
941 1.1 fvdl }
942 1.1 fvdl #endif
943 1.1 fvdl
944 1.1 fvdl static u_int32_t
945 1.1 fvdl agp_i810_get_aperture(struct agp_softc *sc)
946 1.1 fvdl {
947 1.14 scw struct agp_i810_softc *isc = sc->as_chipc;
948 1.14 scw pcireg_t reg;
949 1.58 christos u_int32_t size;
950 1.42 markd u_int16_t miscc, gcc1, msac;
951 1.14 scw
952 1.58 christos size = 0;
953 1.58 christos
954 1.42 markd switch (isc->chiptype) {
955 1.42 markd case CHIP_I810:
956 1.14 scw reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM);
957 1.14 scw miscc = (u_int16_t)(reg >> 16);
958 1.14 scw if ((miscc & AGP_I810_MISCC_WINSIZE) ==
959 1.14 scw AGP_I810_MISCC_WINSIZE_32)
960 1.58 christos size = 32 * 1024 * 1024;
961 1.14 scw else
962 1.58 christos size = 64 * 1024 * 1024;
963 1.58 christos break;
964 1.42 markd case CHIP_I830:
965 1.14 scw reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0);
966 1.14 scw gcc1 = (u_int16_t)(reg >> 16);
967 1.14 scw if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64)
968 1.58 christos size = 64 * 1024 * 1024;
969 1.14 scw else
970 1.58 christos size = 128 * 1024 * 1024;
971 1.58 christos break;
972 1.42 markd case CHIP_I855:
973 1.58 christos size = 128 * 1024 * 1024;
974 1.58 christos break;
975 1.42 markd case CHIP_I915:
976 1.45 joerg case CHIP_G33:
977 1.64 markd case CHIP_G4X:
978 1.75 riastrad reg = pci_conf_read(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag,
979 1.75 riastrad AGP_I915_MSAC);
980 1.28 christos msac = (u_int16_t)(reg >> 16);
981 1.28 christos if (msac & AGP_I915_MSAC_APER_128M)
982 1.58 christos size = 128 * 1024 * 1024;
983 1.28 christos else
984 1.58 christos size = 256 * 1024 * 1024;
985 1.58 christos break;
986 1.42 markd case CHIP_I965:
987 1.58 christos size = 512 * 1024 * 1024;
988 1.58 christos break;
989 1.42 markd default:
990 1.42 markd aprint_error(": Unknown chipset\n");
991 1.14 scw }
992 1.42 markd
993 1.58 christos return size;
994 1.1 fvdl }
995 1.1 fvdl
996 1.1 fvdl static int
997 1.1 fvdl agp_i810_set_aperture(struct agp_softc *sc, u_int32_t aperture)
998 1.1 fvdl {
999 1.14 scw struct agp_i810_softc *isc = sc->as_chipc;
1000 1.14 scw pcireg_t reg;
1001 1.42 markd u_int16_t miscc, gcc1;
1002 1.14 scw
1003 1.42 markd switch (isc->chiptype) {
1004 1.42 markd case CHIP_I810:
1005 1.14 scw /*
1006 1.14 scw * Double check for sanity.
1007 1.14 scw */
1008 1.14 scw if (aperture != (32 * 1024 * 1024) &&
1009 1.14 scw aperture != (64 * 1024 * 1024)) {
1010 1.54 freza aprint_error_dev(sc->as_dev, "bad aperture size %d\n",
1011 1.52 cegger aperture);
1012 1.14 scw return EINVAL;
1013 1.14 scw }
1014 1.1 fvdl
1015 1.14 scw reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM);
1016 1.14 scw miscc = (u_int16_t)(reg >> 16);
1017 1.14 scw miscc &= ~AGP_I810_MISCC_WINSIZE;
1018 1.14 scw if (aperture == 32 * 1024 * 1024)
1019 1.14 scw miscc |= AGP_I810_MISCC_WINSIZE_32;
1020 1.14 scw else
1021 1.14 scw miscc |= AGP_I810_MISCC_WINSIZE_64;
1022 1.14 scw
1023 1.14 scw reg &= 0x0000ffff;
1024 1.14 scw reg |= ((pcireg_t)miscc) << 16;
1025 1.14 scw pci_conf_write(sc->as_pc, sc->as_tag, AGP_I810_SMRAM, reg);
1026 1.42 markd break;
1027 1.42 markd case CHIP_I830:
1028 1.14 scw if (aperture != (64 * 1024 * 1024) &&
1029 1.14 scw aperture != (128 * 1024 * 1024)) {
1030 1.54 freza aprint_error_dev(sc->as_dev, "bad aperture size %d\n",
1031 1.52 cegger aperture);
1032 1.14 scw return EINVAL;
1033 1.14 scw }
1034 1.14 scw reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0);
1035 1.14 scw gcc1 = (u_int16_t)(reg >> 16);
1036 1.14 scw gcc1 &= ~AGP_I830_GCC1_GMASIZE;
1037 1.14 scw if (aperture == 64 * 1024 * 1024)
1038 1.14 scw gcc1 |= AGP_I830_GCC1_GMASIZE_64;
1039 1.14 scw else
1040 1.14 scw gcc1 |= AGP_I830_GCC1_GMASIZE_128;
1041 1.14 scw
1042 1.14 scw reg &= 0x0000ffff;
1043 1.14 scw reg |= ((pcireg_t)gcc1) << 16;
1044 1.14 scw pci_conf_write(sc->as_pc, sc->as_tag, AGP_I830_GCC0, reg);
1045 1.42 markd break;
1046 1.42 markd case CHIP_I855:
1047 1.42 markd case CHIP_I915:
1048 1.28 christos if (aperture != agp_i810_get_aperture(sc)) {
1049 1.54 freza aprint_error_dev(sc->as_dev, "bad aperture size %d\n",
1050 1.52 cegger aperture);
1051 1.17 hannken return EINVAL;
1052 1.17 hannken }
1053 1.42 markd break;
1054 1.42 markd case CHIP_I965:
1055 1.42 markd if (aperture != 512 * 1024 * 1024) {
1056 1.54 freza aprint_error_dev(sc->as_dev, "bad aperture size %d\n",
1057 1.52 cegger aperture);
1058 1.42 markd return EINVAL;
1059 1.42 markd }
1060 1.42 markd break;
1061 1.1 fvdl }
1062 1.1 fvdl
1063 1.1 fvdl return 0;
1064 1.1 fvdl }
1065 1.1 fvdl
1066 1.1 fvdl static int
1067 1.1 fvdl agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical)
1068 1.1 fvdl {
1069 1.1 fvdl struct agp_i810_softc *isc = sc->as_chipc;
1070 1.1 fvdl
1071 1.14 scw if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) {
1072 1.29 rpaulo #ifdef AGP_DEBUG
1073 1.14 scw printf("%s: failed: offset 0x%08x, shift %d, entries %d\n",
1074 1.54 freza device_xname(sc->as_dev), (int)offset, AGP_PAGE_SHIFT,
1075 1.14 scw isc->gatt->ag_entries);
1076 1.14 scw #endif
1077 1.1 fvdl return EINVAL;
1078 1.14 scw }
1079 1.14 scw
1080 1.70 gsutre if (isc->chiptype != CHIP_I810) {
1081 1.14 scw if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) {
1082 1.29 rpaulo #ifdef AGP_DEBUG
1083 1.70 gsutre printf("%s: trying to bind into stolen memory\n",
1084 1.54 freza device_xname(sc->as_dev));
1085 1.14 scw #endif
1086 1.14 scw return EINVAL;
1087 1.14 scw }
1088 1.14 scw }
1089 1.1 fvdl
1090 1.71 gsutre return agp_i810_write_gtt_entry(isc, offset, physical | 1);
1091 1.1 fvdl }
1092 1.1 fvdl
1093 1.1 fvdl static int
1094 1.1 fvdl agp_i810_unbind_page(struct agp_softc *sc, off_t offset)
1095 1.1 fvdl {
1096 1.1 fvdl struct agp_i810_softc *isc = sc->as_chipc;
1097 1.1 fvdl
1098 1.1 fvdl if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT))
1099 1.1 fvdl return EINVAL;
1100 1.1 fvdl
1101 1.17 hannken if (isc->chiptype != CHIP_I810 ) {
1102 1.14 scw if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) {
1103 1.29 rpaulo #ifdef AGP_DEBUG
1104 1.70 gsutre printf("%s: trying to unbind from stolen memory\n",
1105 1.54 freza device_xname(sc->as_dev));
1106 1.14 scw #endif
1107 1.14 scw return EINVAL;
1108 1.14 scw }
1109 1.14 scw }
1110 1.14 scw
1111 1.71 gsutre return agp_i810_write_gtt_entry(isc, offset, 0);
1112 1.1 fvdl }
1113 1.1 fvdl
1114 1.1 fvdl /*
1115 1.1 fvdl * Writing via memory mapped registers already flushes all TLBs.
1116 1.1 fvdl */
1117 1.1 fvdl static void
1118 1.35 christos agp_i810_flush_tlb(struct agp_softc *sc)
1119 1.1 fvdl {
1120 1.1 fvdl }
1121 1.1 fvdl
1122 1.1 fvdl static int
1123 1.35 christos agp_i810_enable(struct agp_softc *sc, u_int32_t mode)
1124 1.1 fvdl {
1125 1.1 fvdl
1126 1.1 fvdl return 0;
1127 1.1 fvdl }
1128 1.1 fvdl
1129 1.1 fvdl static struct agp_memory *
1130 1.1 fvdl agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size)
1131 1.1 fvdl {
1132 1.1 fvdl struct agp_i810_softc *isc = sc->as_chipc;
1133 1.1 fvdl struct agp_memory *mem;
1134 1.1 fvdl
1135 1.29 rpaulo #ifdef AGP_DEBUG
1136 1.28 christos printf("AGP: alloc(%d, 0x%x)\n", type, (int) size);
1137 1.28 christos #endif
1138 1.28 christos
1139 1.1 fvdl if ((size & (AGP_PAGE_SIZE - 1)) != 0)
1140 1.1 fvdl return 0;
1141 1.1 fvdl
1142 1.1 fvdl if (sc->as_allocated + size > sc->as_maxmem)
1143 1.1 fvdl return 0;
1144 1.1 fvdl
1145 1.1 fvdl if (type == 1) {
1146 1.1 fvdl /*
1147 1.1 fvdl * Mapping local DRAM into GATT.
1148 1.1 fvdl */
1149 1.17 hannken if (isc->chiptype != CHIP_I810 )
1150 1.14 scw return 0;
1151 1.1 fvdl if (size != isc->dcache_size)
1152 1.1 fvdl return 0;
1153 1.1 fvdl } else if (type == 2) {
1154 1.1 fvdl /*
1155 1.28 christos * Bogus mapping for the hardware cursor.
1156 1.1 fvdl */
1157 1.28 christos if (size != AGP_PAGE_SIZE && size != 4 * AGP_PAGE_SIZE)
1158 1.1 fvdl return 0;
1159 1.1 fvdl }
1160 1.1 fvdl
1161 1.10 tsutsui mem = malloc(sizeof *mem, M_AGP, M_WAITOK|M_ZERO);
1162 1.1 fvdl if (mem == NULL)
1163 1.1 fvdl return NULL;
1164 1.1 fvdl mem->am_id = sc->as_nextid++;
1165 1.1 fvdl mem->am_size = size;
1166 1.1 fvdl mem->am_type = type;
1167 1.1 fvdl
1168 1.1 fvdl if (type == 2) {
1169 1.1 fvdl /*
1170 1.28 christos * Allocate and wire down the memory now so that we can
1171 1.1 fvdl * get its physical address.
1172 1.1 fvdl */
1173 1.1 fvdl mem->am_dmaseg = malloc(sizeof *mem->am_dmaseg, M_AGP,
1174 1.1 fvdl M_WAITOK);
1175 1.1 fvdl if (mem->am_dmaseg == NULL) {
1176 1.1 fvdl free(mem, M_AGP);
1177 1.1 fvdl return NULL;
1178 1.1 fvdl }
1179 1.1 fvdl if (agp_alloc_dmamem(sc->as_dmat, size, 0,
1180 1.1 fvdl &mem->am_dmamap, &mem->am_virtual, &mem->am_physical,
1181 1.1 fvdl mem->am_dmaseg, 1, &mem->am_nseg) != 0) {
1182 1.1 fvdl free(mem->am_dmaseg, M_AGP);
1183 1.1 fvdl free(mem, M_AGP);
1184 1.1 fvdl return NULL;
1185 1.1 fvdl }
1186 1.28 christos memset(mem->am_virtual, 0, size);
1187 1.1 fvdl } else if (type != 1) {
1188 1.4 drochner if (bus_dmamap_create(sc->as_dmat, size, size / PAGE_SIZE + 1,
1189 1.4 drochner size, 0, BUS_DMA_NOWAIT,
1190 1.4 drochner &mem->am_dmamap) != 0) {
1191 1.1 fvdl free(mem, M_AGP);
1192 1.1 fvdl return NULL;
1193 1.1 fvdl }
1194 1.1 fvdl }
1195 1.1 fvdl
1196 1.1 fvdl TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link);
1197 1.1 fvdl sc->as_allocated += size;
1198 1.1 fvdl
1199 1.1 fvdl return mem;
1200 1.1 fvdl }
1201 1.1 fvdl
1202 1.1 fvdl static int
1203 1.1 fvdl agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem)
1204 1.1 fvdl {
1205 1.1 fvdl if (mem->am_is_bound)
1206 1.1 fvdl return EBUSY;
1207 1.1 fvdl
1208 1.1 fvdl if (mem->am_type == 2) {
1209 1.1 fvdl agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap,
1210 1.1 fvdl mem->am_virtual, mem->am_dmaseg, mem->am_nseg);
1211 1.1 fvdl free(mem->am_dmaseg, M_AGP);
1212 1.1 fvdl }
1213 1.1 fvdl
1214 1.1 fvdl sc->as_allocated -= mem->am_size;
1215 1.1 fvdl TAILQ_REMOVE(&sc->as_memory, mem, am_link);
1216 1.1 fvdl free(mem, M_AGP);
1217 1.1 fvdl return 0;
1218 1.1 fvdl }
1219 1.1 fvdl
1220 1.1 fvdl static int
1221 1.1 fvdl agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem,
1222 1.1 fvdl off_t offset)
1223 1.1 fvdl {
1224 1.1 fvdl struct agp_i810_softc *isc = sc->as_chipc;
1225 1.4 drochner u_int32_t regval, i;
1226 1.4 drochner
1227 1.70 gsutre if (mem->am_is_bound != 0)
1228 1.70 gsutre return EINVAL;
1229 1.70 gsutre
1230 1.4 drochner /*
1231 1.4 drochner * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the
1232 1.4 drochner * X server for mysterious reasons which leads to crashes if we write
1233 1.4 drochner * to the GTT through the MMIO window.
1234 1.4 drochner * Until the issue is solved, simply restore it.
1235 1.4 drochner */
1236 1.4 drochner regval = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL);
1237 1.4 drochner if (regval != (isc->gatt->ag_physical | 1)) {
1238 1.4 drochner printf("agp_i810_bind_memory: PGTBL_CTL is 0x%x - fixing\n",
1239 1.4 drochner regval);
1240 1.4 drochner bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL,
1241 1.4 drochner isc->gatt->ag_physical | 1);
1242 1.4 drochner }
1243 1.1 fvdl
1244 1.5 drochner if (mem->am_type == 2) {
1245 1.70 gsutre for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE)
1246 1.70 gsutre agp_i810_bind_page(sc, offset + i,
1247 1.70 gsutre mem->am_physical + i);
1248 1.5 drochner mem->am_offset = offset;
1249 1.5 drochner mem->am_is_bound = 1;
1250 1.1 fvdl return 0;
1251 1.5 drochner }
1252 1.5 drochner
1253 1.1 fvdl if (mem->am_type != 1)
1254 1.1 fvdl return agp_generic_bind_memory(sc, mem, offset);
1255 1.1 fvdl
1256 1.17 hannken if (isc->chiptype != CHIP_I810)
1257 1.14 scw return EINVAL;
1258 1.14 scw
1259 1.28 christos for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE)
1260 1.70 gsutre agp_i810_write_gtt_entry(isc, i, i | 3);
1261 1.13 drochner mem->am_is_bound = 1;
1262 1.1 fvdl return 0;
1263 1.1 fvdl }
1264 1.1 fvdl
1265 1.1 fvdl static int
1266 1.1 fvdl agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem)
1267 1.1 fvdl {
1268 1.1 fvdl struct agp_i810_softc *isc = sc->as_chipc;
1269 1.1 fvdl u_int32_t i;
1270 1.1 fvdl
1271 1.70 gsutre if (mem->am_is_bound == 0)
1272 1.70 gsutre return EINVAL;
1273 1.70 gsutre
1274 1.5 drochner if (mem->am_type == 2) {
1275 1.70 gsutre for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE)
1276 1.70 gsutre agp_i810_unbind_page(sc, mem->am_offset + i);
1277 1.5 drochner mem->am_offset = 0;
1278 1.5 drochner mem->am_is_bound = 0;
1279 1.1 fvdl return 0;
1280 1.5 drochner }
1281 1.1 fvdl
1282 1.1 fvdl if (mem->am_type != 1)
1283 1.1 fvdl return agp_generic_unbind_memory(sc, mem);
1284 1.14 scw
1285 1.17 hannken if (isc->chiptype != CHIP_I810)
1286 1.14 scw return EINVAL;
1287 1.1 fvdl
1288 1.1 fvdl for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE)
1289 1.58 christos agp_i810_write_gtt_entry(isc, i, 0);
1290 1.13 drochner mem->am_is_bound = 0;
1291 1.1 fvdl return 0;
1292 1.1 fvdl }
1293 1.24 jmcneill
1294 1.47 jmcneill static bool
1295 1.66 dyoung agp_i810_resume(device_t dv, const pmf_qual_t *qual)
1296 1.24 jmcneill {
1297 1.47 jmcneill struct agp_softc *sc = device_private(dv);
1298 1.24 jmcneill struct agp_i810_softc *isc = sc->as_chipc;
1299 1.24 jmcneill
1300 1.79 riastrad /*
1301 1.79 riastrad * XXX Nothing uses isc->pgtblctl! Save on suspend, restore on
1302 1.79 riastrad * resume?
1303 1.79 riastrad */
1304 1.47 jmcneill isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL);
1305 1.47 jmcneill agp_flush_cache();
1306 1.24 jmcneill
1307 1.47 jmcneill return true;
1308 1.24 jmcneill }
1309