agp_i810.c revision 1.105
1 /* $NetBSD: agp_i810.c,v 1.105 2014/06/25 15:04:53 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.105 2014/06/25 15:04:53 riastradh Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/proc.h> 40 #include <sys/device.h> 41 #include <sys/conf.h> 42 #include <sys/xcall.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcidevs.h> 47 #include <dev/pci/agpvar.h> 48 #include <dev/pci/agpreg.h> 49 #include <dev/pci/agp_i810var.h> 50 51 #include <sys/agpio.h> 52 53 #include <sys/bus.h> 54 55 #include "agp_intel.h" 56 57 struct agp_softc *agp_i810_sc = NULL; 58 59 #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off) 60 #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off) 61 #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v) 62 63 #define CHIP_I810 0 /* i810/i815 */ 64 #define CHIP_I830 1 /* 830M/845G */ 65 #define CHIP_I855 2 /* 852GM/855GM/865G */ 66 #define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */ 67 #define CHIP_I965 4 /* 965Q/965PM */ 68 #define CHIP_G33 5 /* G33/Q33/Q35 */ 69 #define CHIP_G4X 6 /* G45/Q45 */ 70 71 /* XXX hack, see below */ 72 static bus_addr_t agp_i810_vga_regbase; 73 static bus_size_t agp_i810_vga_regsize; 74 static bus_space_tag_t agp_i810_vga_bst; 75 static bus_space_handle_t agp_i810_vga_bsh; 76 77 static u_int32_t agp_i810_get_aperture(struct agp_softc *); 78 static int agp_i810_set_aperture(struct agp_softc *, u_int32_t); 79 static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t); 80 static int agp_i810_unbind_page(struct agp_softc *, off_t); 81 static void agp_i810_flush_tlb(struct agp_softc *); 82 static int agp_i810_enable(struct agp_softc *, u_int32_t mode); 83 static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int, 84 vsize_t); 85 static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *); 86 static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, 87 off_t); 88 static int agp_i810_bind_memory_dcache(struct agp_softc *, struct agp_memory *, 89 off_t); 90 static int agp_i810_bind_memory_hwcursor(struct agp_softc *, 91 struct agp_memory *, off_t); 92 static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *); 93 94 static bool agp_i810_resume(device_t, const pmf_qual_t *); 95 static int agp_i810_init(struct agp_softc *); 96 97 static int agp_i810_setup_chipset_flush_page(struct agp_softc *); 98 static void agp_i810_teardown_chipset_flush_page(struct agp_softc *); 99 static int agp_i810_init(struct agp_softc *); 100 101 static struct agp_methods agp_i810_methods = { 102 agp_i810_get_aperture, 103 agp_i810_set_aperture, 104 agp_i810_bind_page, 105 agp_i810_unbind_page, 106 agp_i810_flush_tlb, 107 agp_i810_enable, 108 agp_i810_alloc_memory, 109 agp_i810_free_memory, 110 agp_i810_bind_memory, 111 agp_i810_unbind_memory, 112 }; 113 114 int 115 agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, bus_addr_t v) 116 { 117 u_int32_t pte; 118 119 /* Bits 11:4 (physical start address extension) should be zero. */ 120 if ((v & 0xff0) != 0) 121 return EINVAL; 122 123 pte = (u_int32_t)v; 124 /* 125 * We need to massage the pte if bus_addr_t is wider than 32 bits. 126 * The compiler isn't smart enough, hence the casts to uintmax_t. 127 */ 128 if (sizeof(bus_addr_t) > sizeof(u_int32_t)) { 129 /* 965+ can do 36-bit addressing, add in the extra bits. */ 130 if (isc->chiptype == CHIP_I965 || 131 isc->chiptype == CHIP_G33 || 132 isc->chiptype == CHIP_G4X) { 133 if (((uintmax_t)v >> 36) != 0) 134 return EINVAL; 135 pte |= (v >> 28) & 0xf0; 136 } else { 137 if (((uintmax_t)v >> 32) != 0) 138 return EINVAL; 139 } 140 } 141 142 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, 143 4*(off >> AGP_PAGE_SHIFT), pte); 144 145 return 0; 146 } 147 148 void 149 agp_i810_post_gtt_entry(struct agp_i810_softc *isc, off_t off) 150 { 151 152 (void)bus_space_read_4(isc->gtt_bst, isc->gtt_bsh, 153 4*(off >> AGP_PAGE_SHIFT)); 154 } 155 156 static void 157 agp_flush_cache_xc(void *a __unused, void *b __unused) 158 { 159 160 agp_flush_cache(); 161 } 162 163 void 164 agp_i810_chipset_flush(struct agp_i810_softc *isc) 165 { 166 unsigned int timo = 20000; /* * 50 us = 1 s */ 167 168 switch (isc->chiptype) { 169 case CHIP_I810: 170 break; 171 case CHIP_I830: 172 case CHIP_I855: 173 /* 174 * Flush all CPU caches. If we're cold, we can't run 175 * xcalls, but there should be only one CPU up, so 176 * flushing only the local CPU's cache should suffice. 177 * 178 * XXX Come to think of it, do these chipsets appear in 179 * any multi-CPU systems? 180 */ 181 if (cold) 182 agp_flush_cache(); 183 else 184 xc_wait(xc_broadcast(0, &agp_flush_cache_xc, 185 NULL, NULL)); 186 WRITE4(AGP_I830_HIC, READ4(AGP_I830_HIC) | __BIT(31)); 187 while (ISSET(READ4(AGP_I830_HIC), __BIT(31))) { 188 if (timo-- == 0) 189 break; 190 DELAY(50); 191 } 192 break; 193 case CHIP_I915: 194 case CHIP_I965: 195 case CHIP_G33: 196 case CHIP_G4X: 197 bus_space_write_4(isc->flush_bst, isc->flush_bsh, 0, 1); 198 break; 199 } 200 } 201 202 /* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */ 203 static int 204 agp_i810_vgamatch(const struct pci_attach_args *pa) 205 { 206 207 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 208 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 209 return (0); 210 211 switch (PCI_PRODUCT(pa->pa_id)) { 212 case PCI_PRODUCT_INTEL_82810_GC: 213 case PCI_PRODUCT_INTEL_82810_DC100_GC: 214 case PCI_PRODUCT_INTEL_82810E_GC: 215 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 216 case PCI_PRODUCT_INTEL_82830MP_IV: 217 case PCI_PRODUCT_INTEL_82845G_IGD: 218 case PCI_PRODUCT_INTEL_82855GM_IGD: 219 case PCI_PRODUCT_INTEL_82865_IGD: 220 case PCI_PRODUCT_INTEL_82915G_IGD: 221 case PCI_PRODUCT_INTEL_82915GM_IGD: 222 case PCI_PRODUCT_INTEL_82945P_IGD: 223 case PCI_PRODUCT_INTEL_82945GM_IGD: 224 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 225 case PCI_PRODUCT_INTEL_82945GME_IGD: 226 case PCI_PRODUCT_INTEL_E7221_IGD: 227 case PCI_PRODUCT_INTEL_82965Q_IGD: 228 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 229 case PCI_PRODUCT_INTEL_82965PM_IGD: 230 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 231 case PCI_PRODUCT_INTEL_82G33_IGD: 232 case PCI_PRODUCT_INTEL_82G33_IGD_1: 233 case PCI_PRODUCT_INTEL_82965G_IGD: 234 case PCI_PRODUCT_INTEL_82965G_IGD_1: 235 case PCI_PRODUCT_INTEL_82965GME_IGD: 236 case PCI_PRODUCT_INTEL_82Q35_IGD: 237 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 238 case PCI_PRODUCT_INTEL_82Q33_IGD: 239 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 240 case PCI_PRODUCT_INTEL_82G35_IGD: 241 case PCI_PRODUCT_INTEL_82G35_IGD_1: 242 case PCI_PRODUCT_INTEL_82946GZ_IGD: 243 case PCI_PRODUCT_INTEL_82GM45_IGD: 244 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 245 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 246 case PCI_PRODUCT_INTEL_82Q45_IGD: 247 case PCI_PRODUCT_INTEL_82G45_IGD: 248 case PCI_PRODUCT_INTEL_82G41_IGD: 249 case PCI_PRODUCT_INTEL_82B43_IGD: 250 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 251 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 252 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 253 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 254 return (1); 255 } 256 257 return (0); 258 } 259 260 static int 261 agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg) 262 { 263 /* 264 * Find the aperture. Don't map it (yet), this would 265 * eat KVA. 266 */ 267 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 268 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize, 269 &sc->as_apflags) != 0) 270 return ENXIO; 271 272 sc->as_apt = pa->pa_memt; 273 274 return 0; 275 } 276 277 int 278 agp_i810_attach(device_t parent, device_t self, void *aux) 279 { 280 struct agp_softc *sc = device_private(self); 281 struct agp_i810_softc *isc; 282 int apbase, mmadr_bar, gtt_bar; 283 int mmadr_type, mmadr_flags; 284 bus_addr_t mmadr; 285 bus_size_t mmadr_size, gtt_off; 286 int error; 287 288 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 289 if (isc == NULL) { 290 aprint_error(": can't allocate chipset-specific softc\n"); 291 error = ENOMEM; 292 goto fail0; 293 } 294 sc->as_chipc = isc; 295 sc->as_methods = &agp_i810_methods; 296 297 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) { 298 #if NAGP_INTEL > 0 299 const struct pci_attach_args *pa = aux; 300 301 switch (PCI_PRODUCT(pa->pa_id)) { 302 case PCI_PRODUCT_INTEL_82840_HB: 303 case PCI_PRODUCT_INTEL_82865_HB: 304 case PCI_PRODUCT_INTEL_82845G_DRAM: 305 case PCI_PRODUCT_INTEL_82815_FULL_HUB: 306 case PCI_PRODUCT_INTEL_82855GM_MCH: 307 free(isc, M_AGP); 308 return agp_intel_attach(parent, self, aux); 309 } 310 #endif 311 aprint_error(": can't find internal VGA" 312 " config space\n"); 313 error = ENOENT; 314 goto fail1; 315 } 316 317 /* XXXfvdl */ 318 sc->as_dmat = isc->vga_pa.pa_dmat; 319 320 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 321 case PCI_PRODUCT_INTEL_82810_GC: 322 case PCI_PRODUCT_INTEL_82810_DC100_GC: 323 case PCI_PRODUCT_INTEL_82810E_GC: 324 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 325 isc->chiptype = CHIP_I810; 326 aprint_normal(": i810-family chipset\n"); 327 break; 328 case PCI_PRODUCT_INTEL_82830MP_IV: 329 case PCI_PRODUCT_INTEL_82845G_IGD: 330 isc->chiptype = CHIP_I830; 331 aprint_normal(": i830-family chipset\n"); 332 break; 333 case PCI_PRODUCT_INTEL_82855GM_IGD: 334 case PCI_PRODUCT_INTEL_82865_IGD: 335 isc->chiptype = CHIP_I855; 336 aprint_normal(": i855-family chipset\n"); 337 break; 338 case PCI_PRODUCT_INTEL_82915G_IGD: 339 case PCI_PRODUCT_INTEL_82915GM_IGD: 340 case PCI_PRODUCT_INTEL_82945P_IGD: 341 case PCI_PRODUCT_INTEL_82945GM_IGD: 342 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 343 case PCI_PRODUCT_INTEL_82945GME_IGD: 344 case PCI_PRODUCT_INTEL_E7221_IGD: 345 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 346 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 347 isc->chiptype = CHIP_I915; 348 aprint_normal(": i915-family chipset\n"); 349 break; 350 case PCI_PRODUCT_INTEL_82965Q_IGD: 351 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 352 case PCI_PRODUCT_INTEL_82965PM_IGD: 353 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 354 case PCI_PRODUCT_INTEL_82965G_IGD: 355 case PCI_PRODUCT_INTEL_82965G_IGD_1: 356 case PCI_PRODUCT_INTEL_82965GME_IGD: 357 case PCI_PRODUCT_INTEL_82946GZ_IGD: 358 case PCI_PRODUCT_INTEL_82G35_IGD: 359 case PCI_PRODUCT_INTEL_82G35_IGD_1: 360 isc->chiptype = CHIP_I965; 361 aprint_normal(": i965-family chipset\n"); 362 break; 363 case PCI_PRODUCT_INTEL_82Q35_IGD: 364 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 365 case PCI_PRODUCT_INTEL_82G33_IGD: 366 case PCI_PRODUCT_INTEL_82G33_IGD_1: 367 case PCI_PRODUCT_INTEL_82Q33_IGD: 368 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 369 isc->chiptype = CHIP_G33; 370 aprint_normal(": G33-family chipset\n"); 371 break; 372 case PCI_PRODUCT_INTEL_82GM45_IGD: 373 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 374 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 375 case PCI_PRODUCT_INTEL_82Q45_IGD: 376 case PCI_PRODUCT_INTEL_82G45_IGD: 377 case PCI_PRODUCT_INTEL_82G41_IGD: 378 case PCI_PRODUCT_INTEL_82B43_IGD: 379 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 380 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 381 isc->chiptype = CHIP_G4X; 382 aprint_normal(": G4X-family chipset\n"); 383 break; 384 } 385 aprint_naive("\n"); 386 387 mmadr_type = PCI_MAPREG_TYPE_MEM; 388 switch (isc->chiptype) { 389 case CHIP_I915: 390 case CHIP_G33: 391 apbase = AGP_I915_GMADR; 392 mmadr_bar = AGP_I915_MMADR; 393 isc->size = 512*1024; 394 gtt_bar = AGP_I915_GTTADR; 395 gtt_off = ~(bus_size_t)0; /* XXXGCC */ 396 break; 397 case CHIP_I965: 398 apbase = AGP_I965_GMADR; 399 mmadr_bar = AGP_I965_MMADR; 400 mmadr_type |= PCI_MAPREG_MEM_TYPE_64BIT; 401 isc->size = 512*1024; 402 gtt_bar = 0; 403 gtt_off = AGP_I965_GTT; 404 break; 405 case CHIP_G4X: 406 apbase = AGP_I965_GMADR; 407 mmadr_bar = AGP_I965_MMADR; 408 mmadr_type |= PCI_MAPREG_MEM_TYPE_64BIT; 409 isc->size = 512*1024; 410 gtt_bar = 0; 411 gtt_off = AGP_G4X_GTT; 412 break; 413 default: 414 apbase = AGP_I810_GMADR; 415 mmadr_bar = AGP_I810_MMADR; 416 isc->size = 512*1024; 417 gtt_bar = 0; 418 gtt_off = AGP_I810_GTT; 419 break; 420 } 421 422 /* Map (or, rather, find the address and size of) the aperture. */ 423 if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) 424 error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase); 425 else 426 error = agp_map_aperture(&isc->vga_pa, sc, apbase); 427 if (error) { 428 aprint_error_dev(self, "can't map aperture: %d\n", error); 429 goto fail1; 430 } 431 432 /* Map the memory-mapped I/O registers, or the non-GTT part. */ 433 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, mmadr_bar, 434 mmadr_type, &mmadr, &mmadr_size, &mmadr_flags)) { 435 aprint_error_dev(self, "can't find MMIO registers\n"); 436 error = ENXIO; 437 goto fail1; 438 } 439 if (mmadr_size < isc->size) { 440 aprint_error_dev(self, "MMIO registers too small" 441 ": %"PRIuMAX" < %"PRIuMAX"\n", 442 (uintmax_t)mmadr_size, (uintmax_t)isc->size); 443 error = ENXIO; 444 goto fail1; 445 } 446 isc->bst = isc->vga_pa.pa_memt; 447 error = bus_space_map(isc->bst, mmadr, isc->size, mmadr_flags, 448 &isc->bsh); 449 if (error) { 450 aprint_error_dev(self, "can't map MMIO registers: %d\n", 451 error); 452 error = ENXIO; 453 goto fail1; 454 } 455 456 /* Set up a chipset flush page if necessary. */ 457 switch (isc->chiptype) { 458 case CHIP_I915: 459 case CHIP_I965: 460 case CHIP_G33: 461 case CHIP_G4X: 462 error = agp_i810_setup_chipset_flush_page(sc); 463 if (error) { 464 aprint_error_dev(self, 465 "can't set up chipset flush page: %d\n", error); 466 goto fail2; 467 } 468 break; 469 } 470 471 /* 472 * XXX horrible hack to allow drm code to use our mapping 473 * of VGA chip registers 474 */ 475 agp_i810_vga_regbase = mmadr; 476 agp_i810_vga_regsize = isc->size; 477 agp_i810_vga_bst = isc->bst; 478 agp_i810_vga_bsh = isc->bsh; 479 480 /* Initialize the chipset. */ 481 error = agp_i810_init(sc); 482 if (error) 483 goto fail3; 484 485 /* Map the GTT, from either part of the MMIO region or its own BAR. */ 486 if (gtt_bar == 0) { 487 isc->gtt_bst = isc->bst; 488 if ((mmadr_size - gtt_off) < isc->gtt_size) { 489 aprint_error_dev(self, "GTTMMADR too small for GTT" 490 ": (%"PRIxMAX" - %"PRIxMAX") < %"PRIxMAX"\n", 491 (uintmax_t)mmadr_size, 492 (uintmax_t)gtt_off, 493 (uintmax_t)isc->gtt_size); 494 error = ENXIO; 495 goto fail4; 496 } 497 /* 498 * Map the GTT separately if we can, so that we can map 499 * it prefetchable, but in early models, there are MMIO 500 * registers before and after the GTT, so we can only 501 * take a subregion. 502 */ 503 if (isc->size < gtt_off) 504 error = bus_space_map(isc->gtt_bst, (mmadr + gtt_off), 505 isc->gtt_size, mmadr_flags, &isc->gtt_bsh); 506 else 507 error = bus_space_subregion(isc->bst, isc->bsh, 508 gtt_off, isc->gtt_size, &isc->gtt_bsh); 509 if (error) { 510 aprint_error_dev(self, "can't map GTT: %d\n", error); 511 error = ENXIO; 512 goto fail4; 513 } 514 } else { 515 bus_size_t gtt_bar_size; 516 /* 517 * All chipsets with a separate BAR for the GTT, namely 518 * the i915 and G33 families, have 32-bit GTT BARs. 519 * 520 * XXX [citation needed] 521 */ 522 if (pci_mapreg_map(&isc->vga_pa, gtt_bar, PCI_MAPREG_TYPE_MEM, 523 0, 524 &isc->gtt_bst, &isc->gtt_bsh, NULL, >t_bar_size)) { 525 aprint_error_dev(self, "can't map GTT\n"); 526 error = ENXIO; 527 goto fail4; 528 } 529 if (gtt_bar_size != isc->gtt_size) { 530 aprint_error_dev(self, 531 "BAR size %"PRIxMAX 532 " mismatches detected GTT size %"PRIxMAX 533 "; trusting BAR\n", 534 (uintmax_t)gtt_bar_size, 535 (uintmax_t)isc->gtt_size); 536 isc->gtt_size = gtt_bar_size; 537 } 538 } 539 540 /* Power management. (XXX Nothing to save on suspend? Fishy...) */ 541 if (!pmf_device_register(self, NULL, agp_i810_resume)) 542 aprint_error_dev(self, "can't establish power handler\n"); 543 544 /* Match the generic AGP code's autoconf output format. */ 545 aprint_normal("%s", device_xname(self)); 546 547 /* Success! */ 548 return 0; 549 550 fail5: __unused 551 pmf_device_deregister(self); 552 if ((gtt_bar != 0) || (isc->size < gtt_off)) 553 bus_space_unmap(isc->gtt_bst, isc->gtt_bsh, isc->gtt_size); 554 isc->gtt_size = 0; 555 fail4: 556 #if notyet 557 agp_i810_fini(sc); 558 #endif 559 fail3: switch (isc->chiptype) { 560 case CHIP_I915: 561 case CHIP_I965: 562 case CHIP_G33: 563 case CHIP_G4X: 564 agp_i810_teardown_chipset_flush_page(sc); 565 break; 566 } 567 fail2: bus_space_unmap(isc->bst, isc->bsh, isc->size); 568 isc->size = 0; 569 fail1: free(isc, M_AGP); 570 sc->as_chipc = NULL; 571 fail0: agp_generic_detach(sc); 572 KASSERT(error); 573 return error; 574 } 575 576 static int 577 agp_i810_setup_chipset_flush_page(struct agp_softc *sc) 578 { 579 struct agp_i810_softc *const isc = sc->as_chipc; 580 const pci_chipset_tag_t pc = sc->as_pc; 581 const pcitag_t tag = sc->as_tag; 582 pcireg_t lo, hi; 583 bus_addr_t addr, minaddr, maxaddr; 584 int error; 585 586 /* We always use memory-mapped I/O. */ 587 isc->flush_bst = isc->vga_pa.pa_memt; 588 589 /* No page allocated yet. */ 590 isc->flush_addr = 0; 591 592 /* Read the PCI config register: 4-byte on gen3, 8-byte on gen>=4. */ 593 if (isc->chiptype == CHIP_I915) { 594 addr = pci_conf_read(pc, tag, AGP_I915_IFPADDR); 595 minaddr = PAGE_SIZE; /* XXX PCIBIOS_MIN_MEM? */ 596 maxaddr = UINT32_MAX; 597 } else { 598 hi = pci_conf_read(pc, tag, AGP_I965_IFPADDR+4); 599 lo = pci_conf_read(pc, tag, AGP_I965_IFPADDR); 600 /* 601 * Convert to uint64_t, rather than bus_addr_t which 602 * may be 32-bit, to avoid undefined behaviour with a 603 * too-wide shift. Since the BIOS doesn't know whether 604 * the OS will run 64-bit or with PAE, it ought to 605 * configure at most a 32-bit physical address, so 606 * let's print a warning in case that happens. 607 */ 608 addr = ((uint64_t)hi << 32) | lo; 609 if (hi) { 610 aprint_error_dev(sc->as_dev, 611 "BIOS configured >32-bit flush page address" 612 ": %"PRIx64"\n", ((uint64_t)hi << 32) | lo); 613 #if __i386__ && !PAE 614 return EIO; 615 #endif 616 } 617 minaddr = PAGE_SIZE; /* XXX PCIBIOS_MIN_MEM? */ 618 maxaddr = MIN(UINT64_MAX, ~(bus_addr_t)0); 619 } 620 621 /* Allocate or map a pre-allocated a page for it. */ 622 if (ISSET(addr, 1)) { 623 /* BIOS allocated it for us. Use that. */ 624 error = bus_space_map(isc->flush_bst, addr & ~1, PAGE_SIZE, 0, 625 &isc->flush_bsh); 626 if (error) 627 return error; 628 } else { 629 /* None allocated. Allocate one. */ 630 error = bus_space_alloc(isc->flush_bst, minaddr, maxaddr, 631 PAGE_SIZE, PAGE_SIZE, 0, 0, 632 &isc->flush_addr, &isc->flush_bsh); 633 if (error) 634 return error; 635 KASSERT(isc->flush_addr != 0); 636 /* Write it into the PCI config register. */ 637 addr = isc->flush_addr | 1; 638 if (isc->chiptype == CHIP_I915) { 639 pci_conf_write(pc, tag, AGP_I915_IFPADDR, addr); 640 } else { 641 hi = __SHIFTOUT(addr, __BITS(63, 32)); 642 lo = __SHIFTOUT(addr, __BITS(31, 0)); 643 pci_conf_write(pc, tag, AGP_I965_IFPADDR+4, hi); 644 pci_conf_write(pc, tag, AGP_I965_IFPADDR, lo); 645 } 646 } 647 648 /* Success! */ 649 return 0; 650 } 651 652 static void 653 agp_i810_teardown_chipset_flush_page(struct agp_softc *sc) 654 { 655 struct agp_i810_softc *const isc = sc->as_chipc; 656 657 if (isc->flush_addr) { 658 /* If we allocated a page, clear it. */ 659 if (isc->chiptype == CHIP_I915) { 660 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR, 661 0); 662 } else { 663 pci_conf_write(sc->as_pc, sc->as_tag, 664 AGP_I965_IFPADDR, 0); 665 pci_conf_write(sc->as_pc, sc->as_tag, 666 AGP_I965_IFPADDR + 4, 0); 667 } 668 isc->flush_addr = 0; 669 bus_space_free(isc->flush_bst, isc->flush_bsh, 670 PAGE_SIZE); 671 } else { 672 /* Otherwise, just unmap the pre-allocated page. */ 673 bus_space_unmap(isc->flush_bst, isc->flush_bsh, PAGE_SIZE); 674 } 675 } 676 677 /* 678 * XXX horrible hack to allow drm code to use our mapping 679 * of VGA chip registers 680 */ 681 int 682 agp_i810_borrow(bus_addr_t base, bus_size_t size, bus_space_handle_t *hdlp) 683 { 684 685 if (agp_i810_vga_regbase == 0) 686 return 0; 687 if (base < agp_i810_vga_regbase) 688 return 0; 689 if (agp_i810_vga_regsize < size) 690 return 0; 691 if ((base - agp_i810_vga_regbase) > (agp_i810_vga_regsize - size)) 692 return 0; 693 if (bus_space_subregion(agp_i810_vga_bst, agp_i810_vga_bsh, 694 (base - agp_i810_vga_regbase), (agp_i810_vga_regsize - size), 695 hdlp)) 696 return 0; 697 return 1; 698 } 699 700 static int 701 agp_i810_init(struct agp_softc *sc) 702 { 703 struct agp_i810_softc *isc; 704 int error; 705 706 isc = sc->as_chipc; 707 708 if (isc->chiptype == CHIP_I810) { 709 struct agp_gatt *gatt; 710 void *virtual; 711 int dummyseg; 712 713 /* Some i810s have on-chip memory called dcache */ 714 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 715 isc->dcache_size = 4 * 1024 * 1024; 716 else 717 isc->dcache_size = 0; 718 719 /* According to the specs the gatt on the i810 must be 64k */ 720 isc->gtt_size = 64 * 1024; 721 gatt = malloc(sizeof(*gatt), M_AGP, M_NOWAIT); 722 if (gatt == NULL) { 723 aprint_error_dev(sc->as_dev, 724 "can't malloc GATT record\n"); 725 error = ENOMEM; 726 goto fail0; 727 } 728 gatt->ag_entries = isc->gtt_size / sizeof(uint32_t); 729 error = agp_alloc_dmamem(sc->as_dmat, isc->gtt_size, 730 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical, 731 &gatt->ag_dmaseg, 1, &dummyseg); 732 if (error) { 733 aprint_error_dev(sc->as_dev, 734 "can't allocate memory for GTT: %d\n", error); 735 free(gatt, M_AGP); 736 goto fail0; 737 } 738 739 gatt->ag_virtual = (uint32_t *)virtual; 740 gatt->ag_size = gatt->ag_entries * sizeof(uint32_t); 741 memset(gatt->ag_virtual, 0, gatt->ag_size); 742 agp_flush_cache(); 743 744 /* Install the GATT. */ 745 isc->pgtblctl = gatt->ag_physical | 1; 746 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 747 isc->gatt = gatt; 748 } else if (isc->chiptype == CHIP_I830) { 749 /* The i830 automatically initializes the 128k gatt on boot. */ 750 /* XXX [citation needed] */ 751 pcireg_t reg; 752 u_int16_t gcc1; 753 754 isc->gtt_size = 128 * 1024; 755 756 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 757 gcc1 = (u_int16_t)(reg >> 16); 758 switch (gcc1 & AGP_I830_GCC1_GMS) { 759 case AGP_I830_GCC1_GMS_STOLEN_512: 760 isc->stolen = (512 - 132) * 1024 / 4096; 761 break; 762 case AGP_I830_GCC1_GMS_STOLEN_1024: 763 isc->stolen = (1024 - 132) * 1024 / 4096; 764 break; 765 case AGP_I830_GCC1_GMS_STOLEN_8192: 766 isc->stolen = (8192 - 132) * 1024 / 4096; 767 break; 768 default: 769 isc->stolen = 0; 770 aprint_error_dev(sc->as_dev, 771 "unknown memory configuration, disabling\n"); 772 error = ENXIO; 773 goto fail0; 774 } 775 776 if (isc->stolen > 0) { 777 aprint_normal_dev(sc->as_dev, 778 "detected %dk stolen memory\n", 779 isc->stolen * 4); 780 } 781 782 /* GATT address is already in there, make sure it's enabled */ 783 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 784 isc->pgtblctl |= 1; 785 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 786 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 787 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 || 788 isc->chiptype == CHIP_G4X) { 789 pcireg_t reg; 790 u_int32_t gtt_size, stolen; /* XXX kilobytes */ 791 u_int16_t gcc1; 792 793 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1); 794 gcc1 = (u_int16_t)(reg >> 16); 795 796 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 797 798 /* Stolen memory is set up at the beginning of the aperture by 799 * the BIOS, consisting of the GATT followed by 4kb for the 800 * BIOS display. 801 */ 802 switch (isc->chiptype) { 803 case CHIP_I855: 804 gtt_size = 128; 805 break; 806 case CHIP_I915: 807 gtt_size = 256; 808 break; 809 case CHIP_I965: 810 switch (isc->pgtblctl & AGP_I810_PGTBL_SIZE_MASK) { 811 case AGP_I810_PGTBL_SIZE_128KB: 812 case AGP_I810_PGTBL_SIZE_512KB: 813 gtt_size = 512; 814 break; 815 case AGP_I965_PGTBL_SIZE_1MB: 816 gtt_size = 1024; 817 break; 818 case AGP_I965_PGTBL_SIZE_2MB: 819 gtt_size = 2048; 820 break; 821 case AGP_I965_PGTBL_SIZE_1_5MB: 822 gtt_size = 1024 + 512; 823 break; 824 default: 825 aprint_error_dev(sc->as_dev, 826 "bad PGTBL size\n"); 827 error = ENXIO; 828 goto fail0; 829 } 830 break; 831 case CHIP_G33: 832 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 833 case AGP_G33_PGTBL_SIZE_1M: 834 gtt_size = 1024; 835 break; 836 case AGP_G33_PGTBL_SIZE_2M: 837 gtt_size = 2048; 838 break; 839 default: 840 aprint_error_dev(sc->as_dev, 841 "bad PGTBL size\n"); 842 error = ENXIO; 843 goto fail0; 844 } 845 break; 846 case CHIP_G4X: 847 switch (isc->pgtblctl & AGP_G4X_PGTBL_SIZE_MASK) { 848 case AGP_G4X_PGTBL_SIZE_512K: 849 gtt_size = 512; 850 break; 851 case AGP_G4X_PGTBL_SIZE_256K: 852 gtt_size = 256; 853 break; 854 case AGP_G4X_PGTBL_SIZE_128K: 855 gtt_size = 128; 856 break; 857 case AGP_G4X_PGTBL_SIZE_1M: 858 gtt_size = 1*1024; 859 break; 860 case AGP_G4X_PGTBL_SIZE_2M: 861 gtt_size = 2*1024; 862 break; 863 case AGP_G4X_PGTBL_SIZE_1_5M: 864 gtt_size = 1*1024 + 512; 865 break; 866 default: 867 aprint_error_dev(sc->as_dev, 868 "bad PGTBL size\n"); 869 error = ENXIO; 870 goto fail0; 871 } 872 break; 873 default: 874 panic("impossible chiptype %d", isc->chiptype); 875 } 876 877 /* 878 * XXX If I'm reading the datasheets right, this stolen 879 * memory detection logic is totally wrong. 880 */ 881 switch (gcc1 & AGP_I855_GCC1_GMS) { 882 case AGP_I855_GCC1_GMS_STOLEN_1M: 883 stolen = 1024; 884 break; 885 case AGP_I855_GCC1_GMS_STOLEN_4M: 886 stolen = 4 * 1024; 887 break; 888 case AGP_I855_GCC1_GMS_STOLEN_8M: 889 stolen = 8 * 1024; 890 break; 891 case AGP_I855_GCC1_GMS_STOLEN_16M: 892 stolen = 16 * 1024; 893 break; 894 case AGP_I855_GCC1_GMS_STOLEN_32M: 895 stolen = 32 * 1024; 896 break; 897 case AGP_I915_GCC1_GMS_STOLEN_48M: 898 stolen = 48 * 1024; 899 break; 900 case AGP_I915_GCC1_GMS_STOLEN_64M: 901 stolen = 64 * 1024; 902 break; 903 case AGP_G33_GCC1_GMS_STOLEN_128M: 904 stolen = 128 * 1024; 905 break; 906 case AGP_G33_GCC1_GMS_STOLEN_256M: 907 stolen = 256 * 1024; 908 break; 909 case AGP_G4X_GCC1_GMS_STOLEN_96M: 910 stolen = 96 * 1024; 911 break; 912 case AGP_G4X_GCC1_GMS_STOLEN_160M: 913 stolen = 160 * 1024; 914 break; 915 case AGP_G4X_GCC1_GMS_STOLEN_224M: 916 stolen = 224 * 1024; 917 break; 918 case AGP_G4X_GCC1_GMS_STOLEN_352M: 919 stolen = 352 * 1024; 920 break; 921 default: 922 aprint_error_dev(sc->as_dev, 923 "unknown memory configuration, disabling\n"); 924 error = ENXIO; 925 goto fail0; 926 } 927 928 switch (gcc1 & AGP_I855_GCC1_GMS) { 929 case AGP_I915_GCC1_GMS_STOLEN_48M: 930 case AGP_I915_GCC1_GMS_STOLEN_64M: 931 if (isc->chiptype != CHIP_I915 && 932 isc->chiptype != CHIP_I965 && 933 isc->chiptype != CHIP_G33 && 934 isc->chiptype != CHIP_G4X) 935 stolen = 0; 936 break; 937 case AGP_G33_GCC1_GMS_STOLEN_128M: 938 case AGP_G33_GCC1_GMS_STOLEN_256M: 939 if (isc->chiptype != CHIP_I965 && 940 isc->chiptype != CHIP_G33 && 941 isc->chiptype != CHIP_G4X) 942 stolen = 0; 943 break; 944 case AGP_G4X_GCC1_GMS_STOLEN_96M: 945 case AGP_G4X_GCC1_GMS_STOLEN_160M: 946 case AGP_G4X_GCC1_GMS_STOLEN_224M: 947 case AGP_G4X_GCC1_GMS_STOLEN_352M: 948 if (isc->chiptype != CHIP_I965 && 949 isc->chiptype != CHIP_G4X) 950 stolen = 0; 951 break; 952 } 953 954 isc->gtt_size = gtt_size * 1024; 955 956 /* BIOS space */ 957 /* XXX [citation needed] */ 958 gtt_size += 4; 959 960 /* XXX [citation needed] for this subtraction */ 961 isc->stolen = (stolen - gtt_size) * 1024 / 4096; 962 963 if (isc->stolen > 0) { 964 aprint_normal_dev(sc->as_dev, 965 "detected %dk stolen memory\n", 966 isc->stolen * 4); 967 } 968 969 /* GATT address is already in there, make sure it's enabled */ 970 isc->pgtblctl |= 1; 971 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 972 } 973 974 /* 975 * Make sure the chipset can see everything. 976 */ 977 agp_flush_cache(); 978 979 /* 980 * Publish what we found for kludgey drivers (I'm looking at 981 * you, drm). 982 */ 983 if (agp_i810_sc == NULL) 984 agp_i810_sc = sc; 985 else 986 aprint_error_dev(sc->as_dev, "agp already attached\n"); 987 988 /* Success! */ 989 return 0; 990 991 fail0: KASSERT(error); 992 return error; 993 } 994 995 #if 0 996 static int 997 agp_i810_detach(struct agp_softc *sc) 998 { 999 int error; 1000 struct agp_i810_softc *isc = sc->as_chipc; 1001 1002 error = agp_generic_detach(sc); 1003 if (error) 1004 return error; 1005 1006 switch (isc->chiptype) { 1007 case CHIP_I915: 1008 case CHIP_I965: 1009 case CHIP_G33: 1010 case CHIP_G4X: 1011 agp_i810_teardown_chipset_flush_page(sc); 1012 break; 1013 } 1014 1015 /* Clear the GATT base. */ 1016 if (sc->chiptype == CHIP_I810) { 1017 WRITE4(AGP_I810_PGTBL_CTL, 0); 1018 } else { 1019 unsigned int pgtblctl; 1020 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 1021 pgtblctl &= ~1; 1022 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 1023 } 1024 1025 if (sc->chiptype == CHIP_I810) { 1026 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap, 1027 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 1028 free(isc->gatt, M_AGP); 1029 } 1030 1031 return 0; 1032 } 1033 #endif 1034 1035 static u_int32_t 1036 agp_i810_get_aperture(struct agp_softc *sc) 1037 { 1038 struct agp_i810_softc *isc = sc->as_chipc; 1039 pcireg_t reg; 1040 u_int32_t size; 1041 u_int16_t miscc, gcc1; 1042 1043 size = 0; 1044 1045 switch (isc->chiptype) { 1046 case CHIP_I810: 1047 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 1048 miscc = (u_int16_t)(reg >> 16); 1049 if ((miscc & AGP_I810_MISCC_WINSIZE) == 1050 AGP_I810_MISCC_WINSIZE_32) 1051 size = 32 * 1024 * 1024; 1052 else 1053 size = 64 * 1024 * 1024; 1054 break; 1055 case CHIP_I830: 1056 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 1057 gcc1 = (u_int16_t)(reg >> 16); 1058 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 1059 size = 64 * 1024 * 1024; 1060 else 1061 size = 128 * 1024 * 1024; 1062 break; 1063 case CHIP_I855: 1064 size = 128 * 1024 * 1024; 1065 break; 1066 case CHIP_I915: 1067 case CHIP_G33: 1068 case CHIP_G4X: 1069 size = sc->as_apsize; 1070 break; 1071 case CHIP_I965: 1072 size = 512 * 1024 * 1024; 1073 break; 1074 default: 1075 aprint_error(": Unknown chipset\n"); 1076 } 1077 1078 return size; 1079 } 1080 1081 static int 1082 agp_i810_set_aperture(struct agp_softc *sc __unused, 1083 uint32_t aperture __unused) 1084 { 1085 1086 return ENOSYS; 1087 } 1088 1089 static int 1090 agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 1091 { 1092 struct agp_i810_softc *isc = sc->as_chipc; 1093 1094 if (offset < 0 || offset >= ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) { 1095 #ifdef AGP_DEBUG 1096 printf("%s: failed" 1097 ": offset 0x%08x, shift %d, entries %"PRIuMAX"\n", 1098 device_xname(sc->as_dev), (int)offset, AGP_PAGE_SHIFT, 1099 (uintmax_t)isc->gtt_size/4); 1100 #endif 1101 return EINVAL; 1102 } 1103 1104 if (isc->chiptype != CHIP_I810) { 1105 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1106 #ifdef AGP_DEBUG 1107 printf("%s: trying to bind into stolen memory\n", 1108 device_xname(sc->as_dev)); 1109 #endif 1110 return EINVAL; 1111 } 1112 } 1113 1114 return agp_i810_write_gtt_entry(isc, offset, physical | 1); 1115 } 1116 1117 static int 1118 agp_i810_unbind_page(struct agp_softc *sc, off_t offset) 1119 { 1120 struct agp_i810_softc *isc = sc->as_chipc; 1121 1122 if (offset < 0 || offset >= ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) 1123 return EINVAL; 1124 1125 if (isc->chiptype != CHIP_I810 ) { 1126 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1127 #ifdef AGP_DEBUG 1128 printf("%s: trying to unbind from stolen memory\n", 1129 device_xname(sc->as_dev)); 1130 #endif 1131 return EINVAL; 1132 } 1133 } 1134 1135 return agp_i810_write_gtt_entry(isc, offset, 0); 1136 } 1137 1138 /* 1139 * Writing via memory mapped registers already flushes all TLBs. 1140 */ 1141 static void 1142 agp_i810_flush_tlb(struct agp_softc *sc) 1143 { 1144 } 1145 1146 static int 1147 agp_i810_enable(struct agp_softc *sc, u_int32_t mode) 1148 { 1149 1150 return 0; 1151 } 1152 1153 #define AGP_I810_MEMTYPE_MAIN 0 1154 #define AGP_I810_MEMTYPE_DCACHE 1 1155 #define AGP_I810_MEMTYPE_HWCURSOR 2 1156 1157 static struct agp_memory * 1158 agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size) 1159 { 1160 struct agp_i810_softc *isc = sc->as_chipc; 1161 struct agp_memory *mem; 1162 int error; 1163 1164 #ifdef AGP_DEBUG 1165 printf("AGP: alloc(%d, 0x%x)\n", type, (int) size); 1166 #endif 1167 1168 if (size <= 0) 1169 return NULL; 1170 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 1171 return NULL; 1172 KASSERT(sc->as_allocated <= sc->as_maxmem); 1173 if (size > (sc->as_maxmem - sc->as_allocated)) 1174 return NULL; 1175 if (size > ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) 1176 return NULL; 1177 1178 switch (type) { 1179 case AGP_I810_MEMTYPE_MAIN: 1180 break; 1181 case AGP_I810_MEMTYPE_DCACHE: 1182 if (isc->chiptype != CHIP_I810) 1183 return NULL; 1184 if (size != isc->dcache_size) 1185 return NULL; 1186 break; 1187 case AGP_I810_MEMTYPE_HWCURSOR: 1188 if ((size != AGP_PAGE_SIZE) && 1189 (size != AGP_PAGE_SIZE*4)) 1190 return NULL; 1191 break; 1192 default: 1193 return NULL; 1194 } 1195 1196 mem = malloc(sizeof(*mem), M_AGP, M_WAITOK|M_ZERO); 1197 if (mem == NULL) 1198 goto fail0; 1199 mem->am_id = sc->as_nextid++; 1200 mem->am_size = size; 1201 mem->am_type = type; 1202 1203 switch (type) { 1204 case AGP_I810_MEMTYPE_MAIN: 1205 error = bus_dmamap_create(sc->as_dmat, size, 1206 (size >> AGP_PAGE_SHIFT) + 1, size, 0, BUS_DMA_WAITOK, 1207 &mem->am_dmamap); 1208 if (error) 1209 goto fail1; 1210 break; 1211 case AGP_I810_MEMTYPE_DCACHE: 1212 break; 1213 case AGP_I810_MEMTYPE_HWCURSOR: 1214 mem->am_dmaseg = malloc(sizeof(*mem->am_dmaseg), M_AGP, 1215 M_WAITOK); 1216 error = agp_alloc_dmamem(sc->as_dmat, size, 0, &mem->am_dmamap, 1217 &mem->am_virtual, &mem->am_physical, mem->am_dmaseg, 1, 1218 &mem->am_nseg); 1219 if (error) { 1220 free(mem->am_dmaseg, M_AGP); 1221 goto fail1; 1222 } 1223 (void)memset(mem->am_virtual, 0, size); 1224 break; 1225 default: 1226 panic("invalid agp memory type: %d", type); 1227 } 1228 1229 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link); 1230 sc->as_allocated += size; 1231 1232 return mem; 1233 1234 fail1: free(mem, M_AGP); 1235 fail0: return NULL; 1236 } 1237 1238 static int 1239 agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem) 1240 { 1241 1242 if (mem->am_is_bound) 1243 return EBUSY; 1244 1245 switch (mem->am_type) { 1246 case AGP_I810_MEMTYPE_MAIN: 1247 bus_dmamap_destroy(sc->as_dmat, mem->am_dmamap); 1248 break; 1249 case AGP_I810_MEMTYPE_DCACHE: 1250 break; 1251 case AGP_I810_MEMTYPE_HWCURSOR: 1252 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap, 1253 mem->am_virtual, mem->am_dmaseg, mem->am_nseg); 1254 free(mem->am_dmaseg, M_AGP); 1255 break; 1256 default: 1257 panic("invalid agp i810 memory type: %d", mem->am_type); 1258 } 1259 1260 sc->as_allocated -= mem->am_size; 1261 TAILQ_REMOVE(&sc->as_memory, mem, am_link); 1262 free(mem, M_AGP); 1263 1264 return 0; 1265 } 1266 1267 static int 1268 agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem, 1269 off_t offset) 1270 { 1271 struct agp_i810_softc *isc = sc->as_chipc; 1272 uint32_t pgtblctl; 1273 int error; 1274 1275 if (mem->am_is_bound) 1276 return EINVAL; 1277 1278 /* 1279 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 1280 * X server for mysterious reasons which leads to crashes if we write 1281 * to the GTT through the MMIO window. 1282 * Until the issue is solved, simply restore it. 1283 */ 1284 pgtblctl = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL); 1285 if (pgtblctl != isc->pgtblctl) { 1286 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%"PRIx32 1287 " - fixing\n", pgtblctl); 1288 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 1289 isc->pgtblctl); 1290 } 1291 1292 switch (mem->am_type) { 1293 case AGP_I810_MEMTYPE_MAIN: 1294 return agp_generic_bind_memory_bounded(sc, mem, offset, 1295 0, (isc->gtt_size/4) << AGP_PAGE_SHIFT); 1296 case AGP_I810_MEMTYPE_DCACHE: 1297 error = agp_i810_bind_memory_dcache(sc, mem, offset); 1298 break; 1299 case AGP_I810_MEMTYPE_HWCURSOR: 1300 error = agp_i810_bind_memory_hwcursor(sc, mem, offset); 1301 break; 1302 default: 1303 panic("invalid agp i810 memory type: %d", mem->am_type); 1304 } 1305 if (error) 1306 return error; 1307 1308 /* Success! */ 1309 mem->am_is_bound = 1; 1310 return 0; 1311 } 1312 1313 #define I810_GTT_PTE_VALID 0x01 1314 #define I810_GTT_PTE_DCACHE 0x02 1315 1316 static int 1317 agp_i810_bind_memory_dcache(struct agp_softc *sc, struct agp_memory *mem, 1318 off_t offset) 1319 { 1320 struct agp_i810_softc *const isc __diagused = sc->as_chipc; 1321 uint32_t i, j; 1322 int error; 1323 1324 KASSERT(isc->chiptype == CHIP_I810); 1325 1326 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0); 1327 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 1328 /* XXX No offset? */ 1329 error = agp_i810_write_gtt_entry(isc, i, 1330 i | I810_GTT_PTE_VALID | I810_GTT_PTE_DCACHE); 1331 if (error) 1332 goto fail0; 1333 } 1334 1335 /* Success! */ 1336 return 0; 1337 1338 fail0: for (j = 0; j < i; j += AGP_PAGE_SIZE) 1339 (void)agp_i810_unbind_page(sc, offset + j); 1340 return error; 1341 } 1342 1343 static int 1344 agp_i810_bind_memory_hwcursor(struct agp_softc *sc, struct agp_memory *mem, 1345 off_t offset) 1346 { 1347 const bus_addr_t pa = mem->am_physical; 1348 uint32_t i, j; 1349 int error; 1350 1351 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0); 1352 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 1353 error = agp_i810_bind_page(sc, offset + i, pa + i); 1354 if (error) 1355 goto fail0; 1356 } 1357 1358 /* Success! */ 1359 mem->am_offset = offset; 1360 return 0; 1361 1362 fail0: for (j = 0; j < i; j += AGP_PAGE_SIZE) 1363 (void)agp_i810_unbind_page(sc, offset + j); 1364 return error; 1365 } 1366 1367 static int 1368 agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem) 1369 { 1370 struct agp_i810_softc *isc = sc->as_chipc; 1371 u_int32_t i; 1372 1373 if (!mem->am_is_bound) 1374 return EINVAL; 1375 1376 switch (mem->am_type) { 1377 case AGP_I810_MEMTYPE_MAIN: 1378 return agp_generic_unbind_memory(sc, mem); 1379 case AGP_I810_MEMTYPE_DCACHE: 1380 KASSERT(isc->chiptype == CHIP_I810); 1381 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1382 (void)agp_i810_write_gtt_entry(isc, i, 0); 1383 break; 1384 case AGP_I810_MEMTYPE_HWCURSOR: 1385 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1386 (void)agp_i810_unbind_page(sc, mem->am_offset + i); 1387 mem->am_offset = 0; 1388 break; 1389 default: 1390 panic("invalid agp i810 memory type: %d", mem->am_type); 1391 } 1392 1393 mem->am_is_bound = 0; 1394 return 0; 1395 } 1396 1397 static bool 1398 agp_i810_resume(device_t dv, const pmf_qual_t *qual) 1399 { 1400 struct agp_softc *sc = device_private(dv); 1401 struct agp_i810_softc *isc = sc->as_chipc; 1402 1403 /* 1404 * XXX Nothing uses this! Save on suspend, restore on resume? 1405 */ 1406 isc->pgtblctl_resume_hack = READ4(AGP_I810_PGTBL_CTL); 1407 agp_flush_cache(); 1408 1409 return true; 1410 } 1411
Indexes created Sat Sep 27 14:09:57 GMT 2025