agp_i810.c revision 1.111
1 /* $NetBSD: agp_i810.c,v 1.111 2014/07/23 14:50:23 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.111 2014/07/23 14:50:23 riastradh Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/proc.h> 40 #include <sys/device.h> 41 #include <sys/conf.h> 42 #include <sys/xcall.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcidevs.h> 47 #include <dev/pci/agpvar.h> 48 #include <dev/pci/agpreg.h> 49 #include <dev/pci/agp_i810var.h> 50 51 #include <sys/agpio.h> 52 53 #include <sys/bus.h> 54 55 #include "agp_intel.h" 56 57 #ifdef AGP_DEBUG 58 #define DPRINTF(sc, fmt, ...) \ 59 device_printf((sc)->as_dev, "%s: " fmt, __func__, ##__VA_ARGS__) 60 #else 61 #define DPRINTF(sc, fmt, ...) do {} while (0) 62 #endif 63 64 struct agp_softc *agp_i810_sc = NULL; 65 66 #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off) 67 #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off) 68 #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v) 69 70 #define CHIP_I810 0 /* i810/i815 */ 71 #define CHIP_I830 1 /* 830M/845G */ 72 #define CHIP_I855 2 /* 852GM/855GM/865G */ 73 #define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */ 74 #define CHIP_I965 4 /* 965Q/965PM */ 75 #define CHIP_G33 5 /* G33/Q33/Q35 */ 76 #define CHIP_G4X 6 /* G45/Q45 */ 77 78 /* XXX hack, see below */ 79 static bus_addr_t agp_i810_vga_regbase; 80 static bus_size_t agp_i810_vga_regsize; 81 static bus_space_tag_t agp_i810_vga_bst; 82 static bus_space_handle_t agp_i810_vga_bsh; 83 84 static u_int32_t agp_i810_get_aperture(struct agp_softc *); 85 static int agp_i810_set_aperture(struct agp_softc *, u_int32_t); 86 static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t); 87 static int agp_i810_unbind_page(struct agp_softc *, off_t); 88 static void agp_i810_flush_tlb(struct agp_softc *); 89 static int agp_i810_enable(struct agp_softc *, u_int32_t mode); 90 static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int, 91 vsize_t); 92 static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *); 93 static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, 94 off_t); 95 static int agp_i810_bind_memory_dcache(struct agp_softc *, struct agp_memory *, 96 off_t); 97 static int agp_i810_bind_memory_hwcursor(struct agp_softc *, 98 struct agp_memory *, off_t); 99 static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *); 100 101 static bool agp_i810_resume(device_t, const pmf_qual_t *); 102 static int agp_i810_init(struct agp_softc *); 103 104 static int agp_i810_setup_chipset_flush_page(struct agp_softc *); 105 static void agp_i810_teardown_chipset_flush_page(struct agp_softc *); 106 static int agp_i810_init(struct agp_softc *); 107 108 static struct agp_methods agp_i810_methods = { 109 agp_i810_get_aperture, 110 agp_i810_set_aperture, 111 agp_i810_bind_page, 112 agp_i810_unbind_page, 113 agp_i810_flush_tlb, 114 agp_i810_enable, 115 agp_i810_alloc_memory, 116 agp_i810_free_memory, 117 agp_i810_bind_memory, 118 agp_i810_unbind_memory, 119 }; 120 121 int 122 agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, bus_addr_t v) 123 { 124 u_int32_t pte; 125 126 /* Bits 11:4 (physical start address extension) should be zero. */ 127 if ((v & 0xff0) != 0) 128 return EINVAL; 129 130 pte = (u_int32_t)v; 131 /* 132 * We need to massage the pte if bus_addr_t is wider than 32 bits. 133 * The compiler isn't smart enough, hence the casts to uintmax_t. 134 */ 135 if (sizeof(bus_addr_t) > sizeof(u_int32_t)) { 136 /* 965+ can do 36-bit addressing, add in the extra bits. */ 137 if (isc->chiptype == CHIP_I965 || 138 isc->chiptype == CHIP_G33 || 139 isc->chiptype == CHIP_G4X) { 140 if (((uintmax_t)v >> 36) != 0) 141 return EINVAL; 142 pte |= (v >> 28) & 0xf0; 143 } else { 144 if (((uintmax_t)v >> 32) != 0) 145 return EINVAL; 146 } 147 } 148 149 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, 150 4*(off >> AGP_PAGE_SHIFT), pte); 151 152 return 0; 153 } 154 155 void 156 agp_i810_post_gtt_entry(struct agp_i810_softc *isc, off_t off) 157 { 158 159 (void)bus_space_read_4(isc->gtt_bst, isc->gtt_bsh, 160 4*(off >> AGP_PAGE_SHIFT)); 161 } 162 163 static void 164 agp_flush_cache_xc(void *a __unused, void *b __unused) 165 { 166 167 agp_flush_cache(); 168 } 169 170 void 171 agp_i810_chipset_flush(struct agp_i810_softc *isc) 172 { 173 unsigned int timo = 20000; /* * 50 us = 1 s */ 174 175 switch (isc->chiptype) { 176 case CHIP_I810: 177 break; 178 case CHIP_I830: 179 case CHIP_I855: 180 /* 181 * Flush all CPU caches. If we're cold, we can't run 182 * xcalls, but there should be only one CPU up, so 183 * flushing only the local CPU's cache should suffice. 184 * 185 * XXX Come to think of it, do these chipsets appear in 186 * any multi-CPU systems? 187 */ 188 if (cold) 189 agp_flush_cache(); 190 else 191 xc_wait(xc_broadcast(0, &agp_flush_cache_xc, 192 NULL, NULL)); 193 WRITE4(AGP_I830_HIC, READ4(AGP_I830_HIC) | __BIT(31)); 194 while (ISSET(READ4(AGP_I830_HIC), __BIT(31))) { 195 if (timo-- == 0) 196 break; 197 DELAY(50); 198 } 199 break; 200 case CHIP_I915: 201 case CHIP_I965: 202 case CHIP_G33: 203 case CHIP_G4X: 204 bus_space_write_4(isc->flush_bst, isc->flush_bsh, 0, 1); 205 break; 206 } 207 } 208 209 /* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */ 210 static int 211 agp_i810_vgamatch(const struct pci_attach_args *pa) 212 { 213 214 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 215 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 216 return (0); 217 218 switch (PCI_PRODUCT(pa->pa_id)) { 219 case PCI_PRODUCT_INTEL_82810_GC: 220 case PCI_PRODUCT_INTEL_82810_DC100_GC: 221 case PCI_PRODUCT_INTEL_82810E_GC: 222 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 223 case PCI_PRODUCT_INTEL_82830MP_IV: 224 case PCI_PRODUCT_INTEL_82845G_IGD: 225 case PCI_PRODUCT_INTEL_82855GM_IGD: 226 case PCI_PRODUCT_INTEL_82865_IGD: 227 case PCI_PRODUCT_INTEL_82915G_IGD: 228 case PCI_PRODUCT_INTEL_82915GM_IGD: 229 case PCI_PRODUCT_INTEL_82945P_IGD: 230 case PCI_PRODUCT_INTEL_82945GM_IGD: 231 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 232 case PCI_PRODUCT_INTEL_82945GME_IGD: 233 case PCI_PRODUCT_INTEL_E7221_IGD: 234 case PCI_PRODUCT_INTEL_82965Q_IGD: 235 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 236 case PCI_PRODUCT_INTEL_82965PM_IGD: 237 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 238 case PCI_PRODUCT_INTEL_82G33_IGD: 239 case PCI_PRODUCT_INTEL_82G33_IGD_1: 240 case PCI_PRODUCT_INTEL_82965G_IGD: 241 case PCI_PRODUCT_INTEL_82965G_IGD_1: 242 case PCI_PRODUCT_INTEL_82965GME_IGD: 243 case PCI_PRODUCT_INTEL_82Q35_IGD: 244 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 245 case PCI_PRODUCT_INTEL_82Q33_IGD: 246 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 247 case PCI_PRODUCT_INTEL_82G35_IGD: 248 case PCI_PRODUCT_INTEL_82G35_IGD_1: 249 case PCI_PRODUCT_INTEL_82946GZ_IGD: 250 case PCI_PRODUCT_INTEL_82GM45_IGD: 251 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 252 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 253 case PCI_PRODUCT_INTEL_82Q45_IGD: 254 case PCI_PRODUCT_INTEL_82G45_IGD: 255 case PCI_PRODUCT_INTEL_82G41_IGD: 256 case PCI_PRODUCT_INTEL_82B43_IGD: 257 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 258 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 259 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 260 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 261 return (1); 262 } 263 264 return (0); 265 } 266 267 static int 268 agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg) 269 { 270 /* 271 * Find the aperture. Don't map it (yet), this would 272 * eat KVA. 273 */ 274 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 275 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize, 276 &sc->as_apflags) != 0) 277 return ENXIO; 278 279 sc->as_apt = pa->pa_memt; 280 281 return 0; 282 } 283 284 int 285 agp_i810_attach(device_t parent, device_t self, void *aux) 286 { 287 struct agp_softc *sc = device_private(self); 288 struct agp_i810_softc *isc; 289 int apbase, mmadr_bar, gtt_bar; 290 int mmadr_type, mmadr_flags; 291 bus_addr_t mmadr; 292 bus_size_t mmadr_size, gtt_off; 293 int error; 294 295 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 296 if (isc == NULL) { 297 aprint_error(": can't allocate chipset-specific softc\n"); 298 error = ENOMEM; 299 goto fail0; 300 } 301 sc->as_chipc = isc; 302 sc->as_methods = &agp_i810_methods; 303 304 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) { 305 #if NAGP_INTEL > 0 306 const struct pci_attach_args *pa = aux; 307 308 switch (PCI_PRODUCT(pa->pa_id)) { 309 case PCI_PRODUCT_INTEL_82840_HB: 310 case PCI_PRODUCT_INTEL_82865_HB: 311 case PCI_PRODUCT_INTEL_82845G_DRAM: 312 case PCI_PRODUCT_INTEL_82815_FULL_HUB: 313 case PCI_PRODUCT_INTEL_82855GM_MCH: 314 free(isc, M_AGP); 315 return agp_intel_attach(parent, self, aux); 316 } 317 #endif 318 aprint_error(": can't find internal VGA" 319 " config space\n"); 320 error = ENOENT; 321 goto fail1; 322 } 323 324 /* XXXfvdl */ 325 sc->as_dmat = isc->vga_pa.pa_dmat; 326 327 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 328 case PCI_PRODUCT_INTEL_82810_GC: 329 case PCI_PRODUCT_INTEL_82810_DC100_GC: 330 case PCI_PRODUCT_INTEL_82810E_GC: 331 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 332 isc->chiptype = CHIP_I810; 333 aprint_normal(": i810-family chipset\n"); 334 break; 335 case PCI_PRODUCT_INTEL_82830MP_IV: 336 case PCI_PRODUCT_INTEL_82845G_IGD: 337 isc->chiptype = CHIP_I830; 338 aprint_normal(": i830-family chipset\n"); 339 break; 340 case PCI_PRODUCT_INTEL_82855GM_IGD: 341 case PCI_PRODUCT_INTEL_82865_IGD: 342 isc->chiptype = CHIP_I855; 343 aprint_normal(": i855-family chipset\n"); 344 break; 345 case PCI_PRODUCT_INTEL_82915G_IGD: 346 case PCI_PRODUCT_INTEL_82915GM_IGD: 347 case PCI_PRODUCT_INTEL_82945P_IGD: 348 case PCI_PRODUCT_INTEL_82945GM_IGD: 349 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 350 case PCI_PRODUCT_INTEL_82945GME_IGD: 351 case PCI_PRODUCT_INTEL_E7221_IGD: 352 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 353 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 354 isc->chiptype = CHIP_I915; 355 aprint_normal(": i915-family chipset\n"); 356 break; 357 case PCI_PRODUCT_INTEL_82965Q_IGD: 358 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 359 case PCI_PRODUCT_INTEL_82965PM_IGD: 360 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 361 case PCI_PRODUCT_INTEL_82965G_IGD: 362 case PCI_PRODUCT_INTEL_82965G_IGD_1: 363 case PCI_PRODUCT_INTEL_82965GME_IGD: 364 case PCI_PRODUCT_INTEL_82946GZ_IGD: 365 case PCI_PRODUCT_INTEL_82G35_IGD: 366 case PCI_PRODUCT_INTEL_82G35_IGD_1: 367 isc->chiptype = CHIP_I965; 368 aprint_normal(": i965-family chipset\n"); 369 break; 370 case PCI_PRODUCT_INTEL_82Q35_IGD: 371 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 372 case PCI_PRODUCT_INTEL_82G33_IGD: 373 case PCI_PRODUCT_INTEL_82G33_IGD_1: 374 case PCI_PRODUCT_INTEL_82Q33_IGD: 375 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 376 isc->chiptype = CHIP_G33; 377 aprint_normal(": G33-family chipset\n"); 378 break; 379 case PCI_PRODUCT_INTEL_82GM45_IGD: 380 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 381 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 382 case PCI_PRODUCT_INTEL_82Q45_IGD: 383 case PCI_PRODUCT_INTEL_82G45_IGD: 384 case PCI_PRODUCT_INTEL_82G41_IGD: 385 case PCI_PRODUCT_INTEL_82B43_IGD: 386 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 387 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 388 isc->chiptype = CHIP_G4X; 389 aprint_normal(": G4X-family chipset\n"); 390 break; 391 } 392 aprint_naive("\n"); 393 394 mmadr_type = PCI_MAPREG_TYPE_MEM; 395 switch (isc->chiptype) { 396 case CHIP_I915: 397 case CHIP_G33: 398 apbase = AGP_I915_GMADR; 399 mmadr_bar = AGP_I915_MMADR; 400 isc->size = 512*1024; 401 gtt_bar = AGP_I915_GTTADR; 402 gtt_off = ~(bus_size_t)0; /* XXXGCC */ 403 break; 404 case CHIP_I965: 405 apbase = AGP_I965_GMADR; 406 mmadr_bar = AGP_I965_MMADR; 407 mmadr_type |= PCI_MAPREG_MEM_TYPE_64BIT; 408 isc->size = 512*1024; 409 gtt_bar = 0; 410 gtt_off = AGP_I965_GTT; 411 break; 412 case CHIP_G4X: 413 apbase = AGP_I965_GMADR; 414 mmadr_bar = AGP_I965_MMADR; 415 mmadr_type |= PCI_MAPREG_MEM_TYPE_64BIT; 416 isc->size = 512*1024; 417 gtt_bar = 0; 418 gtt_off = AGP_G4X_GTT; 419 break; 420 default: 421 apbase = AGP_I810_GMADR; 422 mmadr_bar = AGP_I810_MMADR; 423 isc->size = 512*1024; 424 gtt_bar = 0; 425 gtt_off = AGP_I810_GTT; 426 break; 427 } 428 429 /* Map (or, rather, find the address and size of) the aperture. */ 430 if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) 431 error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase); 432 else 433 error = agp_map_aperture(&isc->vga_pa, sc, apbase); 434 if (error) { 435 aprint_error_dev(self, "can't map aperture: %d\n", error); 436 goto fail1; 437 } 438 439 /* Map the memory-mapped I/O registers, or the non-GTT part. */ 440 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, mmadr_bar, 441 mmadr_type, &mmadr, &mmadr_size, &mmadr_flags)) { 442 aprint_error_dev(self, "can't find MMIO registers\n"); 443 error = ENXIO; 444 goto fail1; 445 } 446 if (mmadr_size < isc->size) { 447 aprint_error_dev(self, "MMIO registers too small" 448 ": %"PRIuMAX" < %"PRIuMAX"\n", 449 (uintmax_t)mmadr_size, (uintmax_t)isc->size); 450 error = ENXIO; 451 goto fail1; 452 } 453 isc->bst = isc->vga_pa.pa_memt; 454 error = bus_space_map(isc->bst, mmadr, isc->size, mmadr_flags, 455 &isc->bsh); 456 if (error) { 457 aprint_error_dev(self, "can't map MMIO registers: %d\n", 458 error); 459 error = ENXIO; 460 goto fail1; 461 } 462 463 /* Set up a chipset flush page if necessary. */ 464 switch (isc->chiptype) { 465 case CHIP_I915: 466 case CHIP_I965: 467 case CHIP_G33: 468 case CHIP_G4X: 469 error = agp_i810_setup_chipset_flush_page(sc); 470 if (error) { 471 aprint_error_dev(self, 472 "can't set up chipset flush page: %d\n", error); 473 goto fail2; 474 } 475 break; 476 } 477 478 /* 479 * XXX horrible hack to allow drm code to use our mapping 480 * of VGA chip registers 481 */ 482 agp_i810_vga_regbase = mmadr; 483 agp_i810_vga_regsize = isc->size; 484 agp_i810_vga_bst = isc->bst; 485 agp_i810_vga_bsh = isc->bsh; 486 487 /* Initialize the chipset. */ 488 error = agp_i810_init(sc); 489 if (error) 490 goto fail3; 491 492 /* Map the GTT, from either part of the MMIO region or its own BAR. */ 493 if (gtt_bar == 0) { 494 isc->gtt_bst = isc->bst; 495 if ((mmadr_size - gtt_off) < isc->gtt_size) { 496 aprint_error_dev(self, "GTTMMADR too small for GTT" 497 ": (%"PRIxMAX" - %"PRIxMAX") < %"PRIxMAX"\n", 498 (uintmax_t)mmadr_size, 499 (uintmax_t)gtt_off, 500 (uintmax_t)isc->gtt_size); 501 error = ENXIO; 502 goto fail4; 503 } 504 /* 505 * Map the GTT separately if we can, so that we can map 506 * it prefetchable, but in early models, there are MMIO 507 * registers before and after the GTT, so we can only 508 * take a subregion. 509 */ 510 if (isc->size < gtt_off) 511 error = bus_space_map(isc->gtt_bst, (mmadr + gtt_off), 512 isc->gtt_size, mmadr_flags, &isc->gtt_bsh); 513 else 514 error = bus_space_subregion(isc->bst, isc->bsh, 515 gtt_off, isc->gtt_size, &isc->gtt_bsh); 516 if (error) { 517 aprint_error_dev(self, "can't map GTT: %d\n", error); 518 error = ENXIO; 519 goto fail4; 520 } 521 } else { 522 bus_size_t gtt_bar_size; 523 /* 524 * All chipsets with a separate BAR for the GTT, namely 525 * the i915 and G33 families, have 32-bit GTT BARs. 526 * 527 * XXX [citation needed] 528 */ 529 if (pci_mapreg_map(&isc->vga_pa, gtt_bar, PCI_MAPREG_TYPE_MEM, 530 0, 531 &isc->gtt_bst, &isc->gtt_bsh, NULL, >t_bar_size)) { 532 aprint_error_dev(self, "can't map GTT\n"); 533 error = ENXIO; 534 goto fail4; 535 } 536 if (gtt_bar_size != isc->gtt_size) { 537 aprint_error_dev(self, 538 "BAR size %"PRIxMAX 539 " mismatches detected GTT size %"PRIxMAX 540 "; trusting BAR\n", 541 (uintmax_t)gtt_bar_size, 542 (uintmax_t)isc->gtt_size); 543 isc->gtt_size = gtt_bar_size; 544 } 545 } 546 547 /* Power management. (XXX Nothing to save on suspend? Fishy...) */ 548 if (!pmf_device_register(self, NULL, agp_i810_resume)) 549 aprint_error_dev(self, "can't establish power handler\n"); 550 551 /* Match the generic AGP code's autoconf output format. */ 552 aprint_normal("%s", device_xname(self)); 553 554 /* Success! */ 555 return 0; 556 557 fail5: __unused 558 pmf_device_deregister(self); 559 if ((gtt_bar != 0) || (isc->size < gtt_off)) 560 bus_space_unmap(isc->gtt_bst, isc->gtt_bsh, isc->gtt_size); 561 isc->gtt_size = 0; 562 fail4: 563 #if notyet 564 agp_i810_fini(sc); 565 #endif 566 fail3: switch (isc->chiptype) { 567 case CHIP_I915: 568 case CHIP_I965: 569 case CHIP_G33: 570 case CHIP_G4X: 571 agp_i810_teardown_chipset_flush_page(sc); 572 break; 573 } 574 fail2: bus_space_unmap(isc->bst, isc->bsh, isc->size); 575 isc->size = 0; 576 fail1: free(isc, M_AGP); 577 sc->as_chipc = NULL; 578 fail0: agp_generic_detach(sc); 579 KASSERT(error); 580 return error; 581 } 582 583 static int 584 agp_i810_setup_chipset_flush_page(struct agp_softc *sc) 585 { 586 struct agp_i810_softc *const isc = sc->as_chipc; 587 const pci_chipset_tag_t pc = sc->as_pc; 588 const pcitag_t tag = sc->as_tag; 589 pcireg_t lo, hi; 590 bus_addr_t addr, minaddr, maxaddr; 591 int error; 592 593 /* We always use memory-mapped I/O. */ 594 isc->flush_bst = isc->vga_pa.pa_memt; 595 596 /* No page allocated yet. */ 597 isc->flush_addr = 0; 598 599 /* Read the PCI config register: 4-byte on gen3, 8-byte on gen>=4. */ 600 if (isc->chiptype == CHIP_I915) { 601 addr = pci_conf_read(pc, tag, AGP_I915_IFPADDR); 602 minaddr = PAGE_SIZE; /* XXX PCIBIOS_MIN_MEM? */ 603 maxaddr = UINT32_MAX; 604 } else { 605 hi = pci_conf_read(pc, tag, AGP_I965_IFPADDR+4); 606 lo = pci_conf_read(pc, tag, AGP_I965_IFPADDR); 607 /* 608 * Convert to uint64_t, rather than bus_addr_t which 609 * may be 32-bit, to avoid undefined behaviour with a 610 * too-wide shift. Since the BIOS doesn't know whether 611 * the OS will run 64-bit or with PAE, it ought to 612 * configure at most a 32-bit physical address, so 613 * let's print a warning in case that happens. 614 */ 615 addr = ((uint64_t)hi << 32) | lo; 616 if (hi) { 617 aprint_error_dev(sc->as_dev, 618 "BIOS configured >32-bit flush page address" 619 ": %"PRIx64"\n", ((uint64_t)hi << 32) | lo); 620 #if __i386__ && !PAE 621 return EIO; 622 #endif 623 } 624 minaddr = PAGE_SIZE; /* XXX PCIBIOS_MIN_MEM? */ 625 maxaddr = MIN(UINT64_MAX, ~(bus_addr_t)0); 626 } 627 628 /* Allocate or map a pre-allocated a page for it. */ 629 if (ISSET(addr, 1)) { 630 /* BIOS allocated it for us. Use that. */ 631 error = bus_space_map(isc->flush_bst, addr & ~1, PAGE_SIZE, 0, 632 &isc->flush_bsh); 633 if (error) 634 return error; 635 } else { 636 /* None allocated. Allocate one. */ 637 error = bus_space_alloc(isc->flush_bst, minaddr, maxaddr, 638 PAGE_SIZE, PAGE_SIZE, 0, 0, 639 &isc->flush_addr, &isc->flush_bsh); 640 if (error) 641 return error; 642 KASSERT(isc->flush_addr != 0); 643 /* Write it into the PCI config register. */ 644 addr = isc->flush_addr | 1; 645 if (isc->chiptype == CHIP_I915) { 646 pci_conf_write(pc, tag, AGP_I915_IFPADDR, addr); 647 } else { 648 hi = __SHIFTOUT(addr, __BITS(63, 32)); 649 lo = __SHIFTOUT(addr, __BITS(31, 0)); 650 pci_conf_write(pc, tag, AGP_I965_IFPADDR+4, hi); 651 pci_conf_write(pc, tag, AGP_I965_IFPADDR, lo); 652 } 653 } 654 655 /* Success! */ 656 return 0; 657 } 658 659 static void 660 agp_i810_teardown_chipset_flush_page(struct agp_softc *sc) 661 { 662 struct agp_i810_softc *const isc = sc->as_chipc; 663 664 if (isc->flush_addr) { 665 /* If we allocated a page, clear it. */ 666 if (isc->chiptype == CHIP_I915) { 667 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR, 668 0); 669 } else { 670 pci_conf_write(sc->as_pc, sc->as_tag, 671 AGP_I965_IFPADDR, 0); 672 pci_conf_write(sc->as_pc, sc->as_tag, 673 AGP_I965_IFPADDR + 4, 0); 674 } 675 isc->flush_addr = 0; 676 bus_space_free(isc->flush_bst, isc->flush_bsh, 677 PAGE_SIZE); 678 } else { 679 /* Otherwise, just unmap the pre-allocated page. */ 680 bus_space_unmap(isc->flush_bst, isc->flush_bsh, PAGE_SIZE); 681 } 682 } 683 684 /* 685 * XXX horrible hack to allow drm code to use our mapping 686 * of VGA chip registers 687 */ 688 int 689 agp_i810_borrow(bus_addr_t base, bus_size_t size, bus_space_handle_t *hdlp) 690 { 691 692 if (agp_i810_vga_regbase == 0) 693 return 0; 694 if (base < agp_i810_vga_regbase) 695 return 0; 696 if (agp_i810_vga_regsize < size) 697 return 0; 698 if ((base - agp_i810_vga_regbase) > (agp_i810_vga_regsize - size)) 699 return 0; 700 if (bus_space_subregion(agp_i810_vga_bst, agp_i810_vga_bsh, 701 (base - agp_i810_vga_regbase), (agp_i810_vga_regsize - size), 702 hdlp)) 703 return 0; 704 return 1; 705 } 706 707 static int 708 agp_i810_init(struct agp_softc *sc) 709 { 710 struct agp_i810_softc *isc; 711 int error; 712 713 isc = sc->as_chipc; 714 715 if (isc->chiptype == CHIP_I810) { 716 struct agp_gatt *gatt; 717 void *virtual; 718 int dummyseg; 719 720 /* Some i810s have on-chip memory called dcache */ 721 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 722 isc->dcache_size = 4 * 1024 * 1024; 723 else 724 isc->dcache_size = 0; 725 726 /* According to the specs the gatt on the i810 must be 64k */ 727 isc->gtt_size = 64 * 1024; 728 gatt = malloc(sizeof(*gatt), M_AGP, M_NOWAIT); 729 if (gatt == NULL) { 730 aprint_error_dev(sc->as_dev, 731 "can't malloc GATT record\n"); 732 error = ENOMEM; 733 goto fail0; 734 } 735 gatt->ag_entries = isc->gtt_size / sizeof(uint32_t); 736 error = agp_alloc_dmamem(sc->as_dmat, isc->gtt_size, 737 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical, 738 &gatt->ag_dmaseg, 1, &dummyseg); 739 if (error) { 740 aprint_error_dev(sc->as_dev, 741 "can't allocate memory for GTT: %d\n", error); 742 free(gatt, M_AGP); 743 goto fail0; 744 } 745 746 gatt->ag_virtual = (uint32_t *)virtual; 747 gatt->ag_size = gatt->ag_entries * sizeof(uint32_t); 748 memset(gatt->ag_virtual, 0, gatt->ag_size); 749 agp_flush_cache(); 750 751 /* Install the GATT. */ 752 isc->pgtblctl = gatt->ag_physical | 1; 753 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 754 isc->gatt = gatt; 755 } else if (isc->chiptype == CHIP_I830) { 756 /* The i830 automatically initializes the 128k gatt on boot. */ 757 /* XXX [citation needed] */ 758 pcireg_t reg; 759 u_int16_t gcc1; 760 761 isc->gtt_size = 128 * 1024; 762 763 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 764 gcc1 = (u_int16_t)(reg >> 16); 765 switch (gcc1 & AGP_I830_GCC1_GMS) { 766 case AGP_I830_GCC1_GMS_STOLEN_512: 767 isc->stolen = (512 - 132) * 1024 / 4096; 768 break; 769 case AGP_I830_GCC1_GMS_STOLEN_1024: 770 isc->stolen = (1024 - 132) * 1024 / 4096; 771 break; 772 case AGP_I830_GCC1_GMS_STOLEN_8192: 773 isc->stolen = (8192 - 132) * 1024 / 4096; 774 break; 775 default: 776 isc->stolen = 0; 777 aprint_error_dev(sc->as_dev, 778 "unknown memory configuration, disabling\n"); 779 error = ENXIO; 780 goto fail0; 781 } 782 783 if (isc->stolen > 0) { 784 aprint_normal_dev(sc->as_dev, 785 "detected %dk stolen memory\n", 786 isc->stolen * 4); 787 } 788 789 /* GATT address is already in there, make sure it's enabled */ 790 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 791 isc->pgtblctl |= 1; 792 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 793 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 794 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 || 795 isc->chiptype == CHIP_G4X) { 796 pcireg_t reg; 797 u_int32_t gtt_size, stolen; /* XXX kilobytes */ 798 u_int16_t gcc1; 799 800 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1); 801 gcc1 = (u_int16_t)(reg >> 16); 802 803 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 804 805 /* Stolen memory is set up at the beginning of the aperture by 806 * the BIOS, consisting of the GATT followed by 4kb for the 807 * BIOS display. 808 */ 809 switch (isc->chiptype) { 810 case CHIP_I855: 811 gtt_size = 128; 812 break; 813 case CHIP_I915: 814 gtt_size = 256; 815 break; 816 case CHIP_I965: 817 switch (isc->pgtblctl & AGP_I810_PGTBL_SIZE_MASK) { 818 case AGP_I810_PGTBL_SIZE_128KB: 819 case AGP_I810_PGTBL_SIZE_512KB: 820 gtt_size = 512; 821 break; 822 case AGP_I965_PGTBL_SIZE_1MB: 823 gtt_size = 1024; 824 break; 825 case AGP_I965_PGTBL_SIZE_2MB: 826 gtt_size = 2048; 827 break; 828 case AGP_I965_PGTBL_SIZE_1_5MB: 829 gtt_size = 1024 + 512; 830 break; 831 default: 832 aprint_error_dev(sc->as_dev, 833 "bad PGTBL size\n"); 834 error = ENXIO; 835 goto fail0; 836 } 837 break; 838 case CHIP_G33: 839 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 840 case AGP_G33_PGTBL_SIZE_1M: 841 gtt_size = 1024; 842 break; 843 case AGP_G33_PGTBL_SIZE_2M: 844 gtt_size = 2048; 845 break; 846 default: 847 aprint_error_dev(sc->as_dev, 848 "bad PGTBL size\n"); 849 error = ENXIO; 850 goto fail0; 851 } 852 break; 853 case CHIP_G4X: 854 switch (isc->pgtblctl & AGP_G4X_PGTBL_SIZE_MASK) { 855 case AGP_G4X_PGTBL_SIZE_512K: 856 gtt_size = 512; 857 break; 858 case AGP_G4X_PGTBL_SIZE_256K: 859 gtt_size = 256; 860 break; 861 case AGP_G4X_PGTBL_SIZE_128K: 862 gtt_size = 128; 863 break; 864 case AGP_G4X_PGTBL_SIZE_1M: 865 gtt_size = 1*1024; 866 break; 867 case AGP_G4X_PGTBL_SIZE_2M: 868 gtt_size = 2*1024; 869 break; 870 case AGP_G4X_PGTBL_SIZE_1_5M: 871 gtt_size = 1*1024 + 512; 872 break; 873 default: 874 aprint_error_dev(sc->as_dev, 875 "bad PGTBL size\n"); 876 error = ENXIO; 877 goto fail0; 878 } 879 break; 880 default: 881 panic("impossible chiptype %d", isc->chiptype); 882 } 883 884 /* 885 * XXX If I'm reading the datasheets right, this stolen 886 * memory detection logic is totally wrong. 887 */ 888 switch (gcc1 & AGP_I855_GCC1_GMS) { 889 case AGP_I855_GCC1_GMS_STOLEN_1M: 890 stolen = 1024; 891 break; 892 case AGP_I855_GCC1_GMS_STOLEN_4M: 893 stolen = 4 * 1024; 894 break; 895 case AGP_I855_GCC1_GMS_STOLEN_8M: 896 stolen = 8 * 1024; 897 break; 898 case AGP_I855_GCC1_GMS_STOLEN_16M: 899 stolen = 16 * 1024; 900 break; 901 case AGP_I855_GCC1_GMS_STOLEN_32M: 902 stolen = 32 * 1024; 903 break; 904 case AGP_I915_GCC1_GMS_STOLEN_48M: 905 stolen = 48 * 1024; 906 break; 907 case AGP_I915_GCC1_GMS_STOLEN_64M: 908 stolen = 64 * 1024; 909 break; 910 case AGP_G33_GCC1_GMS_STOLEN_128M: 911 stolen = 128 * 1024; 912 break; 913 case AGP_G33_GCC1_GMS_STOLEN_256M: 914 stolen = 256 * 1024; 915 break; 916 case AGP_G4X_GCC1_GMS_STOLEN_96M: 917 stolen = 96 * 1024; 918 break; 919 case AGP_G4X_GCC1_GMS_STOLEN_160M: 920 stolen = 160 * 1024; 921 break; 922 case AGP_G4X_GCC1_GMS_STOLEN_224M: 923 stolen = 224 * 1024; 924 break; 925 case AGP_G4X_GCC1_GMS_STOLEN_352M: 926 stolen = 352 * 1024; 927 break; 928 default: 929 aprint_error_dev(sc->as_dev, 930 "unknown memory configuration, disabling\n"); 931 error = ENXIO; 932 goto fail0; 933 } 934 935 switch (gcc1 & AGP_I855_GCC1_GMS) { 936 case AGP_I915_GCC1_GMS_STOLEN_48M: 937 case AGP_I915_GCC1_GMS_STOLEN_64M: 938 if (isc->chiptype != CHIP_I915 && 939 isc->chiptype != CHIP_I965 && 940 isc->chiptype != CHIP_G33 && 941 isc->chiptype != CHIP_G4X) 942 stolen = 0; 943 break; 944 case AGP_G33_GCC1_GMS_STOLEN_128M: 945 case AGP_G33_GCC1_GMS_STOLEN_256M: 946 if (isc->chiptype != CHIP_I965 && 947 isc->chiptype != CHIP_G33 && 948 isc->chiptype != CHIP_G4X) 949 stolen = 0; 950 break; 951 case AGP_G4X_GCC1_GMS_STOLEN_96M: 952 case AGP_G4X_GCC1_GMS_STOLEN_160M: 953 case AGP_G4X_GCC1_GMS_STOLEN_224M: 954 case AGP_G4X_GCC1_GMS_STOLEN_352M: 955 if (isc->chiptype != CHIP_I965 && 956 isc->chiptype != CHIP_G4X) 957 stolen = 0; 958 break; 959 } 960 961 isc->gtt_size = gtt_size * 1024; 962 963 /* BIOS space */ 964 /* XXX [citation needed] */ 965 gtt_size += 4; 966 967 /* XXX [citation needed] for this subtraction */ 968 isc->stolen = (stolen - gtt_size) * 1024 / 4096; 969 970 if (isc->stolen > 0) { 971 aprint_normal_dev(sc->as_dev, 972 "detected %dk stolen memory\n", 973 isc->stolen * 4); 974 } 975 976 /* GATT address is already in there, make sure it's enabled */ 977 isc->pgtblctl |= 1; 978 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 979 } 980 981 /* 982 * Make sure the chipset can see everything. 983 */ 984 agp_flush_cache(); 985 986 /* 987 * Publish what we found for kludgey drivers (I'm looking at 988 * you, drm). 989 */ 990 if (agp_i810_sc == NULL) 991 agp_i810_sc = sc; 992 else 993 aprint_error_dev(sc->as_dev, "agp already attached\n"); 994 995 /* Success! */ 996 return 0; 997 998 fail0: KASSERT(error); 999 return error; 1000 } 1001 1002 #if 0 1003 static int 1004 agp_i810_detach(struct agp_softc *sc) 1005 { 1006 int error; 1007 struct agp_i810_softc *isc = sc->as_chipc; 1008 1009 error = agp_generic_detach(sc); 1010 if (error) 1011 return error; 1012 1013 switch (isc->chiptype) { 1014 case CHIP_I915: 1015 case CHIP_I965: 1016 case CHIP_G33: 1017 case CHIP_G4X: 1018 agp_i810_teardown_chipset_flush_page(sc); 1019 break; 1020 } 1021 1022 /* Clear the GATT base. */ 1023 if (sc->chiptype == CHIP_I810) { 1024 WRITE4(AGP_I810_PGTBL_CTL, 0); 1025 } else { 1026 unsigned int pgtblctl; 1027 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 1028 pgtblctl &= ~1; 1029 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 1030 } 1031 1032 if (sc->chiptype == CHIP_I810) { 1033 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap, 1034 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 1035 free(isc->gatt, M_AGP); 1036 } 1037 1038 return 0; 1039 } 1040 #endif 1041 1042 static u_int32_t 1043 agp_i810_get_aperture(struct agp_softc *sc) 1044 { 1045 struct agp_i810_softc *isc = sc->as_chipc; 1046 pcireg_t reg; 1047 u_int32_t size; 1048 u_int16_t miscc, gcc1; 1049 1050 size = 0; 1051 1052 switch (isc->chiptype) { 1053 case CHIP_I810: 1054 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 1055 miscc = (u_int16_t)(reg >> 16); 1056 if ((miscc & AGP_I810_MISCC_WINSIZE) == 1057 AGP_I810_MISCC_WINSIZE_32) 1058 size = 32 * 1024 * 1024; 1059 else 1060 size = 64 * 1024 * 1024; 1061 break; 1062 case CHIP_I830: 1063 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 1064 gcc1 = (u_int16_t)(reg >> 16); 1065 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 1066 size = 64 * 1024 * 1024; 1067 else 1068 size = 128 * 1024 * 1024; 1069 break; 1070 case CHIP_I855: 1071 size = 128 * 1024 * 1024; 1072 break; 1073 case CHIP_I915: 1074 case CHIP_G33: 1075 case CHIP_G4X: 1076 size = sc->as_apsize; 1077 break; 1078 case CHIP_I965: 1079 size = 512 * 1024 * 1024; 1080 break; 1081 default: 1082 aprint_error(": Unknown chipset\n"); 1083 } 1084 1085 return size; 1086 } 1087 1088 static int 1089 agp_i810_set_aperture(struct agp_softc *sc __unused, 1090 uint32_t aperture __unused) 1091 { 1092 1093 return ENOSYS; 1094 } 1095 1096 static int 1097 agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 1098 { 1099 struct agp_i810_softc *isc = sc->as_chipc; 1100 1101 if (offset < 0 || offset >= ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) { 1102 DPRINTF(sc, "failed" 1103 ": offset 0x%"PRIxMAX", shift %u, entries %"PRIuMAX"\n", 1104 (uintmax_t)offset, 1105 (unsigned)AGP_PAGE_SHIFT, 1106 (uintmax_t)isc->gtt_size/4); 1107 return EINVAL; 1108 } 1109 1110 if (isc->chiptype != CHIP_I810) { 1111 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1112 DPRINTF(sc, "trying to bind into stolen memory\n"); 1113 return EINVAL; 1114 } 1115 } 1116 1117 return agp_i810_write_gtt_entry(isc, offset, physical | 1); 1118 } 1119 1120 static int 1121 agp_i810_unbind_page(struct agp_softc *sc, off_t offset) 1122 { 1123 struct agp_i810_softc *isc = sc->as_chipc; 1124 1125 if (offset < 0 || offset >= ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) 1126 return EINVAL; 1127 1128 if (isc->chiptype != CHIP_I810 ) { 1129 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1130 DPRINTF(sc, "trying to unbind from stolen memory\n"); 1131 return EINVAL; 1132 } 1133 } 1134 1135 return agp_i810_write_gtt_entry(isc, offset, 0); 1136 } 1137 1138 /* 1139 * Writing via memory mapped registers already flushes all TLBs. 1140 */ 1141 static void 1142 agp_i810_flush_tlb(struct agp_softc *sc) 1143 { 1144 } 1145 1146 static int 1147 agp_i810_enable(struct agp_softc *sc, u_int32_t mode) 1148 { 1149 1150 return 0; 1151 } 1152 1153 #define AGP_I810_MEMTYPE_MAIN 0 1154 #define AGP_I810_MEMTYPE_DCACHE 1 1155 #define AGP_I810_MEMTYPE_HWCURSOR 2 1156 1157 static struct agp_memory * 1158 agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size) 1159 { 1160 struct agp_i810_softc *isc = sc->as_chipc; 1161 struct agp_memory *mem; 1162 int error; 1163 1164 DPRINTF(sc, "AGP: alloc(%d, 0x%"PRIxMAX")\n", type, (uintmax_t)size); 1165 1166 if (size <= 0) 1167 return NULL; 1168 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 1169 return NULL; 1170 KASSERT(sc->as_allocated <= sc->as_maxmem); 1171 if (size > (sc->as_maxmem - sc->as_allocated)) 1172 return NULL; 1173 if (size > ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) 1174 return NULL; 1175 1176 switch (type) { 1177 case AGP_I810_MEMTYPE_MAIN: 1178 break; 1179 case AGP_I810_MEMTYPE_DCACHE: 1180 if (isc->chiptype != CHIP_I810) 1181 return NULL; 1182 if (size != isc->dcache_size) 1183 return NULL; 1184 break; 1185 case AGP_I810_MEMTYPE_HWCURSOR: 1186 if ((size != AGP_PAGE_SIZE) && 1187 (size != AGP_PAGE_SIZE*4)) 1188 return NULL; 1189 break; 1190 default: 1191 return NULL; 1192 } 1193 1194 mem = malloc(sizeof(*mem), M_AGP, M_WAITOK|M_ZERO); 1195 if (mem == NULL) 1196 goto fail0; 1197 mem->am_id = sc->as_nextid++; 1198 mem->am_size = size; 1199 mem->am_type = type; 1200 1201 switch (type) { 1202 case AGP_I810_MEMTYPE_MAIN: 1203 error = bus_dmamap_create(sc->as_dmat, size, 1204 (size >> AGP_PAGE_SHIFT) + 1, size, 0, BUS_DMA_WAITOK, 1205 &mem->am_dmamap); 1206 if (error) 1207 goto fail1; 1208 break; 1209 case AGP_I810_MEMTYPE_DCACHE: 1210 break; 1211 case AGP_I810_MEMTYPE_HWCURSOR: 1212 mem->am_dmaseg = malloc(sizeof(*mem->am_dmaseg), M_AGP, 1213 M_WAITOK); 1214 error = agp_alloc_dmamem(sc->as_dmat, size, 0, &mem->am_dmamap, 1215 &mem->am_virtual, &mem->am_physical, mem->am_dmaseg, 1, 1216 &mem->am_nseg); 1217 if (error) { 1218 free(mem->am_dmaseg, M_AGP); 1219 goto fail1; 1220 } 1221 (void)memset(mem->am_virtual, 0, size); 1222 break; 1223 default: 1224 panic("invalid agp memory type: %d", type); 1225 } 1226 1227 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link); 1228 sc->as_allocated += size; 1229 1230 return mem; 1231 1232 fail1: free(mem, M_AGP); 1233 fail0: return NULL; 1234 } 1235 1236 static int 1237 agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem) 1238 { 1239 1240 if (mem->am_is_bound) 1241 return EBUSY; 1242 1243 switch (mem->am_type) { 1244 case AGP_I810_MEMTYPE_MAIN: 1245 bus_dmamap_destroy(sc->as_dmat, mem->am_dmamap); 1246 break; 1247 case AGP_I810_MEMTYPE_DCACHE: 1248 break; 1249 case AGP_I810_MEMTYPE_HWCURSOR: 1250 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap, 1251 mem->am_virtual, mem->am_dmaseg, mem->am_nseg); 1252 free(mem->am_dmaseg, M_AGP); 1253 break; 1254 default: 1255 panic("invalid agp i810 memory type: %d", mem->am_type); 1256 } 1257 1258 sc->as_allocated -= mem->am_size; 1259 TAILQ_REMOVE(&sc->as_memory, mem, am_link); 1260 free(mem, M_AGP); 1261 1262 return 0; 1263 } 1264 1265 static int 1266 agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem, 1267 off_t offset) 1268 { 1269 struct agp_i810_softc *isc = sc->as_chipc; 1270 uint32_t pgtblctl; 1271 int error; 1272 1273 if (mem->am_is_bound) 1274 return EINVAL; 1275 1276 /* 1277 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 1278 * X server for mysterious reasons which leads to crashes if we write 1279 * to the GTT through the MMIO window. 1280 * Until the issue is solved, simply restore it. 1281 */ 1282 pgtblctl = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL); 1283 if (pgtblctl != isc->pgtblctl) { 1284 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%"PRIx32 1285 " - fixing\n", pgtblctl); 1286 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 1287 isc->pgtblctl); 1288 } 1289 1290 switch (mem->am_type) { 1291 case AGP_I810_MEMTYPE_MAIN: 1292 return agp_generic_bind_memory_bounded(sc, mem, offset, 1293 0, (isc->gtt_size/4) << AGP_PAGE_SHIFT); 1294 case AGP_I810_MEMTYPE_DCACHE: 1295 error = agp_i810_bind_memory_dcache(sc, mem, offset); 1296 break; 1297 case AGP_I810_MEMTYPE_HWCURSOR: 1298 error = agp_i810_bind_memory_hwcursor(sc, mem, offset); 1299 break; 1300 default: 1301 panic("invalid agp i810 memory type: %d", mem->am_type); 1302 } 1303 if (error) 1304 return error; 1305 1306 /* Success! */ 1307 mem->am_is_bound = 1; 1308 return 0; 1309 } 1310 1311 #define I810_GTT_PTE_VALID 0x01 1312 #define I810_GTT_PTE_DCACHE 0x02 1313 1314 static int 1315 agp_i810_bind_memory_dcache(struct agp_softc *sc, struct agp_memory *mem, 1316 off_t offset) 1317 { 1318 struct agp_i810_softc *const isc __diagused = sc->as_chipc; 1319 uint32_t i, j; 1320 int error; 1321 1322 KASSERT(isc->chiptype == CHIP_I810); 1323 1324 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0); 1325 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 1326 error = agp_i810_write_gtt_entry(isc, offset + i, 1327 i | I810_GTT_PTE_VALID | I810_GTT_PTE_DCACHE); 1328 if (error) 1329 goto fail0; 1330 } 1331 1332 /* Success! */ 1333 mem->am_offset = offset; 1334 return 0; 1335 1336 fail0: for (j = 0; j < i; j += AGP_PAGE_SIZE) 1337 (void)agp_i810_unbind_page(sc, offset + j); 1338 return error; 1339 } 1340 1341 static int 1342 agp_i810_bind_memory_hwcursor(struct agp_softc *sc, struct agp_memory *mem, 1343 off_t offset) 1344 { 1345 const bus_addr_t pa = mem->am_physical; 1346 uint32_t i, j; 1347 int error; 1348 1349 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0); 1350 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 1351 error = agp_i810_bind_page(sc, offset + i, pa + i); 1352 if (error) 1353 goto fail0; 1354 } 1355 1356 /* Success! */ 1357 mem->am_offset = offset; 1358 return 0; 1359 1360 fail0: for (j = 0; j < i; j += AGP_PAGE_SIZE) 1361 (void)agp_i810_unbind_page(sc, offset + j); 1362 return error; 1363 } 1364 1365 static int 1366 agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem) 1367 { 1368 struct agp_i810_softc *isc = sc->as_chipc; 1369 u_int32_t i; 1370 1371 if (!mem->am_is_bound) 1372 return EINVAL; 1373 1374 switch (mem->am_type) { 1375 case AGP_I810_MEMTYPE_MAIN: 1376 return agp_generic_unbind_memory(sc, mem); 1377 case AGP_I810_MEMTYPE_DCACHE: 1378 KASSERT(isc->chiptype == CHIP_I810); 1379 /* FALLTHROUGH */ 1380 case AGP_I810_MEMTYPE_HWCURSOR: 1381 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1382 (void)agp_i810_unbind_page(sc, mem->am_offset + i); 1383 mem->am_offset = 0; 1384 break; 1385 default: 1386 panic("invalid agp i810 memory type: %d", mem->am_type); 1387 } 1388 1389 mem->am_is_bound = 0; 1390 return 0; 1391 } 1392 1393 static bool 1394 agp_i810_resume(device_t dv, const pmf_qual_t *qual) 1395 { 1396 struct agp_softc *sc = device_private(dv); 1397 struct agp_i810_softc *isc = sc->as_chipc; 1398 1399 /* 1400 * XXX Nothing uses this! Save on suspend, restore on resume? 1401 */ 1402 isc->pgtblctl_resume_hack = READ4(AGP_I810_PGTBL_CTL); 1403 agp_flush_cache(); 1404 1405 return true; 1406 } 1407
Indexes created Tue Sep 23 07:09:52 GMT 2025