agp_i810.c revision 1.112.2.3
1 /* $NetBSD: agp_i810.c,v 1.112.2.3 2015/04/23 07:31:16 snj Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.112.2.3 2015/04/23 07:31:16 snj Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/atomic.h> 38 #include <sys/malloc.h> 39 #include <sys/kernel.h> 40 #include <sys/proc.h> 41 #include <sys/device.h> 42 #include <sys/conf.h> 43 #include <sys/xcall.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/agpvar.h> 49 #include <dev/pci/agpreg.h> 50 #include <dev/pci/agp_i810var.h> 51 52 #include <sys/agpio.h> 53 54 #include <sys/bus.h> 55 56 #include "agp_intel.h" 57 58 #ifdef AGP_DEBUG 59 #define DPRINTF(sc, fmt, ...) \ 60 device_printf((sc)->as_dev, "%s: " fmt, __func__, ##__VA_ARGS__) 61 #else 62 #define DPRINTF(sc, fmt, ...) do {} while (0) 63 #endif 64 65 struct agp_softc *agp_i810_sc = NULL; 66 67 #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off) 68 #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off) 69 #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v) 70 71 #define CHIP_I810 0 /* i810/i815 */ 72 #define CHIP_I830 1 /* 830M/845G */ 73 #define CHIP_I855 2 /* 852GM/855GM/865G */ 74 #define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */ 75 #define CHIP_I965 4 /* 965Q/965PM */ 76 #define CHIP_G33 5 /* G33/Q33/Q35 */ 77 #define CHIP_G4X 6 /* G45/Q45 */ 78 79 /* XXX hack, see below */ 80 static bus_addr_t agp_i810_vga_regbase; 81 static bus_size_t agp_i810_vga_regsize; 82 static bus_space_tag_t agp_i810_vga_bst; 83 static bus_space_handle_t agp_i810_vga_bsh; 84 85 static u_int32_t agp_i810_get_aperture(struct agp_softc *); 86 static int agp_i810_set_aperture(struct agp_softc *, u_int32_t); 87 static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t); 88 static int agp_i810_unbind_page(struct agp_softc *, off_t); 89 static void agp_i810_flush_tlb(struct agp_softc *); 90 static int agp_i810_enable(struct agp_softc *, u_int32_t mode); 91 static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int, 92 vsize_t); 93 static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *); 94 static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, 95 off_t); 96 static int agp_i810_bind_memory_dcache(struct agp_softc *, struct agp_memory *, 97 off_t); 98 static int agp_i810_bind_memory_hwcursor(struct agp_softc *, 99 struct agp_memory *, off_t); 100 static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *); 101 102 static bool agp_i810_resume(device_t, const pmf_qual_t *); 103 static int agp_i810_init(struct agp_softc *); 104 105 static int agp_i810_setup_chipset_flush_page(struct agp_softc *); 106 static void agp_i810_teardown_chipset_flush_page(struct agp_softc *); 107 static int agp_i810_init(struct agp_softc *); 108 109 static struct agp_methods agp_i810_methods = { 110 agp_i810_get_aperture, 111 agp_i810_set_aperture, 112 agp_i810_bind_page, 113 agp_i810_unbind_page, 114 agp_i810_flush_tlb, 115 agp_i810_enable, 116 agp_i810_alloc_memory, 117 agp_i810_free_memory, 118 agp_i810_bind_memory, 119 agp_i810_unbind_memory, 120 }; 121 122 int 123 agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, 124 bus_addr_t addr, int flags) 125 { 126 u_int32_t pte; 127 128 /* 129 * Bits 11:4 (physical start address extension) should be zero. 130 * Flag bits 3:0 should be zero too. 131 * 132 * XXX This should be a kassert -- no reason for this routine 133 * to allow failure. 134 */ 135 if ((addr & 0xfff) != 0) 136 return EINVAL; 137 KASSERT(flags == (flags & 0x7)); 138 139 pte = (u_int32_t)addr; 140 /* 141 * We need to massage the pte if bus_addr_t is wider than 32 bits. 142 * The compiler isn't smart enough, hence the casts to uintmax_t. 143 */ 144 if (sizeof(bus_addr_t) > sizeof(u_int32_t)) { 145 /* 965+ can do 36-bit addressing, add in the extra bits. */ 146 if (isc->chiptype == CHIP_I965 || 147 isc->chiptype == CHIP_G33 || 148 isc->chiptype == CHIP_G4X) { 149 if (((uintmax_t)addr >> 36) != 0) 150 return EINVAL; 151 pte |= (addr >> 28) & 0xf0; 152 } else { 153 if (((uintmax_t)addr >> 32) != 0) 154 return EINVAL; 155 } 156 } 157 158 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, 159 4*(off >> AGP_PAGE_SHIFT), pte | flags); 160 161 return 0; 162 } 163 164 void 165 agp_i810_post_gtt_entry(struct agp_i810_softc *isc, off_t off) 166 { 167 168 /* 169 * See <https://bugs.freedesktop.org/show_bug.cgi?id=88191>. 170 * Out of paranoia, let's do the write barrier and posting 171 * read, because I don't have enough time or hardware to 172 * conduct conclusive tests. 173 */ 174 membar_producer(); 175 (void)bus_space_read_4(isc->gtt_bst, isc->gtt_bsh, 176 4*(off >> AGP_PAGE_SHIFT)); 177 } 178 179 static void 180 agp_flush_cache_xc(void *a __unused, void *b __unused) 181 { 182 183 agp_flush_cache(); 184 } 185 186 void 187 agp_i810_chipset_flush(struct agp_i810_softc *isc) 188 { 189 unsigned int timo = 20000; /* * 50 us = 1 s */ 190 191 switch (isc->chiptype) { 192 case CHIP_I810: 193 break; 194 case CHIP_I830: 195 case CHIP_I855: 196 /* 197 * Flush all CPU caches. If we're cold, we can't run 198 * xcalls, but there should be only one CPU up, so 199 * flushing only the local CPU's cache should suffice. 200 * 201 * XXX Come to think of it, do these chipsets appear in 202 * any multi-CPU systems? 203 */ 204 if (cold) 205 agp_flush_cache(); 206 else 207 xc_wait(xc_broadcast(0, &agp_flush_cache_xc, 208 NULL, NULL)); 209 WRITE4(AGP_I830_HIC, READ4(AGP_I830_HIC) | __BIT(31)); 210 while (ISSET(READ4(AGP_I830_HIC), __BIT(31))) { 211 if (timo-- == 0) 212 break; 213 DELAY(50); 214 } 215 break; 216 case CHIP_I915: 217 case CHIP_I965: 218 case CHIP_G33: 219 case CHIP_G4X: 220 bus_space_write_4(isc->flush_bst, isc->flush_bsh, 0, 1); 221 break; 222 } 223 } 224 225 /* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */ 226 static int 227 agp_i810_vgamatch(const struct pci_attach_args *pa) 228 { 229 230 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 231 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 232 return (0); 233 234 switch (PCI_PRODUCT(pa->pa_id)) { 235 case PCI_PRODUCT_INTEL_82810_GC: 236 case PCI_PRODUCT_INTEL_82810_DC100_GC: 237 case PCI_PRODUCT_INTEL_82810E_GC: 238 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 239 case PCI_PRODUCT_INTEL_82830MP_IV: 240 case PCI_PRODUCT_INTEL_82845G_IGD: 241 case PCI_PRODUCT_INTEL_82855GM_IGD: 242 case PCI_PRODUCT_INTEL_82865_IGD: 243 case PCI_PRODUCT_INTEL_82915G_IGD: 244 case PCI_PRODUCT_INTEL_82915GM_IGD: 245 case PCI_PRODUCT_INTEL_82945P_IGD: 246 case PCI_PRODUCT_INTEL_82945GM_IGD: 247 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 248 case PCI_PRODUCT_INTEL_82945GME_IGD: 249 case PCI_PRODUCT_INTEL_E7221_IGD: 250 case PCI_PRODUCT_INTEL_82965Q_IGD: 251 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 252 case PCI_PRODUCT_INTEL_82965PM_IGD: 253 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 254 case PCI_PRODUCT_INTEL_82G33_IGD: 255 case PCI_PRODUCT_INTEL_82G33_IGD_1: 256 case PCI_PRODUCT_INTEL_82965G_IGD: 257 case PCI_PRODUCT_INTEL_82965G_IGD_1: 258 case PCI_PRODUCT_INTEL_82965GME_IGD: 259 case PCI_PRODUCT_INTEL_82Q35_IGD: 260 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 261 case PCI_PRODUCT_INTEL_82Q33_IGD: 262 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 263 case PCI_PRODUCT_INTEL_82G35_IGD: 264 case PCI_PRODUCT_INTEL_82G35_IGD_1: 265 case PCI_PRODUCT_INTEL_82946GZ_IGD: 266 case PCI_PRODUCT_INTEL_82GM45_IGD: 267 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 268 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 269 case PCI_PRODUCT_INTEL_82Q45_IGD: 270 case PCI_PRODUCT_INTEL_82G45_IGD: 271 case PCI_PRODUCT_INTEL_82G41_IGD: 272 case PCI_PRODUCT_INTEL_82B43_IGD: 273 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 274 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 275 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 276 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 277 return (1); 278 } 279 280 return (0); 281 } 282 283 static int 284 agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg) 285 { 286 /* 287 * Find the aperture. Don't map it (yet), this would 288 * eat KVA. 289 */ 290 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 291 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize, 292 &sc->as_apflags) != 0) 293 return ENXIO; 294 295 sc->as_apt = pa->pa_memt; 296 297 return 0; 298 } 299 300 int 301 agp_i810_attach(device_t parent, device_t self, void *aux) 302 { 303 struct agp_softc *sc = device_private(self); 304 struct agp_i810_softc *isc; 305 int apbase, mmadr_bar, gtt_bar; 306 int mmadr_type, mmadr_flags; 307 bus_addr_t mmadr; 308 bus_size_t mmadr_size, gtt_off; 309 int error; 310 311 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 312 if (isc == NULL) { 313 aprint_error(": can't allocate chipset-specific softc\n"); 314 error = ENOMEM; 315 goto fail0; 316 } 317 sc->as_chipc = isc; 318 sc->as_methods = &agp_i810_methods; 319 320 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) { 321 #if NAGP_INTEL > 0 322 const struct pci_attach_args *pa = aux; 323 324 switch (PCI_PRODUCT(pa->pa_id)) { 325 case PCI_PRODUCT_INTEL_82840_HB: 326 case PCI_PRODUCT_INTEL_82865_HB: 327 case PCI_PRODUCT_INTEL_82845G_DRAM: 328 case PCI_PRODUCT_INTEL_82815_FULL_HUB: 329 case PCI_PRODUCT_INTEL_82855GM_MCH: 330 free(isc, M_AGP); 331 return agp_intel_attach(parent, self, aux); 332 } 333 #endif 334 aprint_error(": can't find internal VGA" 335 " config space\n"); 336 error = ENOENT; 337 goto fail1; 338 } 339 340 /* XXXfvdl */ 341 sc->as_dmat = isc->vga_pa.pa_dmat; 342 343 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 344 case PCI_PRODUCT_INTEL_82810_GC: 345 case PCI_PRODUCT_INTEL_82810_DC100_GC: 346 case PCI_PRODUCT_INTEL_82810E_GC: 347 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 348 isc->chiptype = CHIP_I810; 349 aprint_normal(": i810-family chipset\n"); 350 break; 351 case PCI_PRODUCT_INTEL_82830MP_IV: 352 case PCI_PRODUCT_INTEL_82845G_IGD: 353 isc->chiptype = CHIP_I830; 354 aprint_normal(": i830-family chipset\n"); 355 break; 356 case PCI_PRODUCT_INTEL_82855GM_IGD: 357 case PCI_PRODUCT_INTEL_82865_IGD: 358 isc->chiptype = CHIP_I855; 359 aprint_normal(": i855-family chipset\n"); 360 break; 361 case PCI_PRODUCT_INTEL_82915G_IGD: 362 case PCI_PRODUCT_INTEL_82915GM_IGD: 363 case PCI_PRODUCT_INTEL_82945P_IGD: 364 case PCI_PRODUCT_INTEL_82945GM_IGD: 365 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 366 case PCI_PRODUCT_INTEL_82945GME_IGD: 367 case PCI_PRODUCT_INTEL_E7221_IGD: 368 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 369 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 370 isc->chiptype = CHIP_I915; 371 aprint_normal(": i915-family chipset\n"); 372 break; 373 case PCI_PRODUCT_INTEL_82965Q_IGD: 374 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 375 case PCI_PRODUCT_INTEL_82965PM_IGD: 376 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 377 case PCI_PRODUCT_INTEL_82965G_IGD: 378 case PCI_PRODUCT_INTEL_82965G_IGD_1: 379 case PCI_PRODUCT_INTEL_82965GME_IGD: 380 case PCI_PRODUCT_INTEL_82946GZ_IGD: 381 case PCI_PRODUCT_INTEL_82G35_IGD: 382 case PCI_PRODUCT_INTEL_82G35_IGD_1: 383 isc->chiptype = CHIP_I965; 384 aprint_normal(": i965-family chipset\n"); 385 break; 386 case PCI_PRODUCT_INTEL_82Q35_IGD: 387 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 388 case PCI_PRODUCT_INTEL_82G33_IGD: 389 case PCI_PRODUCT_INTEL_82G33_IGD_1: 390 case PCI_PRODUCT_INTEL_82Q33_IGD: 391 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 392 isc->chiptype = CHIP_G33; 393 aprint_normal(": G33-family chipset\n"); 394 break; 395 case PCI_PRODUCT_INTEL_82GM45_IGD: 396 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 397 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 398 case PCI_PRODUCT_INTEL_82Q45_IGD: 399 case PCI_PRODUCT_INTEL_82G45_IGD: 400 case PCI_PRODUCT_INTEL_82G41_IGD: 401 case PCI_PRODUCT_INTEL_82B43_IGD: 402 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 403 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 404 isc->chiptype = CHIP_G4X; 405 aprint_normal(": G4X-family chipset\n"); 406 break; 407 } 408 aprint_naive("\n"); 409 410 mmadr_type = PCI_MAPREG_TYPE_MEM; 411 switch (isc->chiptype) { 412 case CHIP_I915: 413 case CHIP_G33: 414 apbase = AGP_I915_GMADR; 415 mmadr_bar = AGP_I915_MMADR; 416 isc->size = 512*1024; 417 gtt_bar = AGP_I915_GTTADR; 418 gtt_off = ~(bus_size_t)0; /* XXXGCC */ 419 break; 420 case CHIP_I965: 421 apbase = AGP_I965_GMADR; 422 mmadr_bar = AGP_I965_MMADR; 423 mmadr_type |= PCI_MAPREG_MEM_TYPE_64BIT; 424 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, 425 AGP_I965_MMADR, mmadr_type, NULL, &isc->size, NULL)) 426 isc->size = 512*1024; /* XXX */ 427 gtt_bar = 0; 428 gtt_off = AGP_I965_GTT; 429 break; 430 case CHIP_G4X: 431 apbase = AGP_I965_GMADR; 432 mmadr_bar = AGP_I965_MMADR; 433 mmadr_type |= PCI_MAPREG_MEM_TYPE_64BIT; 434 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, 435 AGP_I965_MMADR, mmadr_type, NULL, &isc->size, NULL)) 436 isc->size = 512*1024; /* XXX */ 437 gtt_bar = 0; 438 gtt_off = AGP_G4X_GTT; 439 break; 440 default: 441 apbase = AGP_I810_GMADR; 442 mmadr_bar = AGP_I810_MMADR; 443 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, 444 AGP_I810_MMADR, mmadr_type, NULL, &isc->size, NULL)) 445 isc->size = 512*1024; /* XXX */ 446 gtt_bar = 0; 447 gtt_off = AGP_I810_GTT; 448 break; 449 } 450 451 /* Map (or, rather, find the address and size of) the aperture. */ 452 if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) 453 error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase); 454 else 455 error = agp_map_aperture(&isc->vga_pa, sc, apbase); 456 if (error) { 457 aprint_error_dev(self, "can't map aperture: %d\n", error); 458 goto fail1; 459 } 460 461 /* Map the memory-mapped I/O registers, or the non-GTT part. */ 462 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, mmadr_bar, 463 mmadr_type, &mmadr, &mmadr_size, &mmadr_flags)) { 464 aprint_error_dev(self, "can't find MMIO registers\n"); 465 error = ENXIO; 466 goto fail1; 467 } 468 if (mmadr_size < isc->size) { 469 aprint_error_dev(self, "MMIO registers too small" 470 ": %"PRIuMAX" < %"PRIuMAX"\n", 471 (uintmax_t)mmadr_size, (uintmax_t)isc->size); 472 error = ENXIO; 473 goto fail1; 474 } 475 isc->bst = isc->vga_pa.pa_memt; 476 error = bus_space_map(isc->bst, mmadr, isc->size, mmadr_flags, 477 &isc->bsh); 478 if (error) { 479 aprint_error_dev(self, "can't map MMIO registers: %d\n", 480 error); 481 error = ENXIO; 482 goto fail1; 483 } 484 485 /* Set up a chipset flush page if necessary. */ 486 switch (isc->chiptype) { 487 case CHIP_I915: 488 case CHIP_I965: 489 case CHIP_G33: 490 case CHIP_G4X: 491 error = agp_i810_setup_chipset_flush_page(sc); 492 if (error) { 493 aprint_error_dev(self, 494 "can't set up chipset flush page: %d\n", error); 495 goto fail2; 496 } 497 break; 498 } 499 500 /* 501 * XXX horrible hack to allow drm code to use our mapping 502 * of VGA chip registers 503 */ 504 agp_i810_vga_regbase = mmadr; 505 agp_i810_vga_regsize = isc->size; 506 agp_i810_vga_bst = isc->bst; 507 agp_i810_vga_bsh = isc->bsh; 508 509 /* Initialize the chipset. */ 510 error = agp_i810_init(sc); 511 if (error) 512 goto fail3; 513 514 /* Map the GTT, from either part of the MMIO region or its own BAR. */ 515 if (gtt_bar == 0) { 516 isc->gtt_bst = isc->bst; 517 if ((mmadr_size - gtt_off) < isc->gtt_size) { 518 aprint_error_dev(self, "GTTMMADR too small for GTT" 519 ": (%"PRIxMAX" - %"PRIxMAX") < %"PRIxMAX"\n", 520 (uintmax_t)mmadr_size, 521 (uintmax_t)gtt_off, 522 (uintmax_t)isc->gtt_size); 523 error = ENXIO; 524 goto fail4; 525 } 526 /* 527 * Map the GTT separately if we can, so that we can map 528 * it prefetchable, but in early models, there are MMIO 529 * registers before and after the GTT, so we can only 530 * take a subregion. 531 */ 532 if (isc->size < gtt_off) 533 error = bus_space_map(isc->gtt_bst, (mmadr + gtt_off), 534 isc->gtt_size, mmadr_flags, &isc->gtt_bsh); 535 else 536 error = bus_space_subregion(isc->bst, isc->bsh, 537 gtt_off, isc->gtt_size, &isc->gtt_bsh); 538 if (error) { 539 aprint_error_dev(self, "can't map GTT: %d\n", error); 540 error = ENXIO; 541 goto fail4; 542 } 543 } else { 544 bus_size_t gtt_bar_size; 545 /* 546 * All chipsets with a separate BAR for the GTT, namely 547 * the i915 and G33 families, have 32-bit GTT BARs. 548 * 549 * XXX [citation needed] 550 */ 551 if (pci_mapreg_map(&isc->vga_pa, gtt_bar, PCI_MAPREG_TYPE_MEM, 552 0, 553 &isc->gtt_bst, &isc->gtt_bsh, NULL, >t_bar_size)) { 554 aprint_error_dev(self, "can't map GTT\n"); 555 error = ENXIO; 556 goto fail4; 557 } 558 if (gtt_bar_size != isc->gtt_size) { 559 aprint_error_dev(self, 560 "BAR size %"PRIxMAX 561 " mismatches detected GTT size %"PRIxMAX 562 "; trusting BAR\n", 563 (uintmax_t)gtt_bar_size, 564 (uintmax_t)isc->gtt_size); 565 isc->gtt_size = gtt_bar_size; 566 } 567 } 568 569 /* Power management. (XXX Nothing to save on suspend? Fishy...) */ 570 if (!pmf_device_register(self, NULL, agp_i810_resume)) 571 aprint_error_dev(self, "can't establish power handler\n"); 572 573 /* Match the generic AGP code's autoconf output format. */ 574 aprint_normal("%s", device_xname(self)); 575 576 /* Success! */ 577 return 0; 578 579 fail5: __unused 580 pmf_device_deregister(self); 581 if ((gtt_bar != 0) || (isc->size < gtt_off)) 582 bus_space_unmap(isc->gtt_bst, isc->gtt_bsh, isc->gtt_size); 583 isc->gtt_size = 0; 584 fail4: 585 #if notyet 586 agp_i810_fini(sc); 587 #endif 588 fail3: switch (isc->chiptype) { 589 case CHIP_I915: 590 case CHIP_I965: 591 case CHIP_G33: 592 case CHIP_G4X: 593 agp_i810_teardown_chipset_flush_page(sc); 594 break; 595 } 596 fail2: bus_space_unmap(isc->bst, isc->bsh, isc->size); 597 isc->size = 0; 598 fail1: free(isc, M_AGP); 599 sc->as_chipc = NULL; 600 fail0: agp_generic_detach(sc); 601 KASSERT(error); 602 return error; 603 } 604 605 /* 606 * Skip pages reserved by the BIOS. Notably, skip 0xa0000-0xfffff, 607 * which includes the video BIOS at 0xc0000-0xdffff which the display 608 * drivers need for video mode detection. 609 * 610 * XXX Is there an MI name for this, or a conventional x86 name? Or 611 * should we really use bus_dma instead? 612 */ 613 #define PCIBIOS_MIN_MEM 0x100000 614 615 static int 616 agp_i810_setup_chipset_flush_page(struct agp_softc *sc) 617 { 618 struct agp_i810_softc *const isc = sc->as_chipc; 619 const pci_chipset_tag_t pc = sc->as_pc; 620 const pcitag_t tag = sc->as_tag; 621 pcireg_t lo, hi; 622 bus_addr_t addr, minaddr, maxaddr; 623 int error; 624 625 /* We always use memory-mapped I/O. */ 626 isc->flush_bst = isc->vga_pa.pa_memt; 627 628 /* No page allocated yet. */ 629 isc->flush_addr = 0; 630 631 /* Read the PCI config register: 4-byte on gen3, 8-byte on gen>=4. */ 632 if (isc->chiptype == CHIP_I915) { 633 addr = pci_conf_read(pc, tag, AGP_I915_IFPADDR); 634 minaddr = PCIBIOS_MIN_MEM; 635 maxaddr = UINT32_MAX; 636 } else { 637 hi = pci_conf_read(pc, tag, AGP_I965_IFPADDR+4); 638 lo = pci_conf_read(pc, tag, AGP_I965_IFPADDR); 639 /* 640 * Convert to uint64_t, rather than bus_addr_t which 641 * may be 32-bit, to avoid undefined behaviour with a 642 * too-wide shift. Since the BIOS doesn't know whether 643 * the OS will run 64-bit or with PAE, it ought to 644 * configure at most a 32-bit physical address, so 645 * let's print a warning in case that happens. 646 */ 647 addr = ((uint64_t)hi << 32) | lo; 648 if (hi) { 649 aprint_error_dev(sc->as_dev, 650 "BIOS configured >32-bit flush page address" 651 ": %"PRIx64"\n", ((uint64_t)hi << 32) | lo); 652 #if __i386__ && !PAE 653 return EIO; 654 #endif 655 } 656 minaddr = PCIBIOS_MIN_MEM; 657 maxaddr = MIN(UINT64_MAX, ~(bus_addr_t)0); 658 } 659 660 /* Allocate or map a pre-allocated a page for it. */ 661 if (ISSET(addr, 1)) { 662 /* BIOS allocated it for us. Use that. */ 663 error = bus_space_map(isc->flush_bst, addr & ~1, PAGE_SIZE, 0, 664 &isc->flush_bsh); 665 if (error) 666 return error; 667 } else { 668 /* None allocated. Allocate one. */ 669 error = bus_space_alloc(isc->flush_bst, minaddr, maxaddr, 670 PAGE_SIZE, PAGE_SIZE, 0, 0, 671 &isc->flush_addr, &isc->flush_bsh); 672 if (error) 673 return error; 674 KASSERT(isc->flush_addr != 0); 675 /* Write it into the PCI config register. */ 676 addr = isc->flush_addr | 1; 677 if (isc->chiptype == CHIP_I915) { 678 pci_conf_write(pc, tag, AGP_I915_IFPADDR, addr); 679 } else { 680 hi = __SHIFTOUT(addr, __BITS(63, 32)); 681 lo = __SHIFTOUT(addr, __BITS(31, 0)); 682 pci_conf_write(pc, tag, AGP_I965_IFPADDR+4, hi); 683 pci_conf_write(pc, tag, AGP_I965_IFPADDR, lo); 684 } 685 } 686 687 /* Success! */ 688 return 0; 689 } 690 691 static void 692 agp_i810_teardown_chipset_flush_page(struct agp_softc *sc) 693 { 694 struct agp_i810_softc *const isc = sc->as_chipc; 695 696 if (isc->flush_addr) { 697 /* If we allocated a page, clear it. */ 698 if (isc->chiptype == CHIP_I915) { 699 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR, 700 0); 701 } else { 702 pci_conf_write(sc->as_pc, sc->as_tag, 703 AGP_I965_IFPADDR, 0); 704 pci_conf_write(sc->as_pc, sc->as_tag, 705 AGP_I965_IFPADDR + 4, 0); 706 } 707 isc->flush_addr = 0; 708 bus_space_free(isc->flush_bst, isc->flush_bsh, PAGE_SIZE); 709 } else { 710 /* Otherwise, just unmap the pre-allocated page. */ 711 bus_space_unmap(isc->flush_bst, isc->flush_bsh, PAGE_SIZE); 712 } 713 } 714 715 /* 716 * XXX horrible hack to allow drm code to use our mapping 717 * of VGA chip registers 718 */ 719 int 720 agp_i810_borrow(bus_addr_t base, bus_size_t size, bus_space_handle_t *hdlp) 721 { 722 723 if (agp_i810_vga_regbase == 0) 724 return 0; 725 if (base < agp_i810_vga_regbase) 726 return 0; 727 if (agp_i810_vga_regsize < size) 728 return 0; 729 if ((base - agp_i810_vga_regbase) > (agp_i810_vga_regsize - size)) 730 return 0; 731 if (bus_space_subregion(agp_i810_vga_bst, agp_i810_vga_bsh, 732 (base - agp_i810_vga_regbase), (agp_i810_vga_regsize - size), 733 hdlp)) 734 return 0; 735 return 1; 736 } 737 738 static int 739 agp_i810_init(struct agp_softc *sc) 740 { 741 struct agp_i810_softc *isc; 742 int error; 743 744 isc = sc->as_chipc; 745 746 if (isc->chiptype == CHIP_I810) { 747 struct agp_gatt *gatt; 748 void *virtual; 749 int dummyseg; 750 751 /* Some i810s have on-chip memory called dcache */ 752 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 753 isc->dcache_size = 4 * 1024 * 1024; 754 else 755 isc->dcache_size = 0; 756 757 /* According to the specs the gatt on the i810 must be 64k */ 758 isc->gtt_size = 64 * 1024; 759 gatt = malloc(sizeof(*gatt), M_AGP, M_NOWAIT); 760 if (gatt == NULL) { 761 aprint_error_dev(sc->as_dev, 762 "can't malloc GATT record\n"); 763 error = ENOMEM; 764 goto fail0; 765 } 766 gatt->ag_entries = isc->gtt_size / sizeof(uint32_t); 767 error = agp_alloc_dmamem(sc->as_dmat, isc->gtt_size, 768 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical, 769 &gatt->ag_dmaseg, 1, &dummyseg); 770 if (error) { 771 aprint_error_dev(sc->as_dev, 772 "can't allocate memory for GTT: %d\n", error); 773 free(gatt, M_AGP); 774 goto fail0; 775 } 776 777 gatt->ag_virtual = (uint32_t *)virtual; 778 gatt->ag_size = gatt->ag_entries * sizeof(uint32_t); 779 memset(gatt->ag_virtual, 0, gatt->ag_size); 780 agp_flush_cache(); 781 782 /* Install the GATT. */ 783 isc->pgtblctl = gatt->ag_physical | 1; 784 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 785 isc->gatt = gatt; 786 } else if (isc->chiptype == CHIP_I830) { 787 /* The i830 automatically initializes the 128k gatt on boot. */ 788 /* XXX [citation needed] */ 789 pcireg_t reg; 790 u_int16_t gcc1; 791 792 isc->gtt_size = 128 * 1024; 793 794 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 795 gcc1 = (u_int16_t)(reg >> 16); 796 switch (gcc1 & AGP_I830_GCC1_GMS) { 797 case AGP_I830_GCC1_GMS_STOLEN_512: 798 isc->stolen = (512 - 132) * 1024 / 4096; 799 break; 800 case AGP_I830_GCC1_GMS_STOLEN_1024: 801 isc->stolen = (1024 - 132) * 1024 / 4096; 802 break; 803 case AGP_I830_GCC1_GMS_STOLEN_8192: 804 isc->stolen = (8192 - 132) * 1024 / 4096; 805 break; 806 default: 807 isc->stolen = 0; 808 aprint_error_dev(sc->as_dev, 809 "unknown memory configuration, disabling\n"); 810 error = ENXIO; 811 goto fail0; 812 } 813 814 if (isc->stolen > 0) { 815 aprint_normal_dev(sc->as_dev, 816 "detected %dk stolen memory\n", 817 isc->stolen * 4); 818 } 819 820 /* GATT address is already in there, make sure it's enabled */ 821 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 822 isc->pgtblctl |= 1; 823 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 824 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 825 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 || 826 isc->chiptype == CHIP_G4X) { 827 pcireg_t reg; 828 u_int32_t gtt_size, stolen; /* XXX kilobytes */ 829 u_int16_t gcc1; 830 831 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1); 832 gcc1 = (u_int16_t)(reg >> 16); 833 834 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 835 836 /* Stolen memory is set up at the beginning of the aperture by 837 * the BIOS, consisting of the GATT followed by 4kb for the 838 * BIOS display. 839 */ 840 switch (isc->chiptype) { 841 case CHIP_I855: 842 gtt_size = 128; 843 break; 844 case CHIP_I915: 845 gtt_size = 256; 846 break; 847 case CHIP_I965: 848 switch (isc->pgtblctl & AGP_I810_PGTBL_SIZE_MASK) { 849 case AGP_I810_PGTBL_SIZE_128KB: 850 case AGP_I810_PGTBL_SIZE_512KB: 851 gtt_size = 512; 852 break; 853 case AGP_I965_PGTBL_SIZE_1MB: 854 gtt_size = 1024; 855 break; 856 case AGP_I965_PGTBL_SIZE_2MB: 857 gtt_size = 2048; 858 break; 859 case AGP_I965_PGTBL_SIZE_1_5MB: 860 gtt_size = 1024 + 512; 861 break; 862 default: 863 aprint_error_dev(sc->as_dev, 864 "bad PGTBL size\n"); 865 error = ENXIO; 866 goto fail0; 867 } 868 break; 869 case CHIP_G33: 870 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 871 case AGP_G33_PGTBL_SIZE_1M: 872 gtt_size = 1024; 873 break; 874 case AGP_G33_PGTBL_SIZE_2M: 875 gtt_size = 2048; 876 break; 877 default: 878 aprint_error_dev(sc->as_dev, 879 "bad PGTBL size\n"); 880 error = ENXIO; 881 goto fail0; 882 } 883 break; 884 case CHIP_G4X: 885 switch (isc->pgtblctl & AGP_G4X_PGTBL_SIZE_MASK) { 886 case AGP_G4X_PGTBL_SIZE_512K: 887 gtt_size = 512; 888 break; 889 case AGP_G4X_PGTBL_SIZE_256K: 890 gtt_size = 256; 891 break; 892 case AGP_G4X_PGTBL_SIZE_128K: 893 gtt_size = 128; 894 break; 895 case AGP_G4X_PGTBL_SIZE_1M: 896 gtt_size = 1*1024; 897 break; 898 case AGP_G4X_PGTBL_SIZE_2M: 899 gtt_size = 2*1024; 900 break; 901 case AGP_G4X_PGTBL_SIZE_1_5M: 902 gtt_size = 1*1024 + 512; 903 break; 904 default: 905 aprint_error_dev(sc->as_dev, 906 "bad PGTBL size\n"); 907 error = ENXIO; 908 goto fail0; 909 } 910 break; 911 default: 912 panic("impossible chiptype %d", isc->chiptype); 913 } 914 915 /* 916 * XXX If I'm reading the datasheets right, this stolen 917 * memory detection logic is totally wrong. 918 */ 919 switch (gcc1 & AGP_I855_GCC1_GMS) { 920 case AGP_I855_GCC1_GMS_STOLEN_1M: 921 stolen = 1024; 922 break; 923 case AGP_I855_GCC1_GMS_STOLEN_4M: 924 stolen = 4 * 1024; 925 break; 926 case AGP_I855_GCC1_GMS_STOLEN_8M: 927 stolen = 8 * 1024; 928 break; 929 case AGP_I855_GCC1_GMS_STOLEN_16M: 930 stolen = 16 * 1024; 931 break; 932 case AGP_I855_GCC1_GMS_STOLEN_32M: 933 stolen = 32 * 1024; 934 break; 935 case AGP_I915_GCC1_GMS_STOLEN_48M: 936 stolen = 48 * 1024; 937 break; 938 case AGP_I915_GCC1_GMS_STOLEN_64M: 939 stolen = 64 * 1024; 940 break; 941 case AGP_G33_GCC1_GMS_STOLEN_128M: 942 stolen = 128 * 1024; 943 break; 944 case AGP_G33_GCC1_GMS_STOLEN_256M: 945 stolen = 256 * 1024; 946 break; 947 case AGP_G4X_GCC1_GMS_STOLEN_96M: 948 stolen = 96 * 1024; 949 break; 950 case AGP_G4X_GCC1_GMS_STOLEN_160M: 951 stolen = 160 * 1024; 952 break; 953 case AGP_G4X_GCC1_GMS_STOLEN_224M: 954 stolen = 224 * 1024; 955 break; 956 case AGP_G4X_GCC1_GMS_STOLEN_352M: 957 stolen = 352 * 1024; 958 break; 959 default: 960 aprint_error_dev(sc->as_dev, 961 "unknown memory configuration, disabling\n"); 962 error = ENXIO; 963 goto fail0; 964 } 965 966 switch (gcc1 & AGP_I855_GCC1_GMS) { 967 case AGP_I915_GCC1_GMS_STOLEN_48M: 968 case AGP_I915_GCC1_GMS_STOLEN_64M: 969 if (isc->chiptype != CHIP_I915 && 970 isc->chiptype != CHIP_I965 && 971 isc->chiptype != CHIP_G33 && 972 isc->chiptype != CHIP_G4X) 973 stolen = 0; 974 break; 975 case AGP_G33_GCC1_GMS_STOLEN_128M: 976 case AGP_G33_GCC1_GMS_STOLEN_256M: 977 if (isc->chiptype != CHIP_I965 && 978 isc->chiptype != CHIP_G33 && 979 isc->chiptype != CHIP_G4X) 980 stolen = 0; 981 break; 982 case AGP_G4X_GCC1_GMS_STOLEN_96M: 983 case AGP_G4X_GCC1_GMS_STOLEN_160M: 984 case AGP_G4X_GCC1_GMS_STOLEN_224M: 985 case AGP_G4X_GCC1_GMS_STOLEN_352M: 986 if (isc->chiptype != CHIP_I965 && 987 isc->chiptype != CHIP_G4X) 988 stolen = 0; 989 break; 990 } 991 992 isc->gtt_size = gtt_size * 1024; 993 994 /* BIOS space */ 995 /* XXX [citation needed] */ 996 gtt_size += 4; 997 998 /* XXX [citation needed] for this subtraction */ 999 isc->stolen = (stolen - gtt_size) * 1024 / 4096; 1000 1001 if (isc->stolen > 0) { 1002 aprint_normal_dev(sc->as_dev, 1003 "detected %dk stolen memory\n", 1004 isc->stolen * 4); 1005 } 1006 1007 /* GATT address is already in there, make sure it's enabled */ 1008 isc->pgtblctl |= 1; 1009 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 1010 } 1011 1012 /* 1013 * Make sure the chipset can see everything. 1014 */ 1015 agp_flush_cache(); 1016 1017 /* 1018 * Publish what we found for kludgey drivers (I'm looking at 1019 * you, drm). 1020 */ 1021 if (agp_i810_sc == NULL) 1022 agp_i810_sc = sc; 1023 else 1024 aprint_error_dev(sc->as_dev, "agp already attached\n"); 1025 1026 /* Success! */ 1027 return 0; 1028 1029 fail0: KASSERT(error); 1030 return error; 1031 } 1032 1033 #if 0 1034 static int 1035 agp_i810_detach(struct agp_softc *sc) 1036 { 1037 int error; 1038 struct agp_i810_softc *isc = sc->as_chipc; 1039 1040 error = agp_generic_detach(sc); 1041 if (error) 1042 return error; 1043 1044 switch (isc->chiptype) { 1045 case CHIP_I915: 1046 case CHIP_I965: 1047 case CHIP_G33: 1048 case CHIP_G4X: 1049 agp_i810_teardown_chipset_flush_page(sc); 1050 break; 1051 } 1052 1053 /* Clear the GATT base. */ 1054 if (sc->chiptype == CHIP_I810) { 1055 WRITE4(AGP_I810_PGTBL_CTL, 0); 1056 } else { 1057 unsigned int pgtblctl; 1058 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 1059 pgtblctl &= ~1; 1060 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 1061 } 1062 1063 if (sc->chiptype == CHIP_I810) { 1064 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap, 1065 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 1066 free(isc->gatt, M_AGP); 1067 } 1068 1069 return 0; 1070 } 1071 #endif 1072 1073 static u_int32_t 1074 agp_i810_get_aperture(struct agp_softc *sc) 1075 { 1076 struct agp_i810_softc *isc = sc->as_chipc; 1077 pcireg_t reg; 1078 u_int32_t size; 1079 u_int16_t miscc, gcc1; 1080 1081 size = 0; 1082 1083 switch (isc->chiptype) { 1084 case CHIP_I810: 1085 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 1086 miscc = (u_int16_t)(reg >> 16); 1087 if ((miscc & AGP_I810_MISCC_WINSIZE) == 1088 AGP_I810_MISCC_WINSIZE_32) 1089 size = 32 * 1024 * 1024; 1090 else 1091 size = 64 * 1024 * 1024; 1092 break; 1093 case CHIP_I830: 1094 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 1095 gcc1 = (u_int16_t)(reg >> 16); 1096 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 1097 size = 64 * 1024 * 1024; 1098 else 1099 size = 128 * 1024 * 1024; 1100 break; 1101 case CHIP_I855: 1102 size = 128 * 1024 * 1024; 1103 break; 1104 case CHIP_I915: 1105 case CHIP_G33: 1106 case CHIP_G4X: 1107 size = sc->as_apsize; 1108 break; 1109 case CHIP_I965: 1110 size = 512 * 1024 * 1024; 1111 break; 1112 default: 1113 aprint_error(": Unknown chipset\n"); 1114 } 1115 1116 return size; 1117 } 1118 1119 static int 1120 agp_i810_set_aperture(struct agp_softc *sc __unused, 1121 uint32_t aperture __unused) 1122 { 1123 1124 return ENOSYS; 1125 } 1126 1127 static int 1128 agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 1129 { 1130 struct agp_i810_softc *isc = sc->as_chipc; 1131 1132 if (offset < 0 || offset >= ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) { 1133 DPRINTF(sc, "failed" 1134 ": offset 0x%"PRIxMAX", shift %u, entries %"PRIuMAX"\n", 1135 (uintmax_t)offset, 1136 (unsigned)AGP_PAGE_SHIFT, 1137 (uintmax_t)isc->gtt_size/4); 1138 return EINVAL; 1139 } 1140 1141 if (isc->chiptype != CHIP_I810) { 1142 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1143 DPRINTF(sc, "trying to bind into stolen memory\n"); 1144 return EINVAL; 1145 } 1146 } 1147 1148 return agp_i810_write_gtt_entry(isc, offset, physical, 1149 AGP_I810_GTT_VALID); 1150 } 1151 1152 static int 1153 agp_i810_unbind_page(struct agp_softc *sc, off_t offset) 1154 { 1155 struct agp_i810_softc *isc = sc->as_chipc; 1156 1157 if (offset < 0 || offset >= ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) 1158 return EINVAL; 1159 1160 if (isc->chiptype != CHIP_I810 ) { 1161 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1162 DPRINTF(sc, "trying to unbind from stolen memory\n"); 1163 return EINVAL; 1164 } 1165 } 1166 1167 return agp_i810_write_gtt_entry(isc, offset, 0, 0); 1168 } 1169 1170 /* 1171 * Writing via memory mapped registers already flushes all TLBs. 1172 */ 1173 static void 1174 agp_i810_flush_tlb(struct agp_softc *sc) 1175 { 1176 } 1177 1178 static int 1179 agp_i810_enable(struct agp_softc *sc, u_int32_t mode) 1180 { 1181 1182 return 0; 1183 } 1184 1185 #define AGP_I810_MEMTYPE_MAIN 0 1186 #define AGP_I810_MEMTYPE_DCACHE 1 1187 #define AGP_I810_MEMTYPE_HWCURSOR 2 1188 1189 static struct agp_memory * 1190 agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size) 1191 { 1192 struct agp_i810_softc *isc = sc->as_chipc; 1193 struct agp_memory *mem; 1194 int error; 1195 1196 DPRINTF(sc, "AGP: alloc(%d, 0x%"PRIxMAX")\n", type, (uintmax_t)size); 1197 1198 if (size <= 0) 1199 return NULL; 1200 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 1201 return NULL; 1202 KASSERT(sc->as_allocated <= sc->as_maxmem); 1203 if (size > (sc->as_maxmem - sc->as_allocated)) 1204 return NULL; 1205 if (size > ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) 1206 return NULL; 1207 1208 switch (type) { 1209 case AGP_I810_MEMTYPE_MAIN: 1210 break; 1211 case AGP_I810_MEMTYPE_DCACHE: 1212 if (isc->chiptype != CHIP_I810) 1213 return NULL; 1214 if (size != isc->dcache_size) 1215 return NULL; 1216 break; 1217 case AGP_I810_MEMTYPE_HWCURSOR: 1218 if ((size != AGP_PAGE_SIZE) && 1219 (size != AGP_PAGE_SIZE*4)) 1220 return NULL; 1221 break; 1222 default: 1223 return NULL; 1224 } 1225 1226 mem = malloc(sizeof(*mem), M_AGP, M_WAITOK|M_ZERO); 1227 if (mem == NULL) 1228 goto fail0; 1229 mem->am_id = sc->as_nextid++; 1230 mem->am_size = size; 1231 mem->am_type = type; 1232 1233 switch (type) { 1234 case AGP_I810_MEMTYPE_MAIN: 1235 error = bus_dmamap_create(sc->as_dmat, size, 1236 (size >> AGP_PAGE_SHIFT) + 1, size, 0, BUS_DMA_WAITOK, 1237 &mem->am_dmamap); 1238 if (error) 1239 goto fail1; 1240 break; 1241 case AGP_I810_MEMTYPE_DCACHE: 1242 break; 1243 case AGP_I810_MEMTYPE_HWCURSOR: 1244 mem->am_dmaseg = malloc(sizeof(*mem->am_dmaseg), M_AGP, 1245 M_WAITOK); 1246 error = agp_alloc_dmamem(sc->as_dmat, size, 0, &mem->am_dmamap, 1247 &mem->am_virtual, &mem->am_physical, mem->am_dmaseg, 1, 1248 &mem->am_nseg); 1249 if (error) { 1250 free(mem->am_dmaseg, M_AGP); 1251 goto fail1; 1252 } 1253 (void)memset(mem->am_virtual, 0, size); 1254 break; 1255 default: 1256 panic("invalid agp memory type: %d", type); 1257 } 1258 1259 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link); 1260 sc->as_allocated += size; 1261 1262 return mem; 1263 1264 fail1: free(mem, M_AGP); 1265 fail0: return NULL; 1266 } 1267 1268 static int 1269 agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem) 1270 { 1271 1272 if (mem->am_is_bound) 1273 return EBUSY; 1274 1275 switch (mem->am_type) { 1276 case AGP_I810_MEMTYPE_MAIN: 1277 bus_dmamap_destroy(sc->as_dmat, mem->am_dmamap); 1278 break; 1279 case AGP_I810_MEMTYPE_DCACHE: 1280 break; 1281 case AGP_I810_MEMTYPE_HWCURSOR: 1282 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap, 1283 mem->am_virtual, mem->am_dmaseg, mem->am_nseg); 1284 free(mem->am_dmaseg, M_AGP); 1285 break; 1286 default: 1287 panic("invalid agp i810 memory type: %d", mem->am_type); 1288 } 1289 1290 sc->as_allocated -= mem->am_size; 1291 TAILQ_REMOVE(&sc->as_memory, mem, am_link); 1292 free(mem, M_AGP); 1293 1294 return 0; 1295 } 1296 1297 static int 1298 agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem, 1299 off_t offset) 1300 { 1301 struct agp_i810_softc *isc = sc->as_chipc; 1302 uint32_t pgtblctl; 1303 int error; 1304 1305 if (mem->am_is_bound) 1306 return EINVAL; 1307 1308 /* 1309 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 1310 * X server for mysterious reasons which leads to crashes if we write 1311 * to the GTT through the MMIO window. 1312 * Until the issue is solved, simply restore it. 1313 */ 1314 pgtblctl = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL); 1315 if (pgtblctl != isc->pgtblctl) { 1316 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%"PRIx32 1317 " - fixing\n", pgtblctl); 1318 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 1319 isc->pgtblctl); 1320 } 1321 1322 switch (mem->am_type) { 1323 case AGP_I810_MEMTYPE_MAIN: 1324 return agp_generic_bind_memory_bounded(sc, mem, offset, 1325 0, (isc->gtt_size/4) << AGP_PAGE_SHIFT); 1326 case AGP_I810_MEMTYPE_DCACHE: 1327 error = agp_i810_bind_memory_dcache(sc, mem, offset); 1328 break; 1329 case AGP_I810_MEMTYPE_HWCURSOR: 1330 error = agp_i810_bind_memory_hwcursor(sc, mem, offset); 1331 break; 1332 default: 1333 panic("invalid agp i810 memory type: %d", mem->am_type); 1334 } 1335 if (error) 1336 return error; 1337 1338 /* Success! */ 1339 mem->am_is_bound = 1; 1340 return 0; 1341 } 1342 1343 static int 1344 agp_i810_bind_memory_dcache(struct agp_softc *sc, struct agp_memory *mem, 1345 off_t offset) 1346 { 1347 struct agp_i810_softc *const isc __diagused = sc->as_chipc; 1348 uint32_t i, j; 1349 int error; 1350 1351 KASSERT(isc->chiptype == CHIP_I810); 1352 1353 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0); 1354 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 1355 error = agp_i810_write_gtt_entry(isc, offset + i, 1356 i, AGP_I810_GTT_VALID | AGP_I810_GTT_I810_DCACHE); 1357 if (error) 1358 goto fail0; 1359 } 1360 1361 /* Success! */ 1362 mem->am_offset = offset; 1363 return 0; 1364 1365 fail0: for (j = 0; j < i; j += AGP_PAGE_SIZE) 1366 (void)agp_i810_unbind_page(sc, offset + j); 1367 return error; 1368 } 1369 1370 static int 1371 agp_i810_bind_memory_hwcursor(struct agp_softc *sc, struct agp_memory *mem, 1372 off_t offset) 1373 { 1374 const bus_addr_t pa = mem->am_physical; 1375 uint32_t i, j; 1376 int error; 1377 1378 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0); 1379 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 1380 error = agp_i810_bind_page(sc, offset + i, pa + i); 1381 if (error) 1382 goto fail0; 1383 } 1384 1385 /* Success! */ 1386 mem->am_offset = offset; 1387 return 0; 1388 1389 fail0: for (j = 0; j < i; j += AGP_PAGE_SIZE) 1390 (void)agp_i810_unbind_page(sc, offset + j); 1391 return error; 1392 } 1393 1394 static int 1395 agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem) 1396 { 1397 struct agp_i810_softc *isc __diagused = sc->as_chipc; 1398 u_int32_t i; 1399 1400 if (!mem->am_is_bound) 1401 return EINVAL; 1402 1403 switch (mem->am_type) { 1404 case AGP_I810_MEMTYPE_MAIN: 1405 return agp_generic_unbind_memory(sc, mem); 1406 case AGP_I810_MEMTYPE_DCACHE: 1407 KASSERT(isc->chiptype == CHIP_I810); 1408 /* FALLTHROUGH */ 1409 case AGP_I810_MEMTYPE_HWCURSOR: 1410 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1411 (void)agp_i810_unbind_page(sc, mem->am_offset + i); 1412 mem->am_offset = 0; 1413 break; 1414 default: 1415 panic("invalid agp i810 memory type: %d", mem->am_type); 1416 } 1417 1418 mem->am_is_bound = 0; 1419 return 0; 1420 } 1421 1422 static bool 1423 agp_i810_resume(device_t dv, const pmf_qual_t *qual) 1424 { 1425 struct agp_softc *sc = device_private(dv); 1426 struct agp_i810_softc *isc = sc->as_chipc; 1427 1428 /* 1429 * XXX Nothing uses this! Save on suspend, restore on resume? 1430 */ 1431 isc->pgtblctl_resume_hack = READ4(AGP_I810_PGTBL_CTL); 1432 agp_flush_cache(); 1433 1434 return true; 1435 } 1436
Indexes created Tue Oct 07 21:09:53 GMT 2025