agp_i810.c revision 1.113
1 /* $NetBSD: agp_i810.c,v 1.113 2014/08/22 15:26:28 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.113 2014/08/22 15:26:28 riastradh Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/proc.h> 40 #include <sys/device.h> 41 #include <sys/conf.h> 42 #include <sys/xcall.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcidevs.h> 47 #include <dev/pci/agpvar.h> 48 #include <dev/pci/agpreg.h> 49 #include <dev/pci/agp_i810var.h> 50 51 #include <sys/agpio.h> 52 53 #include <sys/bus.h> 54 55 #include "agp_intel.h" 56 57 #ifdef AGP_DEBUG 58 #define DPRINTF(sc, fmt, ...) \ 59 device_printf((sc)->as_dev, "%s: " fmt, __func__, ##__VA_ARGS__) 60 #else 61 #define DPRINTF(sc, fmt, ...) do {} while (0) 62 #endif 63 64 struct agp_softc *agp_i810_sc = NULL; 65 66 #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off) 67 #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off) 68 #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v) 69 70 #define CHIP_I810 0 /* i810/i815 */ 71 #define CHIP_I830 1 /* 830M/845G */ 72 #define CHIP_I855 2 /* 852GM/855GM/865G */ 73 #define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */ 74 #define CHIP_I965 4 /* 965Q/965PM */ 75 #define CHIP_G33 5 /* G33/Q33/Q35 */ 76 #define CHIP_G4X 6 /* G45/Q45 */ 77 78 /* XXX hack, see below */ 79 static bus_addr_t agp_i810_vga_regbase; 80 static bus_size_t agp_i810_vga_regsize; 81 static bus_space_tag_t agp_i810_vga_bst; 82 static bus_space_handle_t agp_i810_vga_bsh; 83 84 static u_int32_t agp_i810_get_aperture(struct agp_softc *); 85 static int agp_i810_set_aperture(struct agp_softc *, u_int32_t); 86 static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t); 87 static int agp_i810_unbind_page(struct agp_softc *, off_t); 88 static void agp_i810_flush_tlb(struct agp_softc *); 89 static int agp_i810_enable(struct agp_softc *, u_int32_t mode); 90 static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int, 91 vsize_t); 92 static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *); 93 static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, 94 off_t); 95 static int agp_i810_bind_memory_dcache(struct agp_softc *, struct agp_memory *, 96 off_t); 97 static int agp_i810_bind_memory_hwcursor(struct agp_softc *, 98 struct agp_memory *, off_t); 99 static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *); 100 101 static bool agp_i810_resume(device_t, const pmf_qual_t *); 102 static int agp_i810_init(struct agp_softc *); 103 104 static int agp_i810_setup_chipset_flush_page(struct agp_softc *); 105 static void agp_i810_teardown_chipset_flush_page(struct agp_softc *); 106 static int agp_i810_init(struct agp_softc *); 107 108 static struct agp_methods agp_i810_methods = { 109 agp_i810_get_aperture, 110 agp_i810_set_aperture, 111 agp_i810_bind_page, 112 agp_i810_unbind_page, 113 agp_i810_flush_tlb, 114 agp_i810_enable, 115 agp_i810_alloc_memory, 116 agp_i810_free_memory, 117 agp_i810_bind_memory, 118 agp_i810_unbind_memory, 119 }; 120 121 int 122 agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, bus_addr_t v) 123 { 124 u_int32_t pte; 125 126 /* Bits 11:4 (physical start address extension) should be zero. */ 127 if ((v & 0xff0) != 0) 128 return EINVAL; 129 130 pte = (u_int32_t)v; 131 /* 132 * We need to massage the pte if bus_addr_t is wider than 32 bits. 133 * The compiler isn't smart enough, hence the casts to uintmax_t. 134 */ 135 if (sizeof(bus_addr_t) > sizeof(u_int32_t)) { 136 /* 965+ can do 36-bit addressing, add in the extra bits. */ 137 if (isc->chiptype == CHIP_I965 || 138 isc->chiptype == CHIP_G33 || 139 isc->chiptype == CHIP_G4X) { 140 if (((uintmax_t)v >> 36) != 0) 141 return EINVAL; 142 pte |= (v >> 28) & 0xf0; 143 } else { 144 if (((uintmax_t)v >> 32) != 0) 145 return EINVAL; 146 } 147 } 148 149 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, 150 4*(off >> AGP_PAGE_SHIFT), pte); 151 152 return 0; 153 } 154 155 void 156 agp_i810_post_gtt_entry(struct agp_i810_softc *isc, off_t off) 157 { 158 159 (void)bus_space_read_4(isc->gtt_bst, isc->gtt_bsh, 160 4*(off >> AGP_PAGE_SHIFT)); 161 } 162 163 static void 164 agp_flush_cache_xc(void *a __unused, void *b __unused) 165 { 166 167 agp_flush_cache(); 168 } 169 170 void 171 agp_i810_chipset_flush(struct agp_i810_softc *isc) 172 { 173 unsigned int timo = 20000; /* * 50 us = 1 s */ 174 175 switch (isc->chiptype) { 176 case CHIP_I810: 177 break; 178 case CHIP_I830: 179 case CHIP_I855: 180 /* 181 * Flush all CPU caches. If we're cold, we can't run 182 * xcalls, but there should be only one CPU up, so 183 * flushing only the local CPU's cache should suffice. 184 * 185 * XXX Come to think of it, do these chipsets appear in 186 * any multi-CPU systems? 187 */ 188 if (cold) 189 agp_flush_cache(); 190 else 191 xc_wait(xc_broadcast(0, &agp_flush_cache_xc, 192 NULL, NULL)); 193 WRITE4(AGP_I830_HIC, READ4(AGP_I830_HIC) | __BIT(31)); 194 while (ISSET(READ4(AGP_I830_HIC), __BIT(31))) { 195 if (timo-- == 0) 196 break; 197 DELAY(50); 198 } 199 break; 200 case CHIP_I915: 201 case CHIP_I965: 202 case CHIP_G33: 203 case CHIP_G4X: 204 bus_space_write_4(isc->flush_bst, isc->flush_bsh, 0, 1); 205 break; 206 } 207 } 208 209 /* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */ 210 static int 211 agp_i810_vgamatch(const struct pci_attach_args *pa) 212 { 213 214 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 215 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 216 return (0); 217 218 switch (PCI_PRODUCT(pa->pa_id)) { 219 case PCI_PRODUCT_INTEL_82810_GC: 220 case PCI_PRODUCT_INTEL_82810_DC100_GC: 221 case PCI_PRODUCT_INTEL_82810E_GC: 222 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 223 case PCI_PRODUCT_INTEL_82830MP_IV: 224 case PCI_PRODUCT_INTEL_82845G_IGD: 225 case PCI_PRODUCT_INTEL_82855GM_IGD: 226 case PCI_PRODUCT_INTEL_82865_IGD: 227 case PCI_PRODUCT_INTEL_82915G_IGD: 228 case PCI_PRODUCT_INTEL_82915GM_IGD: 229 case PCI_PRODUCT_INTEL_82945P_IGD: 230 case PCI_PRODUCT_INTEL_82945GM_IGD: 231 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 232 case PCI_PRODUCT_INTEL_82945GME_IGD: 233 case PCI_PRODUCT_INTEL_E7221_IGD: 234 case PCI_PRODUCT_INTEL_82965Q_IGD: 235 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 236 case PCI_PRODUCT_INTEL_82965PM_IGD: 237 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 238 case PCI_PRODUCT_INTEL_82G33_IGD: 239 case PCI_PRODUCT_INTEL_82G33_IGD_1: 240 case PCI_PRODUCT_INTEL_82965G_IGD: 241 case PCI_PRODUCT_INTEL_82965G_IGD_1: 242 case PCI_PRODUCT_INTEL_82965GME_IGD: 243 case PCI_PRODUCT_INTEL_82Q35_IGD: 244 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 245 case PCI_PRODUCT_INTEL_82Q33_IGD: 246 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 247 case PCI_PRODUCT_INTEL_82G35_IGD: 248 case PCI_PRODUCT_INTEL_82G35_IGD_1: 249 case PCI_PRODUCT_INTEL_82946GZ_IGD: 250 case PCI_PRODUCT_INTEL_82GM45_IGD: 251 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 252 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 253 case PCI_PRODUCT_INTEL_82Q45_IGD: 254 case PCI_PRODUCT_INTEL_82G45_IGD: 255 case PCI_PRODUCT_INTEL_82G41_IGD: 256 case PCI_PRODUCT_INTEL_82B43_IGD: 257 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 258 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 259 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 260 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 261 return (1); 262 } 263 264 return (0); 265 } 266 267 static int 268 agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg) 269 { 270 /* 271 * Find the aperture. Don't map it (yet), this would 272 * eat KVA. 273 */ 274 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 275 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize, 276 &sc->as_apflags) != 0) 277 return ENXIO; 278 279 sc->as_apt = pa->pa_memt; 280 281 return 0; 282 } 283 284 int 285 agp_i810_attach(device_t parent, device_t self, void *aux) 286 { 287 struct agp_softc *sc = device_private(self); 288 struct agp_i810_softc *isc; 289 int apbase, mmadr_bar, gtt_bar; 290 int mmadr_type, mmadr_flags; 291 bus_addr_t mmadr; 292 bus_size_t mmadr_size, gtt_off; 293 int error; 294 295 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 296 if (isc == NULL) { 297 aprint_error(": can't allocate chipset-specific softc\n"); 298 error = ENOMEM; 299 goto fail0; 300 } 301 sc->as_chipc = isc; 302 sc->as_methods = &agp_i810_methods; 303 304 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) { 305 #if NAGP_INTEL > 0 306 const struct pci_attach_args *pa = aux; 307 308 switch (PCI_PRODUCT(pa->pa_id)) { 309 case PCI_PRODUCT_INTEL_82840_HB: 310 case PCI_PRODUCT_INTEL_82865_HB: 311 case PCI_PRODUCT_INTEL_82845G_DRAM: 312 case PCI_PRODUCT_INTEL_82815_FULL_HUB: 313 case PCI_PRODUCT_INTEL_82855GM_MCH: 314 free(isc, M_AGP); 315 return agp_intel_attach(parent, self, aux); 316 } 317 #endif 318 aprint_error(": can't find internal VGA" 319 " config space\n"); 320 error = ENOENT; 321 goto fail1; 322 } 323 324 /* XXXfvdl */ 325 sc->as_dmat = isc->vga_pa.pa_dmat; 326 327 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 328 case PCI_PRODUCT_INTEL_82810_GC: 329 case PCI_PRODUCT_INTEL_82810_DC100_GC: 330 case PCI_PRODUCT_INTEL_82810E_GC: 331 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 332 isc->chiptype = CHIP_I810; 333 aprint_normal(": i810-family chipset\n"); 334 break; 335 case PCI_PRODUCT_INTEL_82830MP_IV: 336 case PCI_PRODUCT_INTEL_82845G_IGD: 337 isc->chiptype = CHIP_I830; 338 aprint_normal(": i830-family chipset\n"); 339 break; 340 case PCI_PRODUCT_INTEL_82855GM_IGD: 341 case PCI_PRODUCT_INTEL_82865_IGD: 342 isc->chiptype = CHIP_I855; 343 aprint_normal(": i855-family chipset\n"); 344 break; 345 case PCI_PRODUCT_INTEL_82915G_IGD: 346 case PCI_PRODUCT_INTEL_82915GM_IGD: 347 case PCI_PRODUCT_INTEL_82945P_IGD: 348 case PCI_PRODUCT_INTEL_82945GM_IGD: 349 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 350 case PCI_PRODUCT_INTEL_82945GME_IGD: 351 case PCI_PRODUCT_INTEL_E7221_IGD: 352 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 353 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 354 isc->chiptype = CHIP_I915; 355 aprint_normal(": i915-family chipset\n"); 356 break; 357 case PCI_PRODUCT_INTEL_82965Q_IGD: 358 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 359 case PCI_PRODUCT_INTEL_82965PM_IGD: 360 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 361 case PCI_PRODUCT_INTEL_82965G_IGD: 362 case PCI_PRODUCT_INTEL_82965G_IGD_1: 363 case PCI_PRODUCT_INTEL_82965GME_IGD: 364 case PCI_PRODUCT_INTEL_82946GZ_IGD: 365 case PCI_PRODUCT_INTEL_82G35_IGD: 366 case PCI_PRODUCT_INTEL_82G35_IGD_1: 367 isc->chiptype = CHIP_I965; 368 aprint_normal(": i965-family chipset\n"); 369 break; 370 case PCI_PRODUCT_INTEL_82Q35_IGD: 371 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 372 case PCI_PRODUCT_INTEL_82G33_IGD: 373 case PCI_PRODUCT_INTEL_82G33_IGD_1: 374 case PCI_PRODUCT_INTEL_82Q33_IGD: 375 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 376 isc->chiptype = CHIP_G33; 377 aprint_normal(": G33-family chipset\n"); 378 break; 379 case PCI_PRODUCT_INTEL_82GM45_IGD: 380 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 381 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 382 case PCI_PRODUCT_INTEL_82Q45_IGD: 383 case PCI_PRODUCT_INTEL_82G45_IGD: 384 case PCI_PRODUCT_INTEL_82G41_IGD: 385 case PCI_PRODUCT_INTEL_82B43_IGD: 386 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 387 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 388 isc->chiptype = CHIP_G4X; 389 aprint_normal(": G4X-family chipset\n"); 390 break; 391 } 392 aprint_naive("\n"); 393 394 mmadr_type = PCI_MAPREG_TYPE_MEM; 395 switch (isc->chiptype) { 396 case CHIP_I915: 397 case CHIP_G33: 398 apbase = AGP_I915_GMADR; 399 mmadr_bar = AGP_I915_MMADR; 400 isc->size = 512*1024; 401 gtt_bar = AGP_I915_GTTADR; 402 gtt_off = ~(bus_size_t)0; /* XXXGCC */ 403 break; 404 case CHIP_I965: 405 apbase = AGP_I965_GMADR; 406 mmadr_bar = AGP_I965_MMADR; 407 mmadr_type |= PCI_MAPREG_MEM_TYPE_64BIT; 408 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, 409 AGP_I965_MMADR, mmadr_type, NULL, &isc->size, NULL)) 410 isc->size = 512*1024; /* XXX */ 411 gtt_bar = 0; 412 gtt_off = AGP_I965_GTT; 413 break; 414 case CHIP_G4X: 415 apbase = AGP_I965_GMADR; 416 mmadr_bar = AGP_I965_MMADR; 417 mmadr_type |= PCI_MAPREG_MEM_TYPE_64BIT; 418 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, 419 AGP_I965_MMADR, mmadr_type, NULL, &isc->size, NULL)) 420 isc->size = 512*1024; /* XXX */ 421 gtt_bar = 0; 422 gtt_off = AGP_G4X_GTT; 423 break; 424 default: 425 apbase = AGP_I810_GMADR; 426 mmadr_bar = AGP_I810_MMADR; 427 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, 428 AGP_I965_MMADR, mmadr_type, NULL, &isc->size, NULL)) 429 isc->size = 512*1024; /* XXX */ 430 gtt_bar = 0; 431 gtt_off = AGP_I810_GTT; 432 break; 433 } 434 435 /* Map (or, rather, find the address and size of) the aperture. */ 436 if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) 437 error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase); 438 else 439 error = agp_map_aperture(&isc->vga_pa, sc, apbase); 440 if (error) { 441 aprint_error_dev(self, "can't map aperture: %d\n", error); 442 goto fail1; 443 } 444 445 /* Map the memory-mapped I/O registers, or the non-GTT part. */ 446 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, mmadr_bar, 447 mmadr_type, &mmadr, &mmadr_size, &mmadr_flags)) { 448 aprint_error_dev(self, "can't find MMIO registers\n"); 449 error = ENXIO; 450 goto fail1; 451 } 452 if (mmadr_size < isc->size) { 453 aprint_error_dev(self, "MMIO registers too small" 454 ": %"PRIuMAX" < %"PRIuMAX"\n", 455 (uintmax_t)mmadr_size, (uintmax_t)isc->size); 456 error = ENXIO; 457 goto fail1; 458 } 459 isc->bst = isc->vga_pa.pa_memt; 460 error = bus_space_map(isc->bst, mmadr, isc->size, mmadr_flags, 461 &isc->bsh); 462 if (error) { 463 aprint_error_dev(self, "can't map MMIO registers: %d\n", 464 error); 465 error = ENXIO; 466 goto fail1; 467 } 468 469 /* Set up a chipset flush page if necessary. */ 470 switch (isc->chiptype) { 471 case CHIP_I915: 472 case CHIP_I965: 473 case CHIP_G33: 474 case CHIP_G4X: 475 error = agp_i810_setup_chipset_flush_page(sc); 476 if (error) { 477 aprint_error_dev(self, 478 "can't set up chipset flush page: %d\n", error); 479 goto fail2; 480 } 481 break; 482 } 483 484 /* 485 * XXX horrible hack to allow drm code to use our mapping 486 * of VGA chip registers 487 */ 488 agp_i810_vga_regbase = mmadr; 489 agp_i810_vga_regsize = isc->size; 490 agp_i810_vga_bst = isc->bst; 491 agp_i810_vga_bsh = isc->bsh; 492 493 /* Initialize the chipset. */ 494 error = agp_i810_init(sc); 495 if (error) 496 goto fail3; 497 498 /* Map the GTT, from either part of the MMIO region or its own BAR. */ 499 if (gtt_bar == 0) { 500 isc->gtt_bst = isc->bst; 501 if ((mmadr_size - gtt_off) < isc->gtt_size) { 502 aprint_error_dev(self, "GTTMMADR too small for GTT" 503 ": (%"PRIxMAX" - %"PRIxMAX") < %"PRIxMAX"\n", 504 (uintmax_t)mmadr_size, 505 (uintmax_t)gtt_off, 506 (uintmax_t)isc->gtt_size); 507 error = ENXIO; 508 goto fail4; 509 } 510 /* 511 * Map the GTT separately if we can, so that we can map 512 * it prefetchable, but in early models, there are MMIO 513 * registers before and after the GTT, so we can only 514 * take a subregion. 515 */ 516 if (isc->size < gtt_off) 517 error = bus_space_map(isc->gtt_bst, (mmadr + gtt_off), 518 isc->gtt_size, mmadr_flags, &isc->gtt_bsh); 519 else 520 error = bus_space_subregion(isc->bst, isc->bsh, 521 gtt_off, isc->gtt_size, &isc->gtt_bsh); 522 if (error) { 523 aprint_error_dev(self, "can't map GTT: %d\n", error); 524 error = ENXIO; 525 goto fail4; 526 } 527 } else { 528 bus_size_t gtt_bar_size; 529 /* 530 * All chipsets with a separate BAR for the GTT, namely 531 * the i915 and G33 families, have 32-bit GTT BARs. 532 * 533 * XXX [citation needed] 534 */ 535 if (pci_mapreg_map(&isc->vga_pa, gtt_bar, PCI_MAPREG_TYPE_MEM, 536 0, 537 &isc->gtt_bst, &isc->gtt_bsh, NULL, >t_bar_size)) { 538 aprint_error_dev(self, "can't map GTT\n"); 539 error = ENXIO; 540 goto fail4; 541 } 542 if (gtt_bar_size != isc->gtt_size) { 543 aprint_error_dev(self, 544 "BAR size %"PRIxMAX 545 " mismatches detected GTT size %"PRIxMAX 546 "; trusting BAR\n", 547 (uintmax_t)gtt_bar_size, 548 (uintmax_t)isc->gtt_size); 549 isc->gtt_size = gtt_bar_size; 550 } 551 } 552 553 /* Power management. (XXX Nothing to save on suspend? Fishy...) */ 554 if (!pmf_device_register(self, NULL, agp_i810_resume)) 555 aprint_error_dev(self, "can't establish power handler\n"); 556 557 /* Match the generic AGP code's autoconf output format. */ 558 aprint_normal("%s", device_xname(self)); 559 560 /* Success! */ 561 return 0; 562 563 fail5: __unused 564 pmf_device_deregister(self); 565 if ((gtt_bar != 0) || (isc->size < gtt_off)) 566 bus_space_unmap(isc->gtt_bst, isc->gtt_bsh, isc->gtt_size); 567 isc->gtt_size = 0; 568 fail4: 569 #if notyet 570 agp_i810_fini(sc); 571 #endif 572 fail3: switch (isc->chiptype) { 573 case CHIP_I915: 574 case CHIP_I965: 575 case CHIP_G33: 576 case CHIP_G4X: 577 agp_i810_teardown_chipset_flush_page(sc); 578 break; 579 } 580 fail2: bus_space_unmap(isc->bst, isc->bsh, isc->size); 581 isc->size = 0; 582 fail1: free(isc, M_AGP); 583 sc->as_chipc = NULL; 584 fail0: agp_generic_detach(sc); 585 KASSERT(error); 586 return error; 587 } 588 589 static int 590 agp_i810_setup_chipset_flush_page(struct agp_softc *sc) 591 { 592 struct agp_i810_softc *const isc = sc->as_chipc; 593 const pci_chipset_tag_t pc = sc->as_pc; 594 const pcitag_t tag = sc->as_tag; 595 pcireg_t lo, hi; 596 bus_addr_t addr, minaddr, maxaddr; 597 int error; 598 599 /* We always use memory-mapped I/O. */ 600 isc->flush_bst = isc->vga_pa.pa_memt; 601 602 /* No page allocated yet. */ 603 isc->flush_addr = 0; 604 605 /* Read the PCI config register: 4-byte on gen3, 8-byte on gen>=4. */ 606 if (isc->chiptype == CHIP_I915) { 607 addr = pci_conf_read(pc, tag, AGP_I915_IFPADDR); 608 minaddr = PAGE_SIZE; /* XXX PCIBIOS_MIN_MEM? */ 609 maxaddr = UINT32_MAX; 610 } else { 611 hi = pci_conf_read(pc, tag, AGP_I965_IFPADDR+4); 612 lo = pci_conf_read(pc, tag, AGP_I965_IFPADDR); 613 /* 614 * Convert to uint64_t, rather than bus_addr_t which 615 * may be 32-bit, to avoid undefined behaviour with a 616 * too-wide shift. Since the BIOS doesn't know whether 617 * the OS will run 64-bit or with PAE, it ought to 618 * configure at most a 32-bit physical address, so 619 * let's print a warning in case that happens. 620 */ 621 addr = ((uint64_t)hi << 32) | lo; 622 if (hi) { 623 aprint_error_dev(sc->as_dev, 624 "BIOS configured >32-bit flush page address" 625 ": %"PRIx64"\n", ((uint64_t)hi << 32) | lo); 626 #if __i386__ && !PAE 627 return EIO; 628 #endif 629 } 630 minaddr = PAGE_SIZE; /* XXX PCIBIOS_MIN_MEM? */ 631 maxaddr = MIN(UINT64_MAX, ~(bus_addr_t)0); 632 } 633 634 /* Allocate or map a pre-allocated a page for it. */ 635 if (ISSET(addr, 1)) { 636 /* BIOS allocated it for us. Use that. */ 637 error = bus_space_map(isc->flush_bst, addr & ~1, PAGE_SIZE, 0, 638 &isc->flush_bsh); 639 if (error) 640 return error; 641 } else { 642 /* None allocated. Allocate one. */ 643 error = bus_space_alloc(isc->flush_bst, minaddr, maxaddr, 644 PAGE_SIZE, PAGE_SIZE, 0, 0, 645 &isc->flush_addr, &isc->flush_bsh); 646 if (error) 647 return error; 648 KASSERT(isc->flush_addr != 0); 649 /* Write it into the PCI config register. */ 650 addr = isc->flush_addr | 1; 651 if (isc->chiptype == CHIP_I915) { 652 pci_conf_write(pc, tag, AGP_I915_IFPADDR, addr); 653 } else { 654 hi = __SHIFTOUT(addr, __BITS(63, 32)); 655 lo = __SHIFTOUT(addr, __BITS(31, 0)); 656 pci_conf_write(pc, tag, AGP_I965_IFPADDR+4, hi); 657 pci_conf_write(pc, tag, AGP_I965_IFPADDR, lo); 658 } 659 } 660 661 /* Success! */ 662 return 0; 663 } 664 665 static void 666 agp_i810_teardown_chipset_flush_page(struct agp_softc *sc) 667 { 668 struct agp_i810_softc *const isc = sc->as_chipc; 669 670 if (isc->flush_addr) { 671 /* If we allocated a page, clear it. */ 672 if (isc->chiptype == CHIP_I915) { 673 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR, 674 0); 675 } else { 676 pci_conf_write(sc->as_pc, sc->as_tag, 677 AGP_I965_IFPADDR, 0); 678 pci_conf_write(sc->as_pc, sc->as_tag, 679 AGP_I965_IFPADDR + 4, 0); 680 } 681 isc->flush_addr = 0; 682 bus_space_free(isc->flush_bst, isc->flush_bsh, 683 PAGE_SIZE); 684 } else { 685 /* Otherwise, just unmap the pre-allocated page. */ 686 bus_space_unmap(isc->flush_bst, isc->flush_bsh, PAGE_SIZE); 687 } 688 } 689 690 /* 691 * XXX horrible hack to allow drm code to use our mapping 692 * of VGA chip registers 693 */ 694 int 695 agp_i810_borrow(bus_addr_t base, bus_size_t size, bus_space_handle_t *hdlp) 696 { 697 698 if (agp_i810_vga_regbase == 0) 699 return 0; 700 if (base < agp_i810_vga_regbase) 701 return 0; 702 if (agp_i810_vga_regsize < size) 703 return 0; 704 if ((base - agp_i810_vga_regbase) > (agp_i810_vga_regsize - size)) 705 return 0; 706 if (bus_space_subregion(agp_i810_vga_bst, agp_i810_vga_bsh, 707 (base - agp_i810_vga_regbase), (agp_i810_vga_regsize - size), 708 hdlp)) 709 return 0; 710 return 1; 711 } 712 713 static int 714 agp_i810_init(struct agp_softc *sc) 715 { 716 struct agp_i810_softc *isc; 717 int error; 718 719 isc = sc->as_chipc; 720 721 if (isc->chiptype == CHIP_I810) { 722 struct agp_gatt *gatt; 723 void *virtual; 724 int dummyseg; 725 726 /* Some i810s have on-chip memory called dcache */ 727 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 728 isc->dcache_size = 4 * 1024 * 1024; 729 else 730 isc->dcache_size = 0; 731 732 /* According to the specs the gatt on the i810 must be 64k */ 733 isc->gtt_size = 64 * 1024; 734 gatt = malloc(sizeof(*gatt), M_AGP, M_NOWAIT); 735 if (gatt == NULL) { 736 aprint_error_dev(sc->as_dev, 737 "can't malloc GATT record\n"); 738 error = ENOMEM; 739 goto fail0; 740 } 741 gatt->ag_entries = isc->gtt_size / sizeof(uint32_t); 742 error = agp_alloc_dmamem(sc->as_dmat, isc->gtt_size, 743 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical, 744 &gatt->ag_dmaseg, 1, &dummyseg); 745 if (error) { 746 aprint_error_dev(sc->as_dev, 747 "can't allocate memory for GTT: %d\n", error); 748 free(gatt, M_AGP); 749 goto fail0; 750 } 751 752 gatt->ag_virtual = (uint32_t *)virtual; 753 gatt->ag_size = gatt->ag_entries * sizeof(uint32_t); 754 memset(gatt->ag_virtual, 0, gatt->ag_size); 755 agp_flush_cache(); 756 757 /* Install the GATT. */ 758 isc->pgtblctl = gatt->ag_physical | 1; 759 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 760 isc->gatt = gatt; 761 } else if (isc->chiptype == CHIP_I830) { 762 /* The i830 automatically initializes the 128k gatt on boot. */ 763 /* XXX [citation needed] */ 764 pcireg_t reg; 765 u_int16_t gcc1; 766 767 isc->gtt_size = 128 * 1024; 768 769 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 770 gcc1 = (u_int16_t)(reg >> 16); 771 switch (gcc1 & AGP_I830_GCC1_GMS) { 772 case AGP_I830_GCC1_GMS_STOLEN_512: 773 isc->stolen = (512 - 132) * 1024 / 4096; 774 break; 775 case AGP_I830_GCC1_GMS_STOLEN_1024: 776 isc->stolen = (1024 - 132) * 1024 / 4096; 777 break; 778 case AGP_I830_GCC1_GMS_STOLEN_8192: 779 isc->stolen = (8192 - 132) * 1024 / 4096; 780 break; 781 default: 782 isc->stolen = 0; 783 aprint_error_dev(sc->as_dev, 784 "unknown memory configuration, disabling\n"); 785 error = ENXIO; 786 goto fail0; 787 } 788 789 if (isc->stolen > 0) { 790 aprint_normal_dev(sc->as_dev, 791 "detected %dk stolen memory\n", 792 isc->stolen * 4); 793 } 794 795 /* GATT address is already in there, make sure it's enabled */ 796 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 797 isc->pgtblctl |= 1; 798 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 799 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 800 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 || 801 isc->chiptype == CHIP_G4X) { 802 pcireg_t reg; 803 u_int32_t gtt_size, stolen; /* XXX kilobytes */ 804 u_int16_t gcc1; 805 806 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1); 807 gcc1 = (u_int16_t)(reg >> 16); 808 809 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 810 811 /* Stolen memory is set up at the beginning of the aperture by 812 * the BIOS, consisting of the GATT followed by 4kb for the 813 * BIOS display. 814 */ 815 switch (isc->chiptype) { 816 case CHIP_I855: 817 gtt_size = 128; 818 break; 819 case CHIP_I915: 820 gtt_size = 256; 821 break; 822 case CHIP_I965: 823 switch (isc->pgtblctl & AGP_I810_PGTBL_SIZE_MASK) { 824 case AGP_I810_PGTBL_SIZE_128KB: 825 case AGP_I810_PGTBL_SIZE_512KB: 826 gtt_size = 512; 827 break; 828 case AGP_I965_PGTBL_SIZE_1MB: 829 gtt_size = 1024; 830 break; 831 case AGP_I965_PGTBL_SIZE_2MB: 832 gtt_size = 2048; 833 break; 834 case AGP_I965_PGTBL_SIZE_1_5MB: 835 gtt_size = 1024 + 512; 836 break; 837 default: 838 aprint_error_dev(sc->as_dev, 839 "bad PGTBL size\n"); 840 error = ENXIO; 841 goto fail0; 842 } 843 break; 844 case CHIP_G33: 845 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 846 case AGP_G33_PGTBL_SIZE_1M: 847 gtt_size = 1024; 848 break; 849 case AGP_G33_PGTBL_SIZE_2M: 850 gtt_size = 2048; 851 break; 852 default: 853 aprint_error_dev(sc->as_dev, 854 "bad PGTBL size\n"); 855 error = ENXIO; 856 goto fail0; 857 } 858 break; 859 case CHIP_G4X: 860 switch (isc->pgtblctl & AGP_G4X_PGTBL_SIZE_MASK) { 861 case AGP_G4X_PGTBL_SIZE_512K: 862 gtt_size = 512; 863 break; 864 case AGP_G4X_PGTBL_SIZE_256K: 865 gtt_size = 256; 866 break; 867 case AGP_G4X_PGTBL_SIZE_128K: 868 gtt_size = 128; 869 break; 870 case AGP_G4X_PGTBL_SIZE_1M: 871 gtt_size = 1*1024; 872 break; 873 case AGP_G4X_PGTBL_SIZE_2M: 874 gtt_size = 2*1024; 875 break; 876 case AGP_G4X_PGTBL_SIZE_1_5M: 877 gtt_size = 1*1024 + 512; 878 break; 879 default: 880 aprint_error_dev(sc->as_dev, 881 "bad PGTBL size\n"); 882 error = ENXIO; 883 goto fail0; 884 } 885 break; 886 default: 887 panic("impossible chiptype %d", isc->chiptype); 888 } 889 890 /* 891 * XXX If I'm reading the datasheets right, this stolen 892 * memory detection logic is totally wrong. 893 */ 894 switch (gcc1 & AGP_I855_GCC1_GMS) { 895 case AGP_I855_GCC1_GMS_STOLEN_1M: 896 stolen = 1024; 897 break; 898 case AGP_I855_GCC1_GMS_STOLEN_4M: 899 stolen = 4 * 1024; 900 break; 901 case AGP_I855_GCC1_GMS_STOLEN_8M: 902 stolen = 8 * 1024; 903 break; 904 case AGP_I855_GCC1_GMS_STOLEN_16M: 905 stolen = 16 * 1024; 906 break; 907 case AGP_I855_GCC1_GMS_STOLEN_32M: 908 stolen = 32 * 1024; 909 break; 910 case AGP_I915_GCC1_GMS_STOLEN_48M: 911 stolen = 48 * 1024; 912 break; 913 case AGP_I915_GCC1_GMS_STOLEN_64M: 914 stolen = 64 * 1024; 915 break; 916 case AGP_G33_GCC1_GMS_STOLEN_128M: 917 stolen = 128 * 1024; 918 break; 919 case AGP_G33_GCC1_GMS_STOLEN_256M: 920 stolen = 256 * 1024; 921 break; 922 case AGP_G4X_GCC1_GMS_STOLEN_96M: 923 stolen = 96 * 1024; 924 break; 925 case AGP_G4X_GCC1_GMS_STOLEN_160M: 926 stolen = 160 * 1024; 927 break; 928 case AGP_G4X_GCC1_GMS_STOLEN_224M: 929 stolen = 224 * 1024; 930 break; 931 case AGP_G4X_GCC1_GMS_STOLEN_352M: 932 stolen = 352 * 1024; 933 break; 934 default: 935 aprint_error_dev(sc->as_dev, 936 "unknown memory configuration, disabling\n"); 937 error = ENXIO; 938 goto fail0; 939 } 940 941 switch (gcc1 & AGP_I855_GCC1_GMS) { 942 case AGP_I915_GCC1_GMS_STOLEN_48M: 943 case AGP_I915_GCC1_GMS_STOLEN_64M: 944 if (isc->chiptype != CHIP_I915 && 945 isc->chiptype != CHIP_I965 && 946 isc->chiptype != CHIP_G33 && 947 isc->chiptype != CHIP_G4X) 948 stolen = 0; 949 break; 950 case AGP_G33_GCC1_GMS_STOLEN_128M: 951 case AGP_G33_GCC1_GMS_STOLEN_256M: 952 if (isc->chiptype != CHIP_I965 && 953 isc->chiptype != CHIP_G33 && 954 isc->chiptype != CHIP_G4X) 955 stolen = 0; 956 break; 957 case AGP_G4X_GCC1_GMS_STOLEN_96M: 958 case AGP_G4X_GCC1_GMS_STOLEN_160M: 959 case AGP_G4X_GCC1_GMS_STOLEN_224M: 960 case AGP_G4X_GCC1_GMS_STOLEN_352M: 961 if (isc->chiptype != CHIP_I965 && 962 isc->chiptype != CHIP_G4X) 963 stolen = 0; 964 break; 965 } 966 967 isc->gtt_size = gtt_size * 1024; 968 969 /* BIOS space */ 970 /* XXX [citation needed] */ 971 gtt_size += 4; 972 973 /* XXX [citation needed] for this subtraction */ 974 isc->stolen = (stolen - gtt_size) * 1024 / 4096; 975 976 if (isc->stolen > 0) { 977 aprint_normal_dev(sc->as_dev, 978 "detected %dk stolen memory\n", 979 isc->stolen * 4); 980 } 981 982 /* GATT address is already in there, make sure it's enabled */ 983 isc->pgtblctl |= 1; 984 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 985 } 986 987 /* 988 * Make sure the chipset can see everything. 989 */ 990 agp_flush_cache(); 991 992 /* 993 * Publish what we found for kludgey drivers (I'm looking at 994 * you, drm). 995 */ 996 if (agp_i810_sc == NULL) 997 agp_i810_sc = sc; 998 else 999 aprint_error_dev(sc->as_dev, "agp already attached\n"); 1000 1001 /* Success! */ 1002 return 0; 1003 1004 fail0: KASSERT(error); 1005 return error; 1006 } 1007 1008 #if 0 1009 static int 1010 agp_i810_detach(struct agp_softc *sc) 1011 { 1012 int error; 1013 struct agp_i810_softc *isc = sc->as_chipc; 1014 1015 error = agp_generic_detach(sc); 1016 if (error) 1017 return error; 1018 1019 switch (isc->chiptype) { 1020 case CHIP_I915: 1021 case CHIP_I965: 1022 case CHIP_G33: 1023 case CHIP_G4X: 1024 agp_i810_teardown_chipset_flush_page(sc); 1025 break; 1026 } 1027 1028 /* Clear the GATT base. */ 1029 if (sc->chiptype == CHIP_I810) { 1030 WRITE4(AGP_I810_PGTBL_CTL, 0); 1031 } else { 1032 unsigned int pgtblctl; 1033 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 1034 pgtblctl &= ~1; 1035 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 1036 } 1037 1038 if (sc->chiptype == CHIP_I810) { 1039 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap, 1040 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 1041 free(isc->gatt, M_AGP); 1042 } 1043 1044 return 0; 1045 } 1046 #endif 1047 1048 static u_int32_t 1049 agp_i810_get_aperture(struct agp_softc *sc) 1050 { 1051 struct agp_i810_softc *isc = sc->as_chipc; 1052 pcireg_t reg; 1053 u_int32_t size; 1054 u_int16_t miscc, gcc1; 1055 1056 size = 0; 1057 1058 switch (isc->chiptype) { 1059 case CHIP_I810: 1060 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 1061 miscc = (u_int16_t)(reg >> 16); 1062 if ((miscc & AGP_I810_MISCC_WINSIZE) == 1063 AGP_I810_MISCC_WINSIZE_32) 1064 size = 32 * 1024 * 1024; 1065 else 1066 size = 64 * 1024 * 1024; 1067 break; 1068 case CHIP_I830: 1069 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 1070 gcc1 = (u_int16_t)(reg >> 16); 1071 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 1072 size = 64 * 1024 * 1024; 1073 else 1074 size = 128 * 1024 * 1024; 1075 break; 1076 case CHIP_I855: 1077 size = 128 * 1024 * 1024; 1078 break; 1079 case CHIP_I915: 1080 case CHIP_G33: 1081 case CHIP_G4X: 1082 size = sc->as_apsize; 1083 break; 1084 case CHIP_I965: 1085 size = 512 * 1024 * 1024; 1086 break; 1087 default: 1088 aprint_error(": Unknown chipset\n"); 1089 } 1090 1091 return size; 1092 } 1093 1094 static int 1095 agp_i810_set_aperture(struct agp_softc *sc __unused, 1096 uint32_t aperture __unused) 1097 { 1098 1099 return ENOSYS; 1100 } 1101 1102 static int 1103 agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 1104 { 1105 struct agp_i810_softc *isc = sc->as_chipc; 1106 1107 if (offset < 0 || offset >= ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) { 1108 DPRINTF(sc, "failed" 1109 ": offset 0x%"PRIxMAX", shift %u, entries %"PRIuMAX"\n", 1110 (uintmax_t)offset, 1111 (unsigned)AGP_PAGE_SHIFT, 1112 (uintmax_t)isc->gtt_size/4); 1113 return EINVAL; 1114 } 1115 1116 if (isc->chiptype != CHIP_I810) { 1117 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1118 DPRINTF(sc, "trying to bind into stolen memory\n"); 1119 return EINVAL; 1120 } 1121 } 1122 1123 return agp_i810_write_gtt_entry(isc, offset, physical | 1); 1124 } 1125 1126 static int 1127 agp_i810_unbind_page(struct agp_softc *sc, off_t offset) 1128 { 1129 struct agp_i810_softc *isc = sc->as_chipc; 1130 1131 if (offset < 0 || offset >= ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) 1132 return EINVAL; 1133 1134 if (isc->chiptype != CHIP_I810 ) { 1135 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1136 DPRINTF(sc, "trying to unbind from stolen memory\n"); 1137 return EINVAL; 1138 } 1139 } 1140 1141 return agp_i810_write_gtt_entry(isc, offset, 0); 1142 } 1143 1144 /* 1145 * Writing via memory mapped registers already flushes all TLBs. 1146 */ 1147 static void 1148 agp_i810_flush_tlb(struct agp_softc *sc) 1149 { 1150 } 1151 1152 static int 1153 agp_i810_enable(struct agp_softc *sc, u_int32_t mode) 1154 { 1155 1156 return 0; 1157 } 1158 1159 #define AGP_I810_MEMTYPE_MAIN 0 1160 #define AGP_I810_MEMTYPE_DCACHE 1 1161 #define AGP_I810_MEMTYPE_HWCURSOR 2 1162 1163 static struct agp_memory * 1164 agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size) 1165 { 1166 struct agp_i810_softc *isc = sc->as_chipc; 1167 struct agp_memory *mem; 1168 int error; 1169 1170 DPRINTF(sc, "AGP: alloc(%d, 0x%"PRIxMAX")\n", type, (uintmax_t)size); 1171 1172 if (size <= 0) 1173 return NULL; 1174 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 1175 return NULL; 1176 KASSERT(sc->as_allocated <= sc->as_maxmem); 1177 if (size > (sc->as_maxmem - sc->as_allocated)) 1178 return NULL; 1179 if (size > ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) 1180 return NULL; 1181 1182 switch (type) { 1183 case AGP_I810_MEMTYPE_MAIN: 1184 break; 1185 case AGP_I810_MEMTYPE_DCACHE: 1186 if (isc->chiptype != CHIP_I810) 1187 return NULL; 1188 if (size != isc->dcache_size) 1189 return NULL; 1190 break; 1191 case AGP_I810_MEMTYPE_HWCURSOR: 1192 if ((size != AGP_PAGE_SIZE) && 1193 (size != AGP_PAGE_SIZE*4)) 1194 return NULL; 1195 break; 1196 default: 1197 return NULL; 1198 } 1199 1200 mem = malloc(sizeof(*mem), M_AGP, M_WAITOK|M_ZERO); 1201 if (mem == NULL) 1202 goto fail0; 1203 mem->am_id = sc->as_nextid++; 1204 mem->am_size = size; 1205 mem->am_type = type; 1206 1207 switch (type) { 1208 case AGP_I810_MEMTYPE_MAIN: 1209 error = bus_dmamap_create(sc->as_dmat, size, 1210 (size >> AGP_PAGE_SHIFT) + 1, size, 0, BUS_DMA_WAITOK, 1211 &mem->am_dmamap); 1212 if (error) 1213 goto fail1; 1214 break; 1215 case AGP_I810_MEMTYPE_DCACHE: 1216 break; 1217 case AGP_I810_MEMTYPE_HWCURSOR: 1218 mem->am_dmaseg = malloc(sizeof(*mem->am_dmaseg), M_AGP, 1219 M_WAITOK); 1220 error = agp_alloc_dmamem(sc->as_dmat, size, 0, &mem->am_dmamap, 1221 &mem->am_virtual, &mem->am_physical, mem->am_dmaseg, 1, 1222 &mem->am_nseg); 1223 if (error) { 1224 free(mem->am_dmaseg, M_AGP); 1225 goto fail1; 1226 } 1227 (void)memset(mem->am_virtual, 0, size); 1228 break; 1229 default: 1230 panic("invalid agp memory type: %d", type); 1231 } 1232 1233 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link); 1234 sc->as_allocated += size; 1235 1236 return mem; 1237 1238 fail1: free(mem, M_AGP); 1239 fail0: return NULL; 1240 } 1241 1242 static int 1243 agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem) 1244 { 1245 1246 if (mem->am_is_bound) 1247 return EBUSY; 1248 1249 switch (mem->am_type) { 1250 case AGP_I810_MEMTYPE_MAIN: 1251 bus_dmamap_destroy(sc->as_dmat, mem->am_dmamap); 1252 break; 1253 case AGP_I810_MEMTYPE_DCACHE: 1254 break; 1255 case AGP_I810_MEMTYPE_HWCURSOR: 1256 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap, 1257 mem->am_virtual, mem->am_dmaseg, mem->am_nseg); 1258 free(mem->am_dmaseg, M_AGP); 1259 break; 1260 default: 1261 panic("invalid agp i810 memory type: %d", mem->am_type); 1262 } 1263 1264 sc->as_allocated -= mem->am_size; 1265 TAILQ_REMOVE(&sc->as_memory, mem, am_link); 1266 free(mem, M_AGP); 1267 1268 return 0; 1269 } 1270 1271 static int 1272 agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem, 1273 off_t offset) 1274 { 1275 struct agp_i810_softc *isc = sc->as_chipc; 1276 uint32_t pgtblctl; 1277 int error; 1278 1279 if (mem->am_is_bound) 1280 return EINVAL; 1281 1282 /* 1283 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 1284 * X server for mysterious reasons which leads to crashes if we write 1285 * to the GTT through the MMIO window. 1286 * Until the issue is solved, simply restore it. 1287 */ 1288 pgtblctl = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL); 1289 if (pgtblctl != isc->pgtblctl) { 1290 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%"PRIx32 1291 " - fixing\n", pgtblctl); 1292 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 1293 isc->pgtblctl); 1294 } 1295 1296 switch (mem->am_type) { 1297 case AGP_I810_MEMTYPE_MAIN: 1298 return agp_generic_bind_memory_bounded(sc, mem, offset, 1299 0, (isc->gtt_size/4) << AGP_PAGE_SHIFT); 1300 case AGP_I810_MEMTYPE_DCACHE: 1301 error = agp_i810_bind_memory_dcache(sc, mem, offset); 1302 break; 1303 case AGP_I810_MEMTYPE_HWCURSOR: 1304 error = agp_i810_bind_memory_hwcursor(sc, mem, offset); 1305 break; 1306 default: 1307 panic("invalid agp i810 memory type: %d", mem->am_type); 1308 } 1309 if (error) 1310 return error; 1311 1312 /* Success! */ 1313 mem->am_is_bound = 1; 1314 return 0; 1315 } 1316 1317 #define I810_GTT_PTE_VALID 0x01 1318 #define I810_GTT_PTE_DCACHE 0x02 1319 1320 static int 1321 agp_i810_bind_memory_dcache(struct agp_softc *sc, struct agp_memory *mem, 1322 off_t offset) 1323 { 1324 struct agp_i810_softc *const isc __diagused = sc->as_chipc; 1325 uint32_t i, j; 1326 int error; 1327 1328 KASSERT(isc->chiptype == CHIP_I810); 1329 1330 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0); 1331 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 1332 error = agp_i810_write_gtt_entry(isc, offset + i, 1333 i | I810_GTT_PTE_VALID | I810_GTT_PTE_DCACHE); 1334 if (error) 1335 goto fail0; 1336 } 1337 1338 /* Success! */ 1339 mem->am_offset = offset; 1340 return 0; 1341 1342 fail0: for (j = 0; j < i; j += AGP_PAGE_SIZE) 1343 (void)agp_i810_unbind_page(sc, offset + j); 1344 return error; 1345 } 1346 1347 static int 1348 agp_i810_bind_memory_hwcursor(struct agp_softc *sc, struct agp_memory *mem, 1349 off_t offset) 1350 { 1351 const bus_addr_t pa = mem->am_physical; 1352 uint32_t i, j; 1353 int error; 1354 1355 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0); 1356 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 1357 error = agp_i810_bind_page(sc, offset + i, pa + i); 1358 if (error) 1359 goto fail0; 1360 } 1361 1362 /* Success! */ 1363 mem->am_offset = offset; 1364 return 0; 1365 1366 fail0: for (j = 0; j < i; j += AGP_PAGE_SIZE) 1367 (void)agp_i810_unbind_page(sc, offset + j); 1368 return error; 1369 } 1370 1371 static int 1372 agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem) 1373 { 1374 struct agp_i810_softc *isc __diagused = sc->as_chipc; 1375 u_int32_t i; 1376 1377 if (!mem->am_is_bound) 1378 return EINVAL; 1379 1380 switch (mem->am_type) { 1381 case AGP_I810_MEMTYPE_MAIN: 1382 return agp_generic_unbind_memory(sc, mem); 1383 case AGP_I810_MEMTYPE_DCACHE: 1384 KASSERT(isc->chiptype == CHIP_I810); 1385 /* FALLTHROUGH */ 1386 case AGP_I810_MEMTYPE_HWCURSOR: 1387 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1388 (void)agp_i810_unbind_page(sc, mem->am_offset + i); 1389 mem->am_offset = 0; 1390 break; 1391 default: 1392 panic("invalid agp i810 memory type: %d", mem->am_type); 1393 } 1394 1395 mem->am_is_bound = 0; 1396 return 0; 1397 } 1398 1399 static bool 1400 agp_i810_resume(device_t dv, const pmf_qual_t *qual) 1401 { 1402 struct agp_softc *sc = device_private(dv); 1403 struct agp_i810_softc *isc = sc->as_chipc; 1404 1405 /* 1406 * XXX Nothing uses this! Save on suspend, restore on resume? 1407 */ 1408 isc->pgtblctl_resume_hack = READ4(AGP_I810_PGTBL_CTL); 1409 agp_flush_cache(); 1410 1411 return true; 1412 } 1413
Indexes created Fri Sep 26 20:09:58 GMT 2025