agp_i810.c revision 1.115
1 /* $NetBSD: agp_i810.c,v 1.115 2015/02/26 00:42:10 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.115 2015/02/26 00:42:10 riastradh Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/proc.h> 40 #include <sys/device.h> 41 #include <sys/conf.h> 42 #include <sys/xcall.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcidevs.h> 47 #include <dev/pci/agpvar.h> 48 #include <dev/pci/agpreg.h> 49 #include <dev/pci/agp_i810var.h> 50 51 #include <sys/agpio.h> 52 53 #include <sys/bus.h> 54 55 #include "agp_intel.h" 56 57 #ifdef AGP_DEBUG 58 #define DPRINTF(sc, fmt, ...) \ 59 device_printf((sc)->as_dev, "%s: " fmt, __func__, ##__VA_ARGS__) 60 #else 61 #define DPRINTF(sc, fmt, ...) do {} while (0) 62 #endif 63 64 struct agp_softc *agp_i810_sc = NULL; 65 66 #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off) 67 #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off) 68 #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v) 69 70 #define CHIP_I810 0 /* i810/i815 */ 71 #define CHIP_I830 1 /* 830M/845G */ 72 #define CHIP_I855 2 /* 852GM/855GM/865G */ 73 #define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */ 74 #define CHIP_I965 4 /* 965Q/965PM */ 75 #define CHIP_G33 5 /* G33/Q33/Q35 */ 76 #define CHIP_G4X 6 /* G45/Q45 */ 77 78 /* XXX hack, see below */ 79 static bus_addr_t agp_i810_vga_regbase; 80 static bus_size_t agp_i810_vga_regsize; 81 static bus_space_tag_t agp_i810_vga_bst; 82 static bus_space_handle_t agp_i810_vga_bsh; 83 84 static u_int32_t agp_i810_get_aperture(struct agp_softc *); 85 static int agp_i810_set_aperture(struct agp_softc *, u_int32_t); 86 static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t); 87 static int agp_i810_unbind_page(struct agp_softc *, off_t); 88 static void agp_i810_flush_tlb(struct agp_softc *); 89 static int agp_i810_enable(struct agp_softc *, u_int32_t mode); 90 static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int, 91 vsize_t); 92 static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *); 93 static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, 94 off_t); 95 static int agp_i810_bind_memory_dcache(struct agp_softc *, struct agp_memory *, 96 off_t); 97 static int agp_i810_bind_memory_hwcursor(struct agp_softc *, 98 struct agp_memory *, off_t); 99 static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *); 100 101 static bool agp_i810_resume(device_t, const pmf_qual_t *); 102 static int agp_i810_init(struct agp_softc *); 103 104 static int agp_i810_setup_chipset_flush_page(struct agp_softc *); 105 static void agp_i810_teardown_chipset_flush_page(struct agp_softc *); 106 static int agp_i810_init(struct agp_softc *); 107 108 static struct agp_methods agp_i810_methods = { 109 agp_i810_get_aperture, 110 agp_i810_set_aperture, 111 agp_i810_bind_page, 112 agp_i810_unbind_page, 113 agp_i810_flush_tlb, 114 agp_i810_enable, 115 agp_i810_alloc_memory, 116 agp_i810_free_memory, 117 agp_i810_bind_memory, 118 agp_i810_unbind_memory, 119 }; 120 121 int 122 agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, bus_addr_t v) 123 { 124 u_int32_t pte; 125 126 /* Bits 11:4 (physical start address extension) should be zero. */ 127 if ((v & 0xff0) != 0) 128 return EINVAL; 129 130 pte = (u_int32_t)v; 131 /* 132 * We need to massage the pte if bus_addr_t is wider than 32 bits. 133 * The compiler isn't smart enough, hence the casts to uintmax_t. 134 */ 135 if (sizeof(bus_addr_t) > sizeof(u_int32_t)) { 136 /* 965+ can do 36-bit addressing, add in the extra bits. */ 137 if (isc->chiptype == CHIP_I965 || 138 isc->chiptype == CHIP_G33 || 139 isc->chiptype == CHIP_G4X) { 140 if (((uintmax_t)v >> 36) != 0) 141 return EINVAL; 142 pte |= (v >> 28) & 0xf0; 143 } else { 144 if (((uintmax_t)v >> 32) != 0) 145 return EINVAL; 146 } 147 } 148 149 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, 150 4*(off >> AGP_PAGE_SHIFT), pte); 151 152 return 0; 153 } 154 155 void 156 agp_i810_post_gtt_entry(struct agp_i810_softc *isc, off_t off) 157 { 158 159 /* 160 * See <https://bugs.freedesktop.org/show_bug.cgi?id=88191>. 161 * Out of paranoia, let's do the write barrier and posting 162 * read, because I don't have enough time or hardware to 163 * conduct conclusive tests. 164 */ 165 membar_producer(); 166 (void)bus_space_read_4(isc->gtt_bst, isc->gtt_bsh, 167 4*(off >> AGP_PAGE_SHIFT)); 168 } 169 170 static void 171 agp_flush_cache_xc(void *a __unused, void *b __unused) 172 { 173 174 agp_flush_cache(); 175 } 176 177 void 178 agp_i810_chipset_flush(struct agp_i810_softc *isc) 179 { 180 unsigned int timo = 20000; /* * 50 us = 1 s */ 181 182 switch (isc->chiptype) { 183 case CHIP_I810: 184 break; 185 case CHIP_I830: 186 case CHIP_I855: 187 /* 188 * Flush all CPU caches. If we're cold, we can't run 189 * xcalls, but there should be only one CPU up, so 190 * flushing only the local CPU's cache should suffice. 191 * 192 * XXX Come to think of it, do these chipsets appear in 193 * any multi-CPU systems? 194 */ 195 if (cold) 196 agp_flush_cache(); 197 else 198 xc_wait(xc_broadcast(0, &agp_flush_cache_xc, 199 NULL, NULL)); 200 WRITE4(AGP_I830_HIC, READ4(AGP_I830_HIC) | __BIT(31)); 201 while (ISSET(READ4(AGP_I830_HIC), __BIT(31))) { 202 if (timo-- == 0) 203 break; 204 DELAY(50); 205 } 206 break; 207 case CHIP_I915: 208 case CHIP_I965: 209 case CHIP_G33: 210 case CHIP_G4X: 211 bus_space_write_4(isc->flush_bst, isc->flush_bsh, 0, 1); 212 break; 213 } 214 } 215 216 /* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */ 217 static int 218 agp_i810_vgamatch(const struct pci_attach_args *pa) 219 { 220 221 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 222 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 223 return (0); 224 225 switch (PCI_PRODUCT(pa->pa_id)) { 226 case PCI_PRODUCT_INTEL_82810_GC: 227 case PCI_PRODUCT_INTEL_82810_DC100_GC: 228 case PCI_PRODUCT_INTEL_82810E_GC: 229 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 230 case PCI_PRODUCT_INTEL_82830MP_IV: 231 case PCI_PRODUCT_INTEL_82845G_IGD: 232 case PCI_PRODUCT_INTEL_82855GM_IGD: 233 case PCI_PRODUCT_INTEL_82865_IGD: 234 case PCI_PRODUCT_INTEL_82915G_IGD: 235 case PCI_PRODUCT_INTEL_82915GM_IGD: 236 case PCI_PRODUCT_INTEL_82945P_IGD: 237 case PCI_PRODUCT_INTEL_82945GM_IGD: 238 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 239 case PCI_PRODUCT_INTEL_82945GME_IGD: 240 case PCI_PRODUCT_INTEL_E7221_IGD: 241 case PCI_PRODUCT_INTEL_82965Q_IGD: 242 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 243 case PCI_PRODUCT_INTEL_82965PM_IGD: 244 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 245 case PCI_PRODUCT_INTEL_82G33_IGD: 246 case PCI_PRODUCT_INTEL_82G33_IGD_1: 247 case PCI_PRODUCT_INTEL_82965G_IGD: 248 case PCI_PRODUCT_INTEL_82965G_IGD_1: 249 case PCI_PRODUCT_INTEL_82965GME_IGD: 250 case PCI_PRODUCT_INTEL_82Q35_IGD: 251 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 252 case PCI_PRODUCT_INTEL_82Q33_IGD: 253 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 254 case PCI_PRODUCT_INTEL_82G35_IGD: 255 case PCI_PRODUCT_INTEL_82G35_IGD_1: 256 case PCI_PRODUCT_INTEL_82946GZ_IGD: 257 case PCI_PRODUCT_INTEL_82GM45_IGD: 258 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 259 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 260 case PCI_PRODUCT_INTEL_82Q45_IGD: 261 case PCI_PRODUCT_INTEL_82G45_IGD: 262 case PCI_PRODUCT_INTEL_82G41_IGD: 263 case PCI_PRODUCT_INTEL_82B43_IGD: 264 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 265 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 266 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 267 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 268 return (1); 269 } 270 271 return (0); 272 } 273 274 static int 275 agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg) 276 { 277 /* 278 * Find the aperture. Don't map it (yet), this would 279 * eat KVA. 280 */ 281 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 282 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize, 283 &sc->as_apflags) != 0) 284 return ENXIO; 285 286 sc->as_apt = pa->pa_memt; 287 288 return 0; 289 } 290 291 int 292 agp_i810_attach(device_t parent, device_t self, void *aux) 293 { 294 struct agp_softc *sc = device_private(self); 295 struct agp_i810_softc *isc; 296 int apbase, mmadr_bar, gtt_bar; 297 int mmadr_type, mmadr_flags; 298 bus_addr_t mmadr; 299 bus_size_t mmadr_size, gtt_off; 300 int error; 301 302 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 303 if (isc == NULL) { 304 aprint_error(": can't allocate chipset-specific softc\n"); 305 error = ENOMEM; 306 goto fail0; 307 } 308 sc->as_chipc = isc; 309 sc->as_methods = &agp_i810_methods; 310 311 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) { 312 #if NAGP_INTEL > 0 313 const struct pci_attach_args *pa = aux; 314 315 switch (PCI_PRODUCT(pa->pa_id)) { 316 case PCI_PRODUCT_INTEL_82840_HB: 317 case PCI_PRODUCT_INTEL_82865_HB: 318 case PCI_PRODUCT_INTEL_82845G_DRAM: 319 case PCI_PRODUCT_INTEL_82815_FULL_HUB: 320 case PCI_PRODUCT_INTEL_82855GM_MCH: 321 free(isc, M_AGP); 322 return agp_intel_attach(parent, self, aux); 323 } 324 #endif 325 aprint_error(": can't find internal VGA" 326 " config space\n"); 327 error = ENOENT; 328 goto fail1; 329 } 330 331 /* XXXfvdl */ 332 sc->as_dmat = isc->vga_pa.pa_dmat; 333 334 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 335 case PCI_PRODUCT_INTEL_82810_GC: 336 case PCI_PRODUCT_INTEL_82810_DC100_GC: 337 case PCI_PRODUCT_INTEL_82810E_GC: 338 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 339 isc->chiptype = CHIP_I810; 340 aprint_normal(": i810-family chipset\n"); 341 break; 342 case PCI_PRODUCT_INTEL_82830MP_IV: 343 case PCI_PRODUCT_INTEL_82845G_IGD: 344 isc->chiptype = CHIP_I830; 345 aprint_normal(": i830-family chipset\n"); 346 break; 347 case PCI_PRODUCT_INTEL_82855GM_IGD: 348 case PCI_PRODUCT_INTEL_82865_IGD: 349 isc->chiptype = CHIP_I855; 350 aprint_normal(": i855-family chipset\n"); 351 break; 352 case PCI_PRODUCT_INTEL_82915G_IGD: 353 case PCI_PRODUCT_INTEL_82915GM_IGD: 354 case PCI_PRODUCT_INTEL_82945P_IGD: 355 case PCI_PRODUCT_INTEL_82945GM_IGD: 356 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 357 case PCI_PRODUCT_INTEL_82945GME_IGD: 358 case PCI_PRODUCT_INTEL_E7221_IGD: 359 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 360 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 361 isc->chiptype = CHIP_I915; 362 aprint_normal(": i915-family chipset\n"); 363 break; 364 case PCI_PRODUCT_INTEL_82965Q_IGD: 365 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 366 case PCI_PRODUCT_INTEL_82965PM_IGD: 367 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 368 case PCI_PRODUCT_INTEL_82965G_IGD: 369 case PCI_PRODUCT_INTEL_82965G_IGD_1: 370 case PCI_PRODUCT_INTEL_82965GME_IGD: 371 case PCI_PRODUCT_INTEL_82946GZ_IGD: 372 case PCI_PRODUCT_INTEL_82G35_IGD: 373 case PCI_PRODUCT_INTEL_82G35_IGD_1: 374 isc->chiptype = CHIP_I965; 375 aprint_normal(": i965-family chipset\n"); 376 break; 377 case PCI_PRODUCT_INTEL_82Q35_IGD: 378 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 379 case PCI_PRODUCT_INTEL_82G33_IGD: 380 case PCI_PRODUCT_INTEL_82G33_IGD_1: 381 case PCI_PRODUCT_INTEL_82Q33_IGD: 382 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 383 isc->chiptype = CHIP_G33; 384 aprint_normal(": G33-family chipset\n"); 385 break; 386 case PCI_PRODUCT_INTEL_82GM45_IGD: 387 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 388 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 389 case PCI_PRODUCT_INTEL_82Q45_IGD: 390 case PCI_PRODUCT_INTEL_82G45_IGD: 391 case PCI_PRODUCT_INTEL_82G41_IGD: 392 case PCI_PRODUCT_INTEL_82B43_IGD: 393 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 394 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 395 isc->chiptype = CHIP_G4X; 396 aprint_normal(": G4X-family chipset\n"); 397 break; 398 } 399 aprint_naive("\n"); 400 401 mmadr_type = PCI_MAPREG_TYPE_MEM; 402 switch (isc->chiptype) { 403 case CHIP_I915: 404 case CHIP_G33: 405 apbase = AGP_I915_GMADR; 406 mmadr_bar = AGP_I915_MMADR; 407 isc->size = 512*1024; 408 gtt_bar = AGP_I915_GTTADR; 409 gtt_off = ~(bus_size_t)0; /* XXXGCC */ 410 break; 411 case CHIP_I965: 412 apbase = AGP_I965_GMADR; 413 mmadr_bar = AGP_I965_MMADR; 414 mmadr_type |= PCI_MAPREG_MEM_TYPE_64BIT; 415 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, 416 AGP_I965_MMADR, mmadr_type, NULL, &isc->size, NULL)) 417 isc->size = 512*1024; /* XXX */ 418 gtt_bar = 0; 419 gtt_off = AGP_I965_GTT; 420 break; 421 case CHIP_G4X: 422 apbase = AGP_I965_GMADR; 423 mmadr_bar = AGP_I965_MMADR; 424 mmadr_type |= PCI_MAPREG_MEM_TYPE_64BIT; 425 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, 426 AGP_I965_MMADR, mmadr_type, NULL, &isc->size, NULL)) 427 isc->size = 512*1024; /* XXX */ 428 gtt_bar = 0; 429 gtt_off = AGP_G4X_GTT; 430 break; 431 default: 432 apbase = AGP_I810_GMADR; 433 mmadr_bar = AGP_I810_MMADR; 434 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, 435 AGP_I810_MMADR, mmadr_type, NULL, &isc->size, NULL)) 436 isc->size = 512*1024; /* XXX */ 437 gtt_bar = 0; 438 gtt_off = AGP_I810_GTT; 439 break; 440 } 441 442 /* Map (or, rather, find the address and size of) the aperture. */ 443 if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) 444 error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase); 445 else 446 error = agp_map_aperture(&isc->vga_pa, sc, apbase); 447 if (error) { 448 aprint_error_dev(self, "can't map aperture: %d\n", error); 449 goto fail1; 450 } 451 452 /* Map the memory-mapped I/O registers, or the non-GTT part. */ 453 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, mmadr_bar, 454 mmadr_type, &mmadr, &mmadr_size, &mmadr_flags)) { 455 aprint_error_dev(self, "can't find MMIO registers\n"); 456 error = ENXIO; 457 goto fail1; 458 } 459 if (mmadr_size < isc->size) { 460 aprint_error_dev(self, "MMIO registers too small" 461 ": %"PRIuMAX" < %"PRIuMAX"\n", 462 (uintmax_t)mmadr_size, (uintmax_t)isc->size); 463 error = ENXIO; 464 goto fail1; 465 } 466 isc->bst = isc->vga_pa.pa_memt; 467 error = bus_space_map(isc->bst, mmadr, isc->size, mmadr_flags, 468 &isc->bsh); 469 if (error) { 470 aprint_error_dev(self, "can't map MMIO registers: %d\n", 471 error); 472 error = ENXIO; 473 goto fail1; 474 } 475 476 /* Set up a chipset flush page if necessary. */ 477 switch (isc->chiptype) { 478 case CHIP_I915: 479 case CHIP_I965: 480 case CHIP_G33: 481 case CHIP_G4X: 482 error = agp_i810_setup_chipset_flush_page(sc); 483 if (error) { 484 aprint_error_dev(self, 485 "can't set up chipset flush page: %d\n", error); 486 goto fail2; 487 } 488 break; 489 } 490 491 /* 492 * XXX horrible hack to allow drm code to use our mapping 493 * of VGA chip registers 494 */ 495 agp_i810_vga_regbase = mmadr; 496 agp_i810_vga_regsize = isc->size; 497 agp_i810_vga_bst = isc->bst; 498 agp_i810_vga_bsh = isc->bsh; 499 500 /* Initialize the chipset. */ 501 error = agp_i810_init(sc); 502 if (error) 503 goto fail3; 504 505 /* Map the GTT, from either part of the MMIO region or its own BAR. */ 506 if (gtt_bar == 0) { 507 isc->gtt_bst = isc->bst; 508 if ((mmadr_size - gtt_off) < isc->gtt_size) { 509 aprint_error_dev(self, "GTTMMADR too small for GTT" 510 ": (%"PRIxMAX" - %"PRIxMAX") < %"PRIxMAX"\n", 511 (uintmax_t)mmadr_size, 512 (uintmax_t)gtt_off, 513 (uintmax_t)isc->gtt_size); 514 error = ENXIO; 515 goto fail4; 516 } 517 /* 518 * Map the GTT separately if we can, so that we can map 519 * it prefetchable, but in early models, there are MMIO 520 * registers before and after the GTT, so we can only 521 * take a subregion. 522 */ 523 if (isc->size < gtt_off) 524 error = bus_space_map(isc->gtt_bst, (mmadr + gtt_off), 525 isc->gtt_size, mmadr_flags, &isc->gtt_bsh); 526 else 527 error = bus_space_subregion(isc->bst, isc->bsh, 528 gtt_off, isc->gtt_size, &isc->gtt_bsh); 529 if (error) { 530 aprint_error_dev(self, "can't map GTT: %d\n", error); 531 error = ENXIO; 532 goto fail4; 533 } 534 } else { 535 bus_size_t gtt_bar_size; 536 /* 537 * All chipsets with a separate BAR for the GTT, namely 538 * the i915 and G33 families, have 32-bit GTT BARs. 539 * 540 * XXX [citation needed] 541 */ 542 if (pci_mapreg_map(&isc->vga_pa, gtt_bar, PCI_MAPREG_TYPE_MEM, 543 0, 544 &isc->gtt_bst, &isc->gtt_bsh, NULL, >t_bar_size)) { 545 aprint_error_dev(self, "can't map GTT\n"); 546 error = ENXIO; 547 goto fail4; 548 } 549 if (gtt_bar_size != isc->gtt_size) { 550 aprint_error_dev(self, 551 "BAR size %"PRIxMAX 552 " mismatches detected GTT size %"PRIxMAX 553 "; trusting BAR\n", 554 (uintmax_t)gtt_bar_size, 555 (uintmax_t)isc->gtt_size); 556 isc->gtt_size = gtt_bar_size; 557 } 558 } 559 560 /* Power management. (XXX Nothing to save on suspend? Fishy...) */ 561 if (!pmf_device_register(self, NULL, agp_i810_resume)) 562 aprint_error_dev(self, "can't establish power handler\n"); 563 564 /* Match the generic AGP code's autoconf output format. */ 565 aprint_normal("%s", device_xname(self)); 566 567 /* Success! */ 568 return 0; 569 570 fail5: __unused 571 pmf_device_deregister(self); 572 if ((gtt_bar != 0) || (isc->size < gtt_off)) 573 bus_space_unmap(isc->gtt_bst, isc->gtt_bsh, isc->gtt_size); 574 isc->gtt_size = 0; 575 fail4: 576 #if notyet 577 agp_i810_fini(sc); 578 #endif 579 fail3: switch (isc->chiptype) { 580 case CHIP_I915: 581 case CHIP_I965: 582 case CHIP_G33: 583 case CHIP_G4X: 584 agp_i810_teardown_chipset_flush_page(sc); 585 break; 586 } 587 fail2: bus_space_unmap(isc->bst, isc->bsh, isc->size); 588 isc->size = 0; 589 fail1: free(isc, M_AGP); 590 sc->as_chipc = NULL; 591 fail0: agp_generic_detach(sc); 592 KASSERT(error); 593 return error; 594 } 595 596 static int 597 agp_i810_setup_chipset_flush_page(struct agp_softc *sc) 598 { 599 struct agp_i810_softc *const isc = sc->as_chipc; 600 const pci_chipset_tag_t pc = sc->as_pc; 601 const pcitag_t tag = sc->as_tag; 602 pcireg_t lo, hi; 603 bus_addr_t addr, minaddr, maxaddr; 604 int error; 605 606 /* We always use memory-mapped I/O. */ 607 isc->flush_bst = isc->vga_pa.pa_memt; 608 609 /* No page allocated yet. */ 610 isc->flush_addr = 0; 611 612 /* Read the PCI config register: 4-byte on gen3, 8-byte on gen>=4. */ 613 if (isc->chiptype == CHIP_I915) { 614 addr = pci_conf_read(pc, tag, AGP_I915_IFPADDR); 615 minaddr = PAGE_SIZE; /* XXX PCIBIOS_MIN_MEM? */ 616 maxaddr = UINT32_MAX; 617 } else { 618 hi = pci_conf_read(pc, tag, AGP_I965_IFPADDR+4); 619 lo = pci_conf_read(pc, tag, AGP_I965_IFPADDR); 620 /* 621 * Convert to uint64_t, rather than bus_addr_t which 622 * may be 32-bit, to avoid undefined behaviour with a 623 * too-wide shift. Since the BIOS doesn't know whether 624 * the OS will run 64-bit or with PAE, it ought to 625 * configure at most a 32-bit physical address, so 626 * let's print a warning in case that happens. 627 */ 628 addr = ((uint64_t)hi << 32) | lo; 629 if (hi) { 630 aprint_error_dev(sc->as_dev, 631 "BIOS configured >32-bit flush page address" 632 ": %"PRIx64"\n", ((uint64_t)hi << 32) | lo); 633 #if __i386__ && !PAE 634 return EIO; 635 #endif 636 } 637 minaddr = PAGE_SIZE; /* XXX PCIBIOS_MIN_MEM? */ 638 maxaddr = MIN(UINT64_MAX, ~(bus_addr_t)0); 639 } 640 641 /* Allocate or map a pre-allocated a page for it. */ 642 if (ISSET(addr, 1)) { 643 /* BIOS allocated it for us. Use that. */ 644 error = bus_space_map(isc->flush_bst, addr & ~1, PAGE_SIZE, 0, 645 &isc->flush_bsh); 646 if (error) 647 return error; 648 } else { 649 /* None allocated. Allocate one. */ 650 error = bus_space_alloc(isc->flush_bst, minaddr, maxaddr, 651 PAGE_SIZE, PAGE_SIZE, 0, 0, 652 &isc->flush_addr, &isc->flush_bsh); 653 if (error) 654 return error; 655 KASSERT(isc->flush_addr != 0); 656 /* Write it into the PCI config register. */ 657 addr = isc->flush_addr | 1; 658 if (isc->chiptype == CHIP_I915) { 659 pci_conf_write(pc, tag, AGP_I915_IFPADDR, addr); 660 } else { 661 hi = __SHIFTOUT(addr, __BITS(63, 32)); 662 lo = __SHIFTOUT(addr, __BITS(31, 0)); 663 pci_conf_write(pc, tag, AGP_I965_IFPADDR+4, hi); 664 pci_conf_write(pc, tag, AGP_I965_IFPADDR, lo); 665 } 666 } 667 668 /* Success! */ 669 return 0; 670 } 671 672 static void 673 agp_i810_teardown_chipset_flush_page(struct agp_softc *sc) 674 { 675 struct agp_i810_softc *const isc = sc->as_chipc; 676 677 if (isc->flush_addr) { 678 /* If we allocated a page, clear it. */ 679 if (isc->chiptype == CHIP_I915) { 680 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR, 681 0); 682 } else { 683 pci_conf_write(sc->as_pc, sc->as_tag, 684 AGP_I965_IFPADDR, 0); 685 pci_conf_write(sc->as_pc, sc->as_tag, 686 AGP_I965_IFPADDR + 4, 0); 687 } 688 isc->flush_addr = 0; 689 bus_space_free(isc->flush_bst, isc->flush_bsh, 690 PAGE_SIZE); 691 } else { 692 /* Otherwise, just unmap the pre-allocated page. */ 693 bus_space_unmap(isc->flush_bst, isc->flush_bsh, PAGE_SIZE); 694 } 695 } 696 697 /* 698 * XXX horrible hack to allow drm code to use our mapping 699 * of VGA chip registers 700 */ 701 int 702 agp_i810_borrow(bus_addr_t base, bus_size_t size, bus_space_handle_t *hdlp) 703 { 704 705 if (agp_i810_vga_regbase == 0) 706 return 0; 707 if (base < agp_i810_vga_regbase) 708 return 0; 709 if (agp_i810_vga_regsize < size) 710 return 0; 711 if ((base - agp_i810_vga_regbase) > (agp_i810_vga_regsize - size)) 712 return 0; 713 if (bus_space_subregion(agp_i810_vga_bst, agp_i810_vga_bsh, 714 (base - agp_i810_vga_regbase), (agp_i810_vga_regsize - size), 715 hdlp)) 716 return 0; 717 return 1; 718 } 719 720 static int 721 agp_i810_init(struct agp_softc *sc) 722 { 723 struct agp_i810_softc *isc; 724 int error; 725 726 isc = sc->as_chipc; 727 728 if (isc->chiptype == CHIP_I810) { 729 struct agp_gatt *gatt; 730 void *virtual; 731 int dummyseg; 732 733 /* Some i810s have on-chip memory called dcache */ 734 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 735 isc->dcache_size = 4 * 1024 * 1024; 736 else 737 isc->dcache_size = 0; 738 739 /* According to the specs the gatt on the i810 must be 64k */ 740 isc->gtt_size = 64 * 1024; 741 gatt = malloc(sizeof(*gatt), M_AGP, M_NOWAIT); 742 if (gatt == NULL) { 743 aprint_error_dev(sc->as_dev, 744 "can't malloc GATT record\n"); 745 error = ENOMEM; 746 goto fail0; 747 } 748 gatt->ag_entries = isc->gtt_size / sizeof(uint32_t); 749 error = agp_alloc_dmamem(sc->as_dmat, isc->gtt_size, 750 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical, 751 &gatt->ag_dmaseg, 1, &dummyseg); 752 if (error) { 753 aprint_error_dev(sc->as_dev, 754 "can't allocate memory for GTT: %d\n", error); 755 free(gatt, M_AGP); 756 goto fail0; 757 } 758 759 gatt->ag_virtual = (uint32_t *)virtual; 760 gatt->ag_size = gatt->ag_entries * sizeof(uint32_t); 761 memset(gatt->ag_virtual, 0, gatt->ag_size); 762 agp_flush_cache(); 763 764 /* Install the GATT. */ 765 isc->pgtblctl = gatt->ag_physical | 1; 766 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 767 isc->gatt = gatt; 768 } else if (isc->chiptype == CHIP_I830) { 769 /* The i830 automatically initializes the 128k gatt on boot. */ 770 /* XXX [citation needed] */ 771 pcireg_t reg; 772 u_int16_t gcc1; 773 774 isc->gtt_size = 128 * 1024; 775 776 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 777 gcc1 = (u_int16_t)(reg >> 16); 778 switch (gcc1 & AGP_I830_GCC1_GMS) { 779 case AGP_I830_GCC1_GMS_STOLEN_512: 780 isc->stolen = (512 - 132) * 1024 / 4096; 781 break; 782 case AGP_I830_GCC1_GMS_STOLEN_1024: 783 isc->stolen = (1024 - 132) * 1024 / 4096; 784 break; 785 case AGP_I830_GCC1_GMS_STOLEN_8192: 786 isc->stolen = (8192 - 132) * 1024 / 4096; 787 break; 788 default: 789 isc->stolen = 0; 790 aprint_error_dev(sc->as_dev, 791 "unknown memory configuration, disabling\n"); 792 error = ENXIO; 793 goto fail0; 794 } 795 796 if (isc->stolen > 0) { 797 aprint_normal_dev(sc->as_dev, 798 "detected %dk stolen memory\n", 799 isc->stolen * 4); 800 } 801 802 /* GATT address is already in there, make sure it's enabled */ 803 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 804 isc->pgtblctl |= 1; 805 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 806 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 807 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 || 808 isc->chiptype == CHIP_G4X) { 809 pcireg_t reg; 810 u_int32_t gtt_size, stolen; /* XXX kilobytes */ 811 u_int16_t gcc1; 812 813 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1); 814 gcc1 = (u_int16_t)(reg >> 16); 815 816 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 817 818 /* Stolen memory is set up at the beginning of the aperture by 819 * the BIOS, consisting of the GATT followed by 4kb for the 820 * BIOS display. 821 */ 822 switch (isc->chiptype) { 823 case CHIP_I855: 824 gtt_size = 128; 825 break; 826 case CHIP_I915: 827 gtt_size = 256; 828 break; 829 case CHIP_I965: 830 switch (isc->pgtblctl & AGP_I810_PGTBL_SIZE_MASK) { 831 case AGP_I810_PGTBL_SIZE_128KB: 832 case AGP_I810_PGTBL_SIZE_512KB: 833 gtt_size = 512; 834 break; 835 case AGP_I965_PGTBL_SIZE_1MB: 836 gtt_size = 1024; 837 break; 838 case AGP_I965_PGTBL_SIZE_2MB: 839 gtt_size = 2048; 840 break; 841 case AGP_I965_PGTBL_SIZE_1_5MB: 842 gtt_size = 1024 + 512; 843 break; 844 default: 845 aprint_error_dev(sc->as_dev, 846 "bad PGTBL size\n"); 847 error = ENXIO; 848 goto fail0; 849 } 850 break; 851 case CHIP_G33: 852 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 853 case AGP_G33_PGTBL_SIZE_1M: 854 gtt_size = 1024; 855 break; 856 case AGP_G33_PGTBL_SIZE_2M: 857 gtt_size = 2048; 858 break; 859 default: 860 aprint_error_dev(sc->as_dev, 861 "bad PGTBL size\n"); 862 error = ENXIO; 863 goto fail0; 864 } 865 break; 866 case CHIP_G4X: 867 switch (isc->pgtblctl & AGP_G4X_PGTBL_SIZE_MASK) { 868 case AGP_G4X_PGTBL_SIZE_512K: 869 gtt_size = 512; 870 break; 871 case AGP_G4X_PGTBL_SIZE_256K: 872 gtt_size = 256; 873 break; 874 case AGP_G4X_PGTBL_SIZE_128K: 875 gtt_size = 128; 876 break; 877 case AGP_G4X_PGTBL_SIZE_1M: 878 gtt_size = 1*1024; 879 break; 880 case AGP_G4X_PGTBL_SIZE_2M: 881 gtt_size = 2*1024; 882 break; 883 case AGP_G4X_PGTBL_SIZE_1_5M: 884 gtt_size = 1*1024 + 512; 885 break; 886 default: 887 aprint_error_dev(sc->as_dev, 888 "bad PGTBL size\n"); 889 error = ENXIO; 890 goto fail0; 891 } 892 break; 893 default: 894 panic("impossible chiptype %d", isc->chiptype); 895 } 896 897 /* 898 * XXX If I'm reading the datasheets right, this stolen 899 * memory detection logic is totally wrong. 900 */ 901 switch (gcc1 & AGP_I855_GCC1_GMS) { 902 case AGP_I855_GCC1_GMS_STOLEN_1M: 903 stolen = 1024; 904 break; 905 case AGP_I855_GCC1_GMS_STOLEN_4M: 906 stolen = 4 * 1024; 907 break; 908 case AGP_I855_GCC1_GMS_STOLEN_8M: 909 stolen = 8 * 1024; 910 break; 911 case AGP_I855_GCC1_GMS_STOLEN_16M: 912 stolen = 16 * 1024; 913 break; 914 case AGP_I855_GCC1_GMS_STOLEN_32M: 915 stolen = 32 * 1024; 916 break; 917 case AGP_I915_GCC1_GMS_STOLEN_48M: 918 stolen = 48 * 1024; 919 break; 920 case AGP_I915_GCC1_GMS_STOLEN_64M: 921 stolen = 64 * 1024; 922 break; 923 case AGP_G33_GCC1_GMS_STOLEN_128M: 924 stolen = 128 * 1024; 925 break; 926 case AGP_G33_GCC1_GMS_STOLEN_256M: 927 stolen = 256 * 1024; 928 break; 929 case AGP_G4X_GCC1_GMS_STOLEN_96M: 930 stolen = 96 * 1024; 931 break; 932 case AGP_G4X_GCC1_GMS_STOLEN_160M: 933 stolen = 160 * 1024; 934 break; 935 case AGP_G4X_GCC1_GMS_STOLEN_224M: 936 stolen = 224 * 1024; 937 break; 938 case AGP_G4X_GCC1_GMS_STOLEN_352M: 939 stolen = 352 * 1024; 940 break; 941 default: 942 aprint_error_dev(sc->as_dev, 943 "unknown memory configuration, disabling\n"); 944 error = ENXIO; 945 goto fail0; 946 } 947 948 switch (gcc1 & AGP_I855_GCC1_GMS) { 949 case AGP_I915_GCC1_GMS_STOLEN_48M: 950 case AGP_I915_GCC1_GMS_STOLEN_64M: 951 if (isc->chiptype != CHIP_I915 && 952 isc->chiptype != CHIP_I965 && 953 isc->chiptype != CHIP_G33 && 954 isc->chiptype != CHIP_G4X) 955 stolen = 0; 956 break; 957 case AGP_G33_GCC1_GMS_STOLEN_128M: 958 case AGP_G33_GCC1_GMS_STOLEN_256M: 959 if (isc->chiptype != CHIP_I965 && 960 isc->chiptype != CHIP_G33 && 961 isc->chiptype != CHIP_G4X) 962 stolen = 0; 963 break; 964 case AGP_G4X_GCC1_GMS_STOLEN_96M: 965 case AGP_G4X_GCC1_GMS_STOLEN_160M: 966 case AGP_G4X_GCC1_GMS_STOLEN_224M: 967 case AGP_G4X_GCC1_GMS_STOLEN_352M: 968 if (isc->chiptype != CHIP_I965 && 969 isc->chiptype != CHIP_G4X) 970 stolen = 0; 971 break; 972 } 973 974 isc->gtt_size = gtt_size * 1024; 975 976 /* BIOS space */ 977 /* XXX [citation needed] */ 978 gtt_size += 4; 979 980 /* XXX [citation needed] for this subtraction */ 981 isc->stolen = (stolen - gtt_size) * 1024 / 4096; 982 983 if (isc->stolen > 0) { 984 aprint_normal_dev(sc->as_dev, 985 "detected %dk stolen memory\n", 986 isc->stolen * 4); 987 } 988 989 /* GATT address is already in there, make sure it's enabled */ 990 isc->pgtblctl |= 1; 991 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 992 } 993 994 /* 995 * Make sure the chipset can see everything. 996 */ 997 agp_flush_cache(); 998 999 /* 1000 * Publish what we found for kludgey drivers (I'm looking at 1001 * you, drm). 1002 */ 1003 if (agp_i810_sc == NULL) 1004 agp_i810_sc = sc; 1005 else 1006 aprint_error_dev(sc->as_dev, "agp already attached\n"); 1007 1008 /* Success! */ 1009 return 0; 1010 1011 fail0: KASSERT(error); 1012 return error; 1013 } 1014 1015 #if 0 1016 static int 1017 agp_i810_detach(struct agp_softc *sc) 1018 { 1019 int error; 1020 struct agp_i810_softc *isc = sc->as_chipc; 1021 1022 error = agp_generic_detach(sc); 1023 if (error) 1024 return error; 1025 1026 switch (isc->chiptype) { 1027 case CHIP_I915: 1028 case CHIP_I965: 1029 case CHIP_G33: 1030 case CHIP_G4X: 1031 agp_i810_teardown_chipset_flush_page(sc); 1032 break; 1033 } 1034 1035 /* Clear the GATT base. */ 1036 if (sc->chiptype == CHIP_I810) { 1037 WRITE4(AGP_I810_PGTBL_CTL, 0); 1038 } else { 1039 unsigned int pgtblctl; 1040 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 1041 pgtblctl &= ~1; 1042 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 1043 } 1044 1045 if (sc->chiptype == CHIP_I810) { 1046 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap, 1047 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 1048 free(isc->gatt, M_AGP); 1049 } 1050 1051 return 0; 1052 } 1053 #endif 1054 1055 static u_int32_t 1056 agp_i810_get_aperture(struct agp_softc *sc) 1057 { 1058 struct agp_i810_softc *isc = sc->as_chipc; 1059 pcireg_t reg; 1060 u_int32_t size; 1061 u_int16_t miscc, gcc1; 1062 1063 size = 0; 1064 1065 switch (isc->chiptype) { 1066 case CHIP_I810: 1067 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 1068 miscc = (u_int16_t)(reg >> 16); 1069 if ((miscc & AGP_I810_MISCC_WINSIZE) == 1070 AGP_I810_MISCC_WINSIZE_32) 1071 size = 32 * 1024 * 1024; 1072 else 1073 size = 64 * 1024 * 1024; 1074 break; 1075 case CHIP_I830: 1076 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 1077 gcc1 = (u_int16_t)(reg >> 16); 1078 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 1079 size = 64 * 1024 * 1024; 1080 else 1081 size = 128 * 1024 * 1024; 1082 break; 1083 case CHIP_I855: 1084 size = 128 * 1024 * 1024; 1085 break; 1086 case CHIP_I915: 1087 case CHIP_G33: 1088 case CHIP_G4X: 1089 size = sc->as_apsize; 1090 break; 1091 case CHIP_I965: 1092 size = 512 * 1024 * 1024; 1093 break; 1094 default: 1095 aprint_error(": Unknown chipset\n"); 1096 } 1097 1098 return size; 1099 } 1100 1101 static int 1102 agp_i810_set_aperture(struct agp_softc *sc __unused, 1103 uint32_t aperture __unused) 1104 { 1105 1106 return ENOSYS; 1107 } 1108 1109 static int 1110 agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 1111 { 1112 struct agp_i810_softc *isc = sc->as_chipc; 1113 1114 if (offset < 0 || offset >= ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) { 1115 DPRINTF(sc, "failed" 1116 ": offset 0x%"PRIxMAX", shift %u, entries %"PRIuMAX"\n", 1117 (uintmax_t)offset, 1118 (unsigned)AGP_PAGE_SHIFT, 1119 (uintmax_t)isc->gtt_size/4); 1120 return EINVAL; 1121 } 1122 1123 if (isc->chiptype != CHIP_I810) { 1124 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1125 DPRINTF(sc, "trying to bind into stolen memory\n"); 1126 return EINVAL; 1127 } 1128 } 1129 1130 return agp_i810_write_gtt_entry(isc, offset, physical | 1); 1131 } 1132 1133 static int 1134 agp_i810_unbind_page(struct agp_softc *sc, off_t offset) 1135 { 1136 struct agp_i810_softc *isc = sc->as_chipc; 1137 1138 if (offset < 0 || offset >= ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) 1139 return EINVAL; 1140 1141 if (isc->chiptype != CHIP_I810 ) { 1142 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1143 DPRINTF(sc, "trying to unbind from stolen memory\n"); 1144 return EINVAL; 1145 } 1146 } 1147 1148 return agp_i810_write_gtt_entry(isc, offset, 0); 1149 } 1150 1151 /* 1152 * Writing via memory mapped registers already flushes all TLBs. 1153 */ 1154 static void 1155 agp_i810_flush_tlb(struct agp_softc *sc) 1156 { 1157 } 1158 1159 static int 1160 agp_i810_enable(struct agp_softc *sc, u_int32_t mode) 1161 { 1162 1163 return 0; 1164 } 1165 1166 #define AGP_I810_MEMTYPE_MAIN 0 1167 #define AGP_I810_MEMTYPE_DCACHE 1 1168 #define AGP_I810_MEMTYPE_HWCURSOR 2 1169 1170 static struct agp_memory * 1171 agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size) 1172 { 1173 struct agp_i810_softc *isc = sc->as_chipc; 1174 struct agp_memory *mem; 1175 int error; 1176 1177 DPRINTF(sc, "AGP: alloc(%d, 0x%"PRIxMAX")\n", type, (uintmax_t)size); 1178 1179 if (size <= 0) 1180 return NULL; 1181 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 1182 return NULL; 1183 KASSERT(sc->as_allocated <= sc->as_maxmem); 1184 if (size > (sc->as_maxmem - sc->as_allocated)) 1185 return NULL; 1186 if (size > ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) 1187 return NULL; 1188 1189 switch (type) { 1190 case AGP_I810_MEMTYPE_MAIN: 1191 break; 1192 case AGP_I810_MEMTYPE_DCACHE: 1193 if (isc->chiptype != CHIP_I810) 1194 return NULL; 1195 if (size != isc->dcache_size) 1196 return NULL; 1197 break; 1198 case AGP_I810_MEMTYPE_HWCURSOR: 1199 if ((size != AGP_PAGE_SIZE) && 1200 (size != AGP_PAGE_SIZE*4)) 1201 return NULL; 1202 break; 1203 default: 1204 return NULL; 1205 } 1206 1207 mem = malloc(sizeof(*mem), M_AGP, M_WAITOK|M_ZERO); 1208 if (mem == NULL) 1209 goto fail0; 1210 mem->am_id = sc->as_nextid++; 1211 mem->am_size = size; 1212 mem->am_type = type; 1213 1214 switch (type) { 1215 case AGP_I810_MEMTYPE_MAIN: 1216 error = bus_dmamap_create(sc->as_dmat, size, 1217 (size >> AGP_PAGE_SHIFT) + 1, size, 0, BUS_DMA_WAITOK, 1218 &mem->am_dmamap); 1219 if (error) 1220 goto fail1; 1221 break; 1222 case AGP_I810_MEMTYPE_DCACHE: 1223 break; 1224 case AGP_I810_MEMTYPE_HWCURSOR: 1225 mem->am_dmaseg = malloc(sizeof(*mem->am_dmaseg), M_AGP, 1226 M_WAITOK); 1227 error = agp_alloc_dmamem(sc->as_dmat, size, 0, &mem->am_dmamap, 1228 &mem->am_virtual, &mem->am_physical, mem->am_dmaseg, 1, 1229 &mem->am_nseg); 1230 if (error) { 1231 free(mem->am_dmaseg, M_AGP); 1232 goto fail1; 1233 } 1234 (void)memset(mem->am_virtual, 0, size); 1235 break; 1236 default: 1237 panic("invalid agp memory type: %d", type); 1238 } 1239 1240 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link); 1241 sc->as_allocated += size; 1242 1243 return mem; 1244 1245 fail1: free(mem, M_AGP); 1246 fail0: return NULL; 1247 } 1248 1249 static int 1250 agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem) 1251 { 1252 1253 if (mem->am_is_bound) 1254 return EBUSY; 1255 1256 switch (mem->am_type) { 1257 case AGP_I810_MEMTYPE_MAIN: 1258 bus_dmamap_destroy(sc->as_dmat, mem->am_dmamap); 1259 break; 1260 case AGP_I810_MEMTYPE_DCACHE: 1261 break; 1262 case AGP_I810_MEMTYPE_HWCURSOR: 1263 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap, 1264 mem->am_virtual, mem->am_dmaseg, mem->am_nseg); 1265 free(mem->am_dmaseg, M_AGP); 1266 break; 1267 default: 1268 panic("invalid agp i810 memory type: %d", mem->am_type); 1269 } 1270 1271 sc->as_allocated -= mem->am_size; 1272 TAILQ_REMOVE(&sc->as_memory, mem, am_link); 1273 free(mem, M_AGP); 1274 1275 return 0; 1276 } 1277 1278 static int 1279 agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem, 1280 off_t offset) 1281 { 1282 struct agp_i810_softc *isc = sc->as_chipc; 1283 uint32_t pgtblctl; 1284 int error; 1285 1286 if (mem->am_is_bound) 1287 return EINVAL; 1288 1289 /* 1290 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 1291 * X server for mysterious reasons which leads to crashes if we write 1292 * to the GTT through the MMIO window. 1293 * Until the issue is solved, simply restore it. 1294 */ 1295 pgtblctl = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL); 1296 if (pgtblctl != isc->pgtblctl) { 1297 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%"PRIx32 1298 " - fixing\n", pgtblctl); 1299 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 1300 isc->pgtblctl); 1301 } 1302 1303 switch (mem->am_type) { 1304 case AGP_I810_MEMTYPE_MAIN: 1305 return agp_generic_bind_memory_bounded(sc, mem, offset, 1306 0, (isc->gtt_size/4) << AGP_PAGE_SHIFT); 1307 case AGP_I810_MEMTYPE_DCACHE: 1308 error = agp_i810_bind_memory_dcache(sc, mem, offset); 1309 break; 1310 case AGP_I810_MEMTYPE_HWCURSOR: 1311 error = agp_i810_bind_memory_hwcursor(sc, mem, offset); 1312 break; 1313 default: 1314 panic("invalid agp i810 memory type: %d", mem->am_type); 1315 } 1316 if (error) 1317 return error; 1318 1319 /* Success! */ 1320 mem->am_is_bound = 1; 1321 return 0; 1322 } 1323 1324 #define I810_GTT_PTE_VALID 0x01 1325 #define I810_GTT_PTE_DCACHE 0x02 1326 1327 static int 1328 agp_i810_bind_memory_dcache(struct agp_softc *sc, struct agp_memory *mem, 1329 off_t offset) 1330 { 1331 struct agp_i810_softc *const isc __diagused = sc->as_chipc; 1332 uint32_t i, j; 1333 int error; 1334 1335 KASSERT(isc->chiptype == CHIP_I810); 1336 1337 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0); 1338 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 1339 error = agp_i810_write_gtt_entry(isc, offset + i, 1340 i | I810_GTT_PTE_VALID | I810_GTT_PTE_DCACHE); 1341 if (error) 1342 goto fail0; 1343 } 1344 1345 /* Success! */ 1346 mem->am_offset = offset; 1347 return 0; 1348 1349 fail0: for (j = 0; j < i; j += AGP_PAGE_SIZE) 1350 (void)agp_i810_unbind_page(sc, offset + j); 1351 return error; 1352 } 1353 1354 static int 1355 agp_i810_bind_memory_hwcursor(struct agp_softc *sc, struct agp_memory *mem, 1356 off_t offset) 1357 { 1358 const bus_addr_t pa = mem->am_physical; 1359 uint32_t i, j; 1360 int error; 1361 1362 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0); 1363 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 1364 error = agp_i810_bind_page(sc, offset + i, pa + i); 1365 if (error) 1366 goto fail0; 1367 } 1368 1369 /* Success! */ 1370 mem->am_offset = offset; 1371 return 0; 1372 1373 fail0: for (j = 0; j < i; j += AGP_PAGE_SIZE) 1374 (void)agp_i810_unbind_page(sc, offset + j); 1375 return error; 1376 } 1377 1378 static int 1379 agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem) 1380 { 1381 struct agp_i810_softc *isc __diagused = sc->as_chipc; 1382 u_int32_t i; 1383 1384 if (!mem->am_is_bound) 1385 return EINVAL; 1386 1387 switch (mem->am_type) { 1388 case AGP_I810_MEMTYPE_MAIN: 1389 return agp_generic_unbind_memory(sc, mem); 1390 case AGP_I810_MEMTYPE_DCACHE: 1391 KASSERT(isc->chiptype == CHIP_I810); 1392 /* FALLTHROUGH */ 1393 case AGP_I810_MEMTYPE_HWCURSOR: 1394 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1395 (void)agp_i810_unbind_page(sc, mem->am_offset + i); 1396 mem->am_offset = 0; 1397 break; 1398 default: 1399 panic("invalid agp i810 memory type: %d", mem->am_type); 1400 } 1401 1402 mem->am_is_bound = 0; 1403 return 0; 1404 } 1405 1406 static bool 1407 agp_i810_resume(device_t dv, const pmf_qual_t *qual) 1408 { 1409 struct agp_softc *sc = device_private(dv); 1410 struct agp_i810_softc *isc = sc->as_chipc; 1411 1412 /* 1413 * XXX Nothing uses this! Save on suspend, restore on resume? 1414 */ 1415 isc->pgtblctl_resume_hack = READ4(AGP_I810_PGTBL_CTL); 1416 agp_flush_cache(); 1417 1418 return true; 1419 } 1420
Indexes created Wed Sep 24 22:09:59 GMT 2025