agp_i810.c revision 1.116
1 /* $NetBSD: agp_i810.c,v 1.116 2015/02/26 00:58:17 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.116 2015/02/26 00:58:17 riastradh Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/atomic.h> 38 #include <sys/malloc.h> 39 #include <sys/kernel.h> 40 #include <sys/proc.h> 41 #include <sys/device.h> 42 #include <sys/conf.h> 43 #include <sys/xcall.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/agpvar.h> 49 #include <dev/pci/agpreg.h> 50 #include <dev/pci/agp_i810var.h> 51 52 #include <sys/agpio.h> 53 54 #include <sys/bus.h> 55 56 #include "agp_intel.h" 57 58 #ifdef AGP_DEBUG 59 #define DPRINTF(sc, fmt, ...) \ 60 device_printf((sc)->as_dev, "%s: " fmt, __func__, ##__VA_ARGS__) 61 #else 62 #define DPRINTF(sc, fmt, ...) do {} while (0) 63 #endif 64 65 struct agp_softc *agp_i810_sc = NULL; 66 67 #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off) 68 #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off) 69 #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v) 70 71 #define CHIP_I810 0 /* i810/i815 */ 72 #define CHIP_I830 1 /* 830M/845G */ 73 #define CHIP_I855 2 /* 852GM/855GM/865G */ 74 #define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */ 75 #define CHIP_I965 4 /* 965Q/965PM */ 76 #define CHIP_G33 5 /* G33/Q33/Q35 */ 77 #define CHIP_G4X 6 /* G45/Q45 */ 78 79 /* XXX hack, see below */ 80 static bus_addr_t agp_i810_vga_regbase; 81 static bus_size_t agp_i810_vga_regsize; 82 static bus_space_tag_t agp_i810_vga_bst; 83 static bus_space_handle_t agp_i810_vga_bsh; 84 85 static u_int32_t agp_i810_get_aperture(struct agp_softc *); 86 static int agp_i810_set_aperture(struct agp_softc *, u_int32_t); 87 static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t); 88 static int agp_i810_unbind_page(struct agp_softc *, off_t); 89 static void agp_i810_flush_tlb(struct agp_softc *); 90 static int agp_i810_enable(struct agp_softc *, u_int32_t mode); 91 static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int, 92 vsize_t); 93 static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *); 94 static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, 95 off_t); 96 static int agp_i810_bind_memory_dcache(struct agp_softc *, struct agp_memory *, 97 off_t); 98 static int agp_i810_bind_memory_hwcursor(struct agp_softc *, 99 struct agp_memory *, off_t); 100 static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *); 101 102 static bool agp_i810_resume(device_t, const pmf_qual_t *); 103 static int agp_i810_init(struct agp_softc *); 104 105 static int agp_i810_setup_chipset_flush_page(struct agp_softc *); 106 static void agp_i810_teardown_chipset_flush_page(struct agp_softc *); 107 static int agp_i810_init(struct agp_softc *); 108 109 static struct agp_methods agp_i810_methods = { 110 agp_i810_get_aperture, 111 agp_i810_set_aperture, 112 agp_i810_bind_page, 113 agp_i810_unbind_page, 114 agp_i810_flush_tlb, 115 agp_i810_enable, 116 agp_i810_alloc_memory, 117 agp_i810_free_memory, 118 agp_i810_bind_memory, 119 agp_i810_unbind_memory, 120 }; 121 122 int 123 agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, bus_addr_t v) 124 { 125 u_int32_t pte; 126 127 /* Bits 11:4 (physical start address extension) should be zero. */ 128 if ((v & 0xff0) != 0) 129 return EINVAL; 130 131 pte = (u_int32_t)v; 132 /* 133 * We need to massage the pte if bus_addr_t is wider than 32 bits. 134 * The compiler isn't smart enough, hence the casts to uintmax_t. 135 */ 136 if (sizeof(bus_addr_t) > sizeof(u_int32_t)) { 137 /* 965+ can do 36-bit addressing, add in the extra bits. */ 138 if (isc->chiptype == CHIP_I965 || 139 isc->chiptype == CHIP_G33 || 140 isc->chiptype == CHIP_G4X) { 141 if (((uintmax_t)v >> 36) != 0) 142 return EINVAL; 143 pte |= (v >> 28) & 0xf0; 144 } else { 145 if (((uintmax_t)v >> 32) != 0) 146 return EINVAL; 147 } 148 } 149 150 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, 151 4*(off >> AGP_PAGE_SHIFT), pte); 152 153 return 0; 154 } 155 156 void 157 agp_i810_post_gtt_entry(struct agp_i810_softc *isc, off_t off) 158 { 159 160 /* 161 * See <https://bugs.freedesktop.org/show_bug.cgi?id=88191>. 162 * Out of paranoia, let's do the write barrier and posting 163 * read, because I don't have enough time or hardware to 164 * conduct conclusive tests. 165 */ 166 membar_producer(); 167 (void)bus_space_read_4(isc->gtt_bst, isc->gtt_bsh, 168 4*(off >> AGP_PAGE_SHIFT)); 169 } 170 171 static void 172 agp_flush_cache_xc(void *a __unused, void *b __unused) 173 { 174 175 agp_flush_cache(); 176 } 177 178 void 179 agp_i810_chipset_flush(struct agp_i810_softc *isc) 180 { 181 unsigned int timo = 20000; /* * 50 us = 1 s */ 182 183 switch (isc->chiptype) { 184 case CHIP_I810: 185 break; 186 case CHIP_I830: 187 case CHIP_I855: 188 /* 189 * Flush all CPU caches. If we're cold, we can't run 190 * xcalls, but there should be only one CPU up, so 191 * flushing only the local CPU's cache should suffice. 192 * 193 * XXX Come to think of it, do these chipsets appear in 194 * any multi-CPU systems? 195 */ 196 if (cold) 197 agp_flush_cache(); 198 else 199 xc_wait(xc_broadcast(0, &agp_flush_cache_xc, 200 NULL, NULL)); 201 WRITE4(AGP_I830_HIC, READ4(AGP_I830_HIC) | __BIT(31)); 202 while (ISSET(READ4(AGP_I830_HIC), __BIT(31))) { 203 if (timo-- == 0) 204 break; 205 DELAY(50); 206 } 207 break; 208 case CHIP_I915: 209 case CHIP_I965: 210 case CHIP_G33: 211 case CHIP_G4X: 212 bus_space_write_4(isc->flush_bst, isc->flush_bsh, 0, 1); 213 break; 214 } 215 } 216 217 /* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */ 218 static int 219 agp_i810_vgamatch(const struct pci_attach_args *pa) 220 { 221 222 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 223 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 224 return (0); 225 226 switch (PCI_PRODUCT(pa->pa_id)) { 227 case PCI_PRODUCT_INTEL_82810_GC: 228 case PCI_PRODUCT_INTEL_82810_DC100_GC: 229 case PCI_PRODUCT_INTEL_82810E_GC: 230 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 231 case PCI_PRODUCT_INTEL_82830MP_IV: 232 case PCI_PRODUCT_INTEL_82845G_IGD: 233 case PCI_PRODUCT_INTEL_82855GM_IGD: 234 case PCI_PRODUCT_INTEL_82865_IGD: 235 case PCI_PRODUCT_INTEL_82915G_IGD: 236 case PCI_PRODUCT_INTEL_82915GM_IGD: 237 case PCI_PRODUCT_INTEL_82945P_IGD: 238 case PCI_PRODUCT_INTEL_82945GM_IGD: 239 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 240 case PCI_PRODUCT_INTEL_82945GME_IGD: 241 case PCI_PRODUCT_INTEL_E7221_IGD: 242 case PCI_PRODUCT_INTEL_82965Q_IGD: 243 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 244 case PCI_PRODUCT_INTEL_82965PM_IGD: 245 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 246 case PCI_PRODUCT_INTEL_82G33_IGD: 247 case PCI_PRODUCT_INTEL_82G33_IGD_1: 248 case PCI_PRODUCT_INTEL_82965G_IGD: 249 case PCI_PRODUCT_INTEL_82965G_IGD_1: 250 case PCI_PRODUCT_INTEL_82965GME_IGD: 251 case PCI_PRODUCT_INTEL_82Q35_IGD: 252 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 253 case PCI_PRODUCT_INTEL_82Q33_IGD: 254 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 255 case PCI_PRODUCT_INTEL_82G35_IGD: 256 case PCI_PRODUCT_INTEL_82G35_IGD_1: 257 case PCI_PRODUCT_INTEL_82946GZ_IGD: 258 case PCI_PRODUCT_INTEL_82GM45_IGD: 259 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 260 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 261 case PCI_PRODUCT_INTEL_82Q45_IGD: 262 case PCI_PRODUCT_INTEL_82G45_IGD: 263 case PCI_PRODUCT_INTEL_82G41_IGD: 264 case PCI_PRODUCT_INTEL_82B43_IGD: 265 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 266 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 267 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 268 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 269 return (1); 270 } 271 272 return (0); 273 } 274 275 static int 276 agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg) 277 { 278 /* 279 * Find the aperture. Don't map it (yet), this would 280 * eat KVA. 281 */ 282 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 283 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize, 284 &sc->as_apflags) != 0) 285 return ENXIO; 286 287 sc->as_apt = pa->pa_memt; 288 289 return 0; 290 } 291 292 int 293 agp_i810_attach(device_t parent, device_t self, void *aux) 294 { 295 struct agp_softc *sc = device_private(self); 296 struct agp_i810_softc *isc; 297 int apbase, mmadr_bar, gtt_bar; 298 int mmadr_type, mmadr_flags; 299 bus_addr_t mmadr; 300 bus_size_t mmadr_size, gtt_off; 301 int error; 302 303 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 304 if (isc == NULL) { 305 aprint_error(": can't allocate chipset-specific softc\n"); 306 error = ENOMEM; 307 goto fail0; 308 } 309 sc->as_chipc = isc; 310 sc->as_methods = &agp_i810_methods; 311 312 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) { 313 #if NAGP_INTEL > 0 314 const struct pci_attach_args *pa = aux; 315 316 switch (PCI_PRODUCT(pa->pa_id)) { 317 case PCI_PRODUCT_INTEL_82840_HB: 318 case PCI_PRODUCT_INTEL_82865_HB: 319 case PCI_PRODUCT_INTEL_82845G_DRAM: 320 case PCI_PRODUCT_INTEL_82815_FULL_HUB: 321 case PCI_PRODUCT_INTEL_82855GM_MCH: 322 free(isc, M_AGP); 323 return agp_intel_attach(parent, self, aux); 324 } 325 #endif 326 aprint_error(": can't find internal VGA" 327 " config space\n"); 328 error = ENOENT; 329 goto fail1; 330 } 331 332 /* XXXfvdl */ 333 sc->as_dmat = isc->vga_pa.pa_dmat; 334 335 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 336 case PCI_PRODUCT_INTEL_82810_GC: 337 case PCI_PRODUCT_INTEL_82810_DC100_GC: 338 case PCI_PRODUCT_INTEL_82810E_GC: 339 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 340 isc->chiptype = CHIP_I810; 341 aprint_normal(": i810-family chipset\n"); 342 break; 343 case PCI_PRODUCT_INTEL_82830MP_IV: 344 case PCI_PRODUCT_INTEL_82845G_IGD: 345 isc->chiptype = CHIP_I830; 346 aprint_normal(": i830-family chipset\n"); 347 break; 348 case PCI_PRODUCT_INTEL_82855GM_IGD: 349 case PCI_PRODUCT_INTEL_82865_IGD: 350 isc->chiptype = CHIP_I855; 351 aprint_normal(": i855-family chipset\n"); 352 break; 353 case PCI_PRODUCT_INTEL_82915G_IGD: 354 case PCI_PRODUCT_INTEL_82915GM_IGD: 355 case PCI_PRODUCT_INTEL_82945P_IGD: 356 case PCI_PRODUCT_INTEL_82945GM_IGD: 357 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 358 case PCI_PRODUCT_INTEL_82945GME_IGD: 359 case PCI_PRODUCT_INTEL_E7221_IGD: 360 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 361 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 362 isc->chiptype = CHIP_I915; 363 aprint_normal(": i915-family chipset\n"); 364 break; 365 case PCI_PRODUCT_INTEL_82965Q_IGD: 366 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 367 case PCI_PRODUCT_INTEL_82965PM_IGD: 368 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 369 case PCI_PRODUCT_INTEL_82965G_IGD: 370 case PCI_PRODUCT_INTEL_82965G_IGD_1: 371 case PCI_PRODUCT_INTEL_82965GME_IGD: 372 case PCI_PRODUCT_INTEL_82946GZ_IGD: 373 case PCI_PRODUCT_INTEL_82G35_IGD: 374 case PCI_PRODUCT_INTEL_82G35_IGD_1: 375 isc->chiptype = CHIP_I965; 376 aprint_normal(": i965-family chipset\n"); 377 break; 378 case PCI_PRODUCT_INTEL_82Q35_IGD: 379 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 380 case PCI_PRODUCT_INTEL_82G33_IGD: 381 case PCI_PRODUCT_INTEL_82G33_IGD_1: 382 case PCI_PRODUCT_INTEL_82Q33_IGD: 383 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 384 isc->chiptype = CHIP_G33; 385 aprint_normal(": G33-family chipset\n"); 386 break; 387 case PCI_PRODUCT_INTEL_82GM45_IGD: 388 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 389 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 390 case PCI_PRODUCT_INTEL_82Q45_IGD: 391 case PCI_PRODUCT_INTEL_82G45_IGD: 392 case PCI_PRODUCT_INTEL_82G41_IGD: 393 case PCI_PRODUCT_INTEL_82B43_IGD: 394 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 395 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 396 isc->chiptype = CHIP_G4X; 397 aprint_normal(": G4X-family chipset\n"); 398 break; 399 } 400 aprint_naive("\n"); 401 402 mmadr_type = PCI_MAPREG_TYPE_MEM; 403 switch (isc->chiptype) { 404 case CHIP_I915: 405 case CHIP_G33: 406 apbase = AGP_I915_GMADR; 407 mmadr_bar = AGP_I915_MMADR; 408 isc->size = 512*1024; 409 gtt_bar = AGP_I915_GTTADR; 410 gtt_off = ~(bus_size_t)0; /* XXXGCC */ 411 break; 412 case CHIP_I965: 413 apbase = AGP_I965_GMADR; 414 mmadr_bar = AGP_I965_MMADR; 415 mmadr_type |= PCI_MAPREG_MEM_TYPE_64BIT; 416 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, 417 AGP_I965_MMADR, mmadr_type, NULL, &isc->size, NULL)) 418 isc->size = 512*1024; /* XXX */ 419 gtt_bar = 0; 420 gtt_off = AGP_I965_GTT; 421 break; 422 case CHIP_G4X: 423 apbase = AGP_I965_GMADR; 424 mmadr_bar = AGP_I965_MMADR; 425 mmadr_type |= PCI_MAPREG_MEM_TYPE_64BIT; 426 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, 427 AGP_I965_MMADR, mmadr_type, NULL, &isc->size, NULL)) 428 isc->size = 512*1024; /* XXX */ 429 gtt_bar = 0; 430 gtt_off = AGP_G4X_GTT; 431 break; 432 default: 433 apbase = AGP_I810_GMADR; 434 mmadr_bar = AGP_I810_MMADR; 435 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, 436 AGP_I810_MMADR, mmadr_type, NULL, &isc->size, NULL)) 437 isc->size = 512*1024; /* XXX */ 438 gtt_bar = 0; 439 gtt_off = AGP_I810_GTT; 440 break; 441 } 442 443 /* Map (or, rather, find the address and size of) the aperture. */ 444 if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) 445 error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase); 446 else 447 error = agp_map_aperture(&isc->vga_pa, sc, apbase); 448 if (error) { 449 aprint_error_dev(self, "can't map aperture: %d\n", error); 450 goto fail1; 451 } 452 453 /* Map the memory-mapped I/O registers, or the non-GTT part. */ 454 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, mmadr_bar, 455 mmadr_type, &mmadr, &mmadr_size, &mmadr_flags)) { 456 aprint_error_dev(self, "can't find MMIO registers\n"); 457 error = ENXIO; 458 goto fail1; 459 } 460 if (mmadr_size < isc->size) { 461 aprint_error_dev(self, "MMIO registers too small" 462 ": %"PRIuMAX" < %"PRIuMAX"\n", 463 (uintmax_t)mmadr_size, (uintmax_t)isc->size); 464 error = ENXIO; 465 goto fail1; 466 } 467 isc->bst = isc->vga_pa.pa_memt; 468 error = bus_space_map(isc->bst, mmadr, isc->size, mmadr_flags, 469 &isc->bsh); 470 if (error) { 471 aprint_error_dev(self, "can't map MMIO registers: %d\n", 472 error); 473 error = ENXIO; 474 goto fail1; 475 } 476 477 /* Set up a chipset flush page if necessary. */ 478 switch (isc->chiptype) { 479 case CHIP_I915: 480 case CHIP_I965: 481 case CHIP_G33: 482 case CHIP_G4X: 483 error = agp_i810_setup_chipset_flush_page(sc); 484 if (error) { 485 aprint_error_dev(self, 486 "can't set up chipset flush page: %d\n", error); 487 goto fail2; 488 } 489 break; 490 } 491 492 /* 493 * XXX horrible hack to allow drm code to use our mapping 494 * of VGA chip registers 495 */ 496 agp_i810_vga_regbase = mmadr; 497 agp_i810_vga_regsize = isc->size; 498 agp_i810_vga_bst = isc->bst; 499 agp_i810_vga_bsh = isc->bsh; 500 501 /* Initialize the chipset. */ 502 error = agp_i810_init(sc); 503 if (error) 504 goto fail3; 505 506 /* Map the GTT, from either part of the MMIO region or its own BAR. */ 507 if (gtt_bar == 0) { 508 isc->gtt_bst = isc->bst; 509 if ((mmadr_size - gtt_off) < isc->gtt_size) { 510 aprint_error_dev(self, "GTTMMADR too small for GTT" 511 ": (%"PRIxMAX" - %"PRIxMAX") < %"PRIxMAX"\n", 512 (uintmax_t)mmadr_size, 513 (uintmax_t)gtt_off, 514 (uintmax_t)isc->gtt_size); 515 error = ENXIO; 516 goto fail4; 517 } 518 /* 519 * Map the GTT separately if we can, so that we can map 520 * it prefetchable, but in early models, there are MMIO 521 * registers before and after the GTT, so we can only 522 * take a subregion. 523 */ 524 if (isc->size < gtt_off) 525 error = bus_space_map(isc->gtt_bst, (mmadr + gtt_off), 526 isc->gtt_size, mmadr_flags, &isc->gtt_bsh); 527 else 528 error = bus_space_subregion(isc->bst, isc->bsh, 529 gtt_off, isc->gtt_size, &isc->gtt_bsh); 530 if (error) { 531 aprint_error_dev(self, "can't map GTT: %d\n", error); 532 error = ENXIO; 533 goto fail4; 534 } 535 } else { 536 bus_size_t gtt_bar_size; 537 /* 538 * All chipsets with a separate BAR for the GTT, namely 539 * the i915 and G33 families, have 32-bit GTT BARs. 540 * 541 * XXX [citation needed] 542 */ 543 if (pci_mapreg_map(&isc->vga_pa, gtt_bar, PCI_MAPREG_TYPE_MEM, 544 0, 545 &isc->gtt_bst, &isc->gtt_bsh, NULL, >t_bar_size)) { 546 aprint_error_dev(self, "can't map GTT\n"); 547 error = ENXIO; 548 goto fail4; 549 } 550 if (gtt_bar_size != isc->gtt_size) { 551 aprint_error_dev(self, 552 "BAR size %"PRIxMAX 553 " mismatches detected GTT size %"PRIxMAX 554 "; trusting BAR\n", 555 (uintmax_t)gtt_bar_size, 556 (uintmax_t)isc->gtt_size); 557 isc->gtt_size = gtt_bar_size; 558 } 559 } 560 561 /* Power management. (XXX Nothing to save on suspend? Fishy...) */ 562 if (!pmf_device_register(self, NULL, agp_i810_resume)) 563 aprint_error_dev(self, "can't establish power handler\n"); 564 565 /* Match the generic AGP code's autoconf output format. */ 566 aprint_normal("%s", device_xname(self)); 567 568 /* Success! */ 569 return 0; 570 571 fail5: __unused 572 pmf_device_deregister(self); 573 if ((gtt_bar != 0) || (isc->size < gtt_off)) 574 bus_space_unmap(isc->gtt_bst, isc->gtt_bsh, isc->gtt_size); 575 isc->gtt_size = 0; 576 fail4: 577 #if notyet 578 agp_i810_fini(sc); 579 #endif 580 fail3: switch (isc->chiptype) { 581 case CHIP_I915: 582 case CHIP_I965: 583 case CHIP_G33: 584 case CHIP_G4X: 585 agp_i810_teardown_chipset_flush_page(sc); 586 break; 587 } 588 fail2: bus_space_unmap(isc->bst, isc->bsh, isc->size); 589 isc->size = 0; 590 fail1: free(isc, M_AGP); 591 sc->as_chipc = NULL; 592 fail0: agp_generic_detach(sc); 593 KASSERT(error); 594 return error; 595 } 596 597 static int 598 agp_i810_setup_chipset_flush_page(struct agp_softc *sc) 599 { 600 struct agp_i810_softc *const isc = sc->as_chipc; 601 const pci_chipset_tag_t pc = sc->as_pc; 602 const pcitag_t tag = sc->as_tag; 603 pcireg_t lo, hi; 604 bus_addr_t addr, minaddr, maxaddr; 605 int error; 606 607 /* We always use memory-mapped I/O. */ 608 isc->flush_bst = isc->vga_pa.pa_memt; 609 610 /* No page allocated yet. */ 611 isc->flush_addr = 0; 612 613 /* Read the PCI config register: 4-byte on gen3, 8-byte on gen>=4. */ 614 if (isc->chiptype == CHIP_I915) { 615 addr = pci_conf_read(pc, tag, AGP_I915_IFPADDR); 616 minaddr = PAGE_SIZE; /* XXX PCIBIOS_MIN_MEM? */ 617 maxaddr = UINT32_MAX; 618 } else { 619 hi = pci_conf_read(pc, tag, AGP_I965_IFPADDR+4); 620 lo = pci_conf_read(pc, tag, AGP_I965_IFPADDR); 621 /* 622 * Convert to uint64_t, rather than bus_addr_t which 623 * may be 32-bit, to avoid undefined behaviour with a 624 * too-wide shift. Since the BIOS doesn't know whether 625 * the OS will run 64-bit or with PAE, it ought to 626 * configure at most a 32-bit physical address, so 627 * let's print a warning in case that happens. 628 */ 629 addr = ((uint64_t)hi << 32) | lo; 630 if (hi) { 631 aprint_error_dev(sc->as_dev, 632 "BIOS configured >32-bit flush page address" 633 ": %"PRIx64"\n", ((uint64_t)hi << 32) | lo); 634 #if __i386__ && !PAE 635 return EIO; 636 #endif 637 } 638 minaddr = PAGE_SIZE; /* XXX PCIBIOS_MIN_MEM? */ 639 maxaddr = MIN(UINT64_MAX, ~(bus_addr_t)0); 640 } 641 642 /* Allocate or map a pre-allocated a page for it. */ 643 if (ISSET(addr, 1)) { 644 /* BIOS allocated it for us. Use that. */ 645 error = bus_space_map(isc->flush_bst, addr & ~1, PAGE_SIZE, 0, 646 &isc->flush_bsh); 647 if (error) 648 return error; 649 } else { 650 /* None allocated. Allocate one. */ 651 error = bus_space_alloc(isc->flush_bst, minaddr, maxaddr, 652 PAGE_SIZE, PAGE_SIZE, 0, 0, 653 &isc->flush_addr, &isc->flush_bsh); 654 if (error) 655 return error; 656 KASSERT(isc->flush_addr != 0); 657 /* Write it into the PCI config register. */ 658 addr = isc->flush_addr | 1; 659 if (isc->chiptype == CHIP_I915) { 660 pci_conf_write(pc, tag, AGP_I915_IFPADDR, addr); 661 } else { 662 hi = __SHIFTOUT(addr, __BITS(63, 32)); 663 lo = __SHIFTOUT(addr, __BITS(31, 0)); 664 pci_conf_write(pc, tag, AGP_I965_IFPADDR+4, hi); 665 pci_conf_write(pc, tag, AGP_I965_IFPADDR, lo); 666 } 667 } 668 669 /* Success! */ 670 return 0; 671 } 672 673 static void 674 agp_i810_teardown_chipset_flush_page(struct agp_softc *sc) 675 { 676 struct agp_i810_softc *const isc = sc->as_chipc; 677 678 if (isc->flush_addr) { 679 /* If we allocated a page, clear it. */ 680 if (isc->chiptype == CHIP_I915) { 681 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR, 682 0); 683 } else { 684 pci_conf_write(sc->as_pc, sc->as_tag, 685 AGP_I965_IFPADDR, 0); 686 pci_conf_write(sc->as_pc, sc->as_tag, 687 AGP_I965_IFPADDR + 4, 0); 688 } 689 isc->flush_addr = 0; 690 bus_space_free(isc->flush_bst, isc->flush_bsh, 691 PAGE_SIZE); 692 } else { 693 /* Otherwise, just unmap the pre-allocated page. */ 694 bus_space_unmap(isc->flush_bst, isc->flush_bsh, PAGE_SIZE); 695 } 696 } 697 698 /* 699 * XXX horrible hack to allow drm code to use our mapping 700 * of VGA chip registers 701 */ 702 int 703 agp_i810_borrow(bus_addr_t base, bus_size_t size, bus_space_handle_t *hdlp) 704 { 705 706 if (agp_i810_vga_regbase == 0) 707 return 0; 708 if (base < agp_i810_vga_regbase) 709 return 0; 710 if (agp_i810_vga_regsize < size) 711 return 0; 712 if ((base - agp_i810_vga_regbase) > (agp_i810_vga_regsize - size)) 713 return 0; 714 if (bus_space_subregion(agp_i810_vga_bst, agp_i810_vga_bsh, 715 (base - agp_i810_vga_regbase), (agp_i810_vga_regsize - size), 716 hdlp)) 717 return 0; 718 return 1; 719 } 720 721 static int 722 agp_i810_init(struct agp_softc *sc) 723 { 724 struct agp_i810_softc *isc; 725 int error; 726 727 isc = sc->as_chipc; 728 729 if (isc->chiptype == CHIP_I810) { 730 struct agp_gatt *gatt; 731 void *virtual; 732 int dummyseg; 733 734 /* Some i810s have on-chip memory called dcache */ 735 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 736 isc->dcache_size = 4 * 1024 * 1024; 737 else 738 isc->dcache_size = 0; 739 740 /* According to the specs the gatt on the i810 must be 64k */ 741 isc->gtt_size = 64 * 1024; 742 gatt = malloc(sizeof(*gatt), M_AGP, M_NOWAIT); 743 if (gatt == NULL) { 744 aprint_error_dev(sc->as_dev, 745 "can't malloc GATT record\n"); 746 error = ENOMEM; 747 goto fail0; 748 } 749 gatt->ag_entries = isc->gtt_size / sizeof(uint32_t); 750 error = agp_alloc_dmamem(sc->as_dmat, isc->gtt_size, 751 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical, 752 &gatt->ag_dmaseg, 1, &dummyseg); 753 if (error) { 754 aprint_error_dev(sc->as_dev, 755 "can't allocate memory for GTT: %d\n", error); 756 free(gatt, M_AGP); 757 goto fail0; 758 } 759 760 gatt->ag_virtual = (uint32_t *)virtual; 761 gatt->ag_size = gatt->ag_entries * sizeof(uint32_t); 762 memset(gatt->ag_virtual, 0, gatt->ag_size); 763 agp_flush_cache(); 764 765 /* Install the GATT. */ 766 isc->pgtblctl = gatt->ag_physical | 1; 767 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 768 isc->gatt = gatt; 769 } else if (isc->chiptype == CHIP_I830) { 770 /* The i830 automatically initializes the 128k gatt on boot. */ 771 /* XXX [citation needed] */ 772 pcireg_t reg; 773 u_int16_t gcc1; 774 775 isc->gtt_size = 128 * 1024; 776 777 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 778 gcc1 = (u_int16_t)(reg >> 16); 779 switch (gcc1 & AGP_I830_GCC1_GMS) { 780 case AGP_I830_GCC1_GMS_STOLEN_512: 781 isc->stolen = (512 - 132) * 1024 / 4096; 782 break; 783 case AGP_I830_GCC1_GMS_STOLEN_1024: 784 isc->stolen = (1024 - 132) * 1024 / 4096; 785 break; 786 case AGP_I830_GCC1_GMS_STOLEN_8192: 787 isc->stolen = (8192 - 132) * 1024 / 4096; 788 break; 789 default: 790 isc->stolen = 0; 791 aprint_error_dev(sc->as_dev, 792 "unknown memory configuration, disabling\n"); 793 error = ENXIO; 794 goto fail0; 795 } 796 797 if (isc->stolen > 0) { 798 aprint_normal_dev(sc->as_dev, 799 "detected %dk stolen memory\n", 800 isc->stolen * 4); 801 } 802 803 /* GATT address is already in there, make sure it's enabled */ 804 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 805 isc->pgtblctl |= 1; 806 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 807 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 808 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 || 809 isc->chiptype == CHIP_G4X) { 810 pcireg_t reg; 811 u_int32_t gtt_size, stolen; /* XXX kilobytes */ 812 u_int16_t gcc1; 813 814 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1); 815 gcc1 = (u_int16_t)(reg >> 16); 816 817 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 818 819 /* Stolen memory is set up at the beginning of the aperture by 820 * the BIOS, consisting of the GATT followed by 4kb for the 821 * BIOS display. 822 */ 823 switch (isc->chiptype) { 824 case CHIP_I855: 825 gtt_size = 128; 826 break; 827 case CHIP_I915: 828 gtt_size = 256; 829 break; 830 case CHIP_I965: 831 switch (isc->pgtblctl & AGP_I810_PGTBL_SIZE_MASK) { 832 case AGP_I810_PGTBL_SIZE_128KB: 833 case AGP_I810_PGTBL_SIZE_512KB: 834 gtt_size = 512; 835 break; 836 case AGP_I965_PGTBL_SIZE_1MB: 837 gtt_size = 1024; 838 break; 839 case AGP_I965_PGTBL_SIZE_2MB: 840 gtt_size = 2048; 841 break; 842 case AGP_I965_PGTBL_SIZE_1_5MB: 843 gtt_size = 1024 + 512; 844 break; 845 default: 846 aprint_error_dev(sc->as_dev, 847 "bad PGTBL size\n"); 848 error = ENXIO; 849 goto fail0; 850 } 851 break; 852 case CHIP_G33: 853 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 854 case AGP_G33_PGTBL_SIZE_1M: 855 gtt_size = 1024; 856 break; 857 case AGP_G33_PGTBL_SIZE_2M: 858 gtt_size = 2048; 859 break; 860 default: 861 aprint_error_dev(sc->as_dev, 862 "bad PGTBL size\n"); 863 error = ENXIO; 864 goto fail0; 865 } 866 break; 867 case CHIP_G4X: 868 switch (isc->pgtblctl & AGP_G4X_PGTBL_SIZE_MASK) { 869 case AGP_G4X_PGTBL_SIZE_512K: 870 gtt_size = 512; 871 break; 872 case AGP_G4X_PGTBL_SIZE_256K: 873 gtt_size = 256; 874 break; 875 case AGP_G4X_PGTBL_SIZE_128K: 876 gtt_size = 128; 877 break; 878 case AGP_G4X_PGTBL_SIZE_1M: 879 gtt_size = 1*1024; 880 break; 881 case AGP_G4X_PGTBL_SIZE_2M: 882 gtt_size = 2*1024; 883 break; 884 case AGP_G4X_PGTBL_SIZE_1_5M: 885 gtt_size = 1*1024 + 512; 886 break; 887 default: 888 aprint_error_dev(sc->as_dev, 889 "bad PGTBL size\n"); 890 error = ENXIO; 891 goto fail0; 892 } 893 break; 894 default: 895 panic("impossible chiptype %d", isc->chiptype); 896 } 897 898 /* 899 * XXX If I'm reading the datasheets right, this stolen 900 * memory detection logic is totally wrong. 901 */ 902 switch (gcc1 & AGP_I855_GCC1_GMS) { 903 case AGP_I855_GCC1_GMS_STOLEN_1M: 904 stolen = 1024; 905 break; 906 case AGP_I855_GCC1_GMS_STOLEN_4M: 907 stolen = 4 * 1024; 908 break; 909 case AGP_I855_GCC1_GMS_STOLEN_8M: 910 stolen = 8 * 1024; 911 break; 912 case AGP_I855_GCC1_GMS_STOLEN_16M: 913 stolen = 16 * 1024; 914 break; 915 case AGP_I855_GCC1_GMS_STOLEN_32M: 916 stolen = 32 * 1024; 917 break; 918 case AGP_I915_GCC1_GMS_STOLEN_48M: 919 stolen = 48 * 1024; 920 break; 921 case AGP_I915_GCC1_GMS_STOLEN_64M: 922 stolen = 64 * 1024; 923 break; 924 case AGP_G33_GCC1_GMS_STOLEN_128M: 925 stolen = 128 * 1024; 926 break; 927 case AGP_G33_GCC1_GMS_STOLEN_256M: 928 stolen = 256 * 1024; 929 break; 930 case AGP_G4X_GCC1_GMS_STOLEN_96M: 931 stolen = 96 * 1024; 932 break; 933 case AGP_G4X_GCC1_GMS_STOLEN_160M: 934 stolen = 160 * 1024; 935 break; 936 case AGP_G4X_GCC1_GMS_STOLEN_224M: 937 stolen = 224 * 1024; 938 break; 939 case AGP_G4X_GCC1_GMS_STOLEN_352M: 940 stolen = 352 * 1024; 941 break; 942 default: 943 aprint_error_dev(sc->as_dev, 944 "unknown memory configuration, disabling\n"); 945 error = ENXIO; 946 goto fail0; 947 } 948 949 switch (gcc1 & AGP_I855_GCC1_GMS) { 950 case AGP_I915_GCC1_GMS_STOLEN_48M: 951 case AGP_I915_GCC1_GMS_STOLEN_64M: 952 if (isc->chiptype != CHIP_I915 && 953 isc->chiptype != CHIP_I965 && 954 isc->chiptype != CHIP_G33 && 955 isc->chiptype != CHIP_G4X) 956 stolen = 0; 957 break; 958 case AGP_G33_GCC1_GMS_STOLEN_128M: 959 case AGP_G33_GCC1_GMS_STOLEN_256M: 960 if (isc->chiptype != CHIP_I965 && 961 isc->chiptype != CHIP_G33 && 962 isc->chiptype != CHIP_G4X) 963 stolen = 0; 964 break; 965 case AGP_G4X_GCC1_GMS_STOLEN_96M: 966 case AGP_G4X_GCC1_GMS_STOLEN_160M: 967 case AGP_G4X_GCC1_GMS_STOLEN_224M: 968 case AGP_G4X_GCC1_GMS_STOLEN_352M: 969 if (isc->chiptype != CHIP_I965 && 970 isc->chiptype != CHIP_G4X) 971 stolen = 0; 972 break; 973 } 974 975 isc->gtt_size = gtt_size * 1024; 976 977 /* BIOS space */ 978 /* XXX [citation needed] */ 979 gtt_size += 4; 980 981 /* XXX [citation needed] for this subtraction */ 982 isc->stolen = (stolen - gtt_size) * 1024 / 4096; 983 984 if (isc->stolen > 0) { 985 aprint_normal_dev(sc->as_dev, 986 "detected %dk stolen memory\n", 987 isc->stolen * 4); 988 } 989 990 /* GATT address is already in there, make sure it's enabled */ 991 isc->pgtblctl |= 1; 992 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 993 } 994 995 /* 996 * Make sure the chipset can see everything. 997 */ 998 agp_flush_cache(); 999 1000 /* 1001 * Publish what we found for kludgey drivers (I'm looking at 1002 * you, drm). 1003 */ 1004 if (agp_i810_sc == NULL) 1005 agp_i810_sc = sc; 1006 else 1007 aprint_error_dev(sc->as_dev, "agp already attached\n"); 1008 1009 /* Success! */ 1010 return 0; 1011 1012 fail0: KASSERT(error); 1013 return error; 1014 } 1015 1016 #if 0 1017 static int 1018 agp_i810_detach(struct agp_softc *sc) 1019 { 1020 int error; 1021 struct agp_i810_softc *isc = sc->as_chipc; 1022 1023 error = agp_generic_detach(sc); 1024 if (error) 1025 return error; 1026 1027 switch (isc->chiptype) { 1028 case CHIP_I915: 1029 case CHIP_I965: 1030 case CHIP_G33: 1031 case CHIP_G4X: 1032 agp_i810_teardown_chipset_flush_page(sc); 1033 break; 1034 } 1035 1036 /* Clear the GATT base. */ 1037 if (sc->chiptype == CHIP_I810) { 1038 WRITE4(AGP_I810_PGTBL_CTL, 0); 1039 } else { 1040 unsigned int pgtblctl; 1041 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 1042 pgtblctl &= ~1; 1043 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 1044 } 1045 1046 if (sc->chiptype == CHIP_I810) { 1047 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap, 1048 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 1049 free(isc->gatt, M_AGP); 1050 } 1051 1052 return 0; 1053 } 1054 #endif 1055 1056 static u_int32_t 1057 agp_i810_get_aperture(struct agp_softc *sc) 1058 { 1059 struct agp_i810_softc *isc = sc->as_chipc; 1060 pcireg_t reg; 1061 u_int32_t size; 1062 u_int16_t miscc, gcc1; 1063 1064 size = 0; 1065 1066 switch (isc->chiptype) { 1067 case CHIP_I810: 1068 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 1069 miscc = (u_int16_t)(reg >> 16); 1070 if ((miscc & AGP_I810_MISCC_WINSIZE) == 1071 AGP_I810_MISCC_WINSIZE_32) 1072 size = 32 * 1024 * 1024; 1073 else 1074 size = 64 * 1024 * 1024; 1075 break; 1076 case CHIP_I830: 1077 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 1078 gcc1 = (u_int16_t)(reg >> 16); 1079 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 1080 size = 64 * 1024 * 1024; 1081 else 1082 size = 128 * 1024 * 1024; 1083 break; 1084 case CHIP_I855: 1085 size = 128 * 1024 * 1024; 1086 break; 1087 case CHIP_I915: 1088 case CHIP_G33: 1089 case CHIP_G4X: 1090 size = sc->as_apsize; 1091 break; 1092 case CHIP_I965: 1093 size = 512 * 1024 * 1024; 1094 break; 1095 default: 1096 aprint_error(": Unknown chipset\n"); 1097 } 1098 1099 return size; 1100 } 1101 1102 static int 1103 agp_i810_set_aperture(struct agp_softc *sc __unused, 1104 uint32_t aperture __unused) 1105 { 1106 1107 return ENOSYS; 1108 } 1109 1110 static int 1111 agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 1112 { 1113 struct agp_i810_softc *isc = sc->as_chipc; 1114 1115 if (offset < 0 || offset >= ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) { 1116 DPRINTF(sc, "failed" 1117 ": offset 0x%"PRIxMAX", shift %u, entries %"PRIuMAX"\n", 1118 (uintmax_t)offset, 1119 (unsigned)AGP_PAGE_SHIFT, 1120 (uintmax_t)isc->gtt_size/4); 1121 return EINVAL; 1122 } 1123 1124 if (isc->chiptype != CHIP_I810) { 1125 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1126 DPRINTF(sc, "trying to bind into stolen memory\n"); 1127 return EINVAL; 1128 } 1129 } 1130 1131 return agp_i810_write_gtt_entry(isc, offset, physical | 1); 1132 } 1133 1134 static int 1135 agp_i810_unbind_page(struct agp_softc *sc, off_t offset) 1136 { 1137 struct agp_i810_softc *isc = sc->as_chipc; 1138 1139 if (offset < 0 || offset >= ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) 1140 return EINVAL; 1141 1142 if (isc->chiptype != CHIP_I810 ) { 1143 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1144 DPRINTF(sc, "trying to unbind from stolen memory\n"); 1145 return EINVAL; 1146 } 1147 } 1148 1149 return agp_i810_write_gtt_entry(isc, offset, 0); 1150 } 1151 1152 /* 1153 * Writing via memory mapped registers already flushes all TLBs. 1154 */ 1155 static void 1156 agp_i810_flush_tlb(struct agp_softc *sc) 1157 { 1158 } 1159 1160 static int 1161 agp_i810_enable(struct agp_softc *sc, u_int32_t mode) 1162 { 1163 1164 return 0; 1165 } 1166 1167 #define AGP_I810_MEMTYPE_MAIN 0 1168 #define AGP_I810_MEMTYPE_DCACHE 1 1169 #define AGP_I810_MEMTYPE_HWCURSOR 2 1170 1171 static struct agp_memory * 1172 agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size) 1173 { 1174 struct agp_i810_softc *isc = sc->as_chipc; 1175 struct agp_memory *mem; 1176 int error; 1177 1178 DPRINTF(sc, "AGP: alloc(%d, 0x%"PRIxMAX")\n", type, (uintmax_t)size); 1179 1180 if (size <= 0) 1181 return NULL; 1182 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 1183 return NULL; 1184 KASSERT(sc->as_allocated <= sc->as_maxmem); 1185 if (size > (sc->as_maxmem - sc->as_allocated)) 1186 return NULL; 1187 if (size > ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) 1188 return NULL; 1189 1190 switch (type) { 1191 case AGP_I810_MEMTYPE_MAIN: 1192 break; 1193 case AGP_I810_MEMTYPE_DCACHE: 1194 if (isc->chiptype != CHIP_I810) 1195 return NULL; 1196 if (size != isc->dcache_size) 1197 return NULL; 1198 break; 1199 case AGP_I810_MEMTYPE_HWCURSOR: 1200 if ((size != AGP_PAGE_SIZE) && 1201 (size != AGP_PAGE_SIZE*4)) 1202 return NULL; 1203 break; 1204 default: 1205 return NULL; 1206 } 1207 1208 mem = malloc(sizeof(*mem), M_AGP, M_WAITOK|M_ZERO); 1209 if (mem == NULL) 1210 goto fail0; 1211 mem->am_id = sc->as_nextid++; 1212 mem->am_size = size; 1213 mem->am_type = type; 1214 1215 switch (type) { 1216 case AGP_I810_MEMTYPE_MAIN: 1217 error = bus_dmamap_create(sc->as_dmat, size, 1218 (size >> AGP_PAGE_SHIFT) + 1, size, 0, BUS_DMA_WAITOK, 1219 &mem->am_dmamap); 1220 if (error) 1221 goto fail1; 1222 break; 1223 case AGP_I810_MEMTYPE_DCACHE: 1224 break; 1225 case AGP_I810_MEMTYPE_HWCURSOR: 1226 mem->am_dmaseg = malloc(sizeof(*mem->am_dmaseg), M_AGP, 1227 M_WAITOK); 1228 error = agp_alloc_dmamem(sc->as_dmat, size, 0, &mem->am_dmamap, 1229 &mem->am_virtual, &mem->am_physical, mem->am_dmaseg, 1, 1230 &mem->am_nseg); 1231 if (error) { 1232 free(mem->am_dmaseg, M_AGP); 1233 goto fail1; 1234 } 1235 (void)memset(mem->am_virtual, 0, size); 1236 break; 1237 default: 1238 panic("invalid agp memory type: %d", type); 1239 } 1240 1241 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link); 1242 sc->as_allocated += size; 1243 1244 return mem; 1245 1246 fail1: free(mem, M_AGP); 1247 fail0: return NULL; 1248 } 1249 1250 static int 1251 agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem) 1252 { 1253 1254 if (mem->am_is_bound) 1255 return EBUSY; 1256 1257 switch (mem->am_type) { 1258 case AGP_I810_MEMTYPE_MAIN: 1259 bus_dmamap_destroy(sc->as_dmat, mem->am_dmamap); 1260 break; 1261 case AGP_I810_MEMTYPE_DCACHE: 1262 break; 1263 case AGP_I810_MEMTYPE_HWCURSOR: 1264 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap, 1265 mem->am_virtual, mem->am_dmaseg, mem->am_nseg); 1266 free(mem->am_dmaseg, M_AGP); 1267 break; 1268 default: 1269 panic("invalid agp i810 memory type: %d", mem->am_type); 1270 } 1271 1272 sc->as_allocated -= mem->am_size; 1273 TAILQ_REMOVE(&sc->as_memory, mem, am_link); 1274 free(mem, M_AGP); 1275 1276 return 0; 1277 } 1278 1279 static int 1280 agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem, 1281 off_t offset) 1282 { 1283 struct agp_i810_softc *isc = sc->as_chipc; 1284 uint32_t pgtblctl; 1285 int error; 1286 1287 if (mem->am_is_bound) 1288 return EINVAL; 1289 1290 /* 1291 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 1292 * X server for mysterious reasons which leads to crashes if we write 1293 * to the GTT through the MMIO window. 1294 * Until the issue is solved, simply restore it. 1295 */ 1296 pgtblctl = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL); 1297 if (pgtblctl != isc->pgtblctl) { 1298 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%"PRIx32 1299 " - fixing\n", pgtblctl); 1300 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 1301 isc->pgtblctl); 1302 } 1303 1304 switch (mem->am_type) { 1305 case AGP_I810_MEMTYPE_MAIN: 1306 return agp_generic_bind_memory_bounded(sc, mem, offset, 1307 0, (isc->gtt_size/4) << AGP_PAGE_SHIFT); 1308 case AGP_I810_MEMTYPE_DCACHE: 1309 error = agp_i810_bind_memory_dcache(sc, mem, offset); 1310 break; 1311 case AGP_I810_MEMTYPE_HWCURSOR: 1312 error = agp_i810_bind_memory_hwcursor(sc, mem, offset); 1313 break; 1314 default: 1315 panic("invalid agp i810 memory type: %d", mem->am_type); 1316 } 1317 if (error) 1318 return error; 1319 1320 /* Success! */ 1321 mem->am_is_bound = 1; 1322 return 0; 1323 } 1324 1325 #define I810_GTT_PTE_VALID 0x01 1326 #define I810_GTT_PTE_DCACHE 0x02 1327 1328 static int 1329 agp_i810_bind_memory_dcache(struct agp_softc *sc, struct agp_memory *mem, 1330 off_t offset) 1331 { 1332 struct agp_i810_softc *const isc __diagused = sc->as_chipc; 1333 uint32_t i, j; 1334 int error; 1335 1336 KASSERT(isc->chiptype == CHIP_I810); 1337 1338 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0); 1339 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 1340 error = agp_i810_write_gtt_entry(isc, offset + i, 1341 i | I810_GTT_PTE_VALID | I810_GTT_PTE_DCACHE); 1342 if (error) 1343 goto fail0; 1344 } 1345 1346 /* Success! */ 1347 mem->am_offset = offset; 1348 return 0; 1349 1350 fail0: for (j = 0; j < i; j += AGP_PAGE_SIZE) 1351 (void)agp_i810_unbind_page(sc, offset + j); 1352 return error; 1353 } 1354 1355 static int 1356 agp_i810_bind_memory_hwcursor(struct agp_softc *sc, struct agp_memory *mem, 1357 off_t offset) 1358 { 1359 const bus_addr_t pa = mem->am_physical; 1360 uint32_t i, j; 1361 int error; 1362 1363 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0); 1364 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 1365 error = agp_i810_bind_page(sc, offset + i, pa + i); 1366 if (error) 1367 goto fail0; 1368 } 1369 1370 /* Success! */ 1371 mem->am_offset = offset; 1372 return 0; 1373 1374 fail0: for (j = 0; j < i; j += AGP_PAGE_SIZE) 1375 (void)agp_i810_unbind_page(sc, offset + j); 1376 return error; 1377 } 1378 1379 static int 1380 agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem) 1381 { 1382 struct agp_i810_softc *isc __diagused = sc->as_chipc; 1383 u_int32_t i; 1384 1385 if (!mem->am_is_bound) 1386 return EINVAL; 1387 1388 switch (mem->am_type) { 1389 case AGP_I810_MEMTYPE_MAIN: 1390 return agp_generic_unbind_memory(sc, mem); 1391 case AGP_I810_MEMTYPE_DCACHE: 1392 KASSERT(isc->chiptype == CHIP_I810); 1393 /* FALLTHROUGH */ 1394 case AGP_I810_MEMTYPE_HWCURSOR: 1395 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1396 (void)agp_i810_unbind_page(sc, mem->am_offset + i); 1397 mem->am_offset = 0; 1398 break; 1399 default: 1400 panic("invalid agp i810 memory type: %d", mem->am_type); 1401 } 1402 1403 mem->am_is_bound = 0; 1404 return 0; 1405 } 1406 1407 static bool 1408 agp_i810_resume(device_t dv, const pmf_qual_t *qual) 1409 { 1410 struct agp_softc *sc = device_private(dv); 1411 struct agp_i810_softc *isc = sc->as_chipc; 1412 1413 /* 1414 * XXX Nothing uses this! Save on suspend, restore on resume? 1415 */ 1416 isc->pgtblctl_resume_hack = READ4(AGP_I810_PGTBL_CTL); 1417 agp_flush_cache(); 1418 1419 return true; 1420 } 1421
Indexes created Wed Sep 24 02:09:48 GMT 2025