agp_i810.c revision 1.121
1 /* $NetBSD: agp_i810.c,v 1.121 2015/10/21 15:37:35 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.121 2015/10/21 15:37:35 christos Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/atomic.h> 38 #include <sys/malloc.h> 39 #include <sys/kernel.h> 40 #include <sys/proc.h> 41 #include <sys/device.h> 42 #include <sys/conf.h> 43 #include <sys/xcall.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/agpvar.h> 49 #include <dev/pci/agpreg.h> 50 #include <dev/pci/agp_i810var.h> 51 52 #include <sys/agpio.h> 53 54 #include <sys/bus.h> 55 56 #include "agp_intel.h" 57 58 #ifdef AGP_DEBUG 59 #define DPRINTF(sc, fmt, ...) \ 60 device_printf((sc)->as_dev, "%s: " fmt, __func__, ##__VA_ARGS__) 61 #else 62 #define DPRINTF(sc, fmt, ...) do {} while (0) 63 #endif 64 65 struct agp_softc *agp_i810_sc = NULL; 66 67 #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off) 68 #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off) 69 #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v) 70 71 #define CHIP_I810 0 /* i810/i815 */ 72 #define CHIP_I830 1 /* 830M/845G */ 73 #define CHIP_I855 2 /* 852GM/855GM/865G */ 74 #define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */ 75 #define CHIP_I965 4 /* 965Q/965PM */ 76 #define CHIP_G33 5 /* G33/Q33/Q35 */ 77 #define CHIP_G4X 6 /* G45/Q45 */ 78 79 /* XXX hack, see below */ 80 static bus_addr_t agp_i810_vga_regbase; 81 static bus_size_t agp_i810_vga_regsize; 82 static bus_space_tag_t agp_i810_vga_bst; 83 static bus_space_handle_t agp_i810_vga_bsh; 84 85 static u_int32_t agp_i810_get_aperture(struct agp_softc *); 86 static int agp_i810_set_aperture(struct agp_softc *, u_int32_t); 87 static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t); 88 static int agp_i810_unbind_page(struct agp_softc *, off_t); 89 static void agp_i810_flush_tlb(struct agp_softc *); 90 static int agp_i810_enable(struct agp_softc *, u_int32_t mode); 91 static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int, 92 vsize_t); 93 static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *); 94 static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, 95 off_t); 96 static int agp_i810_bind_memory_dcache(struct agp_softc *, struct agp_memory *, 97 off_t); 98 static int agp_i810_bind_memory_hwcursor(struct agp_softc *, 99 struct agp_memory *, off_t); 100 static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *); 101 102 static bool agp_i810_resume(device_t, const pmf_qual_t *); 103 static int agp_i810_init(struct agp_softc *); 104 105 static int agp_i810_setup_chipset_flush_page(struct agp_softc *); 106 static void agp_i810_teardown_chipset_flush_page(struct agp_softc *); 107 static int agp_i810_init(struct agp_softc *); 108 109 static struct agp_methods agp_i810_methods = { 110 agp_i810_get_aperture, 111 agp_i810_set_aperture, 112 agp_i810_bind_page, 113 agp_i810_unbind_page, 114 agp_i810_flush_tlb, 115 agp_i810_enable, 116 agp_i810_alloc_memory, 117 agp_i810_free_memory, 118 agp_i810_bind_memory, 119 agp_i810_unbind_memory, 120 }; 121 122 int 123 agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, 124 bus_addr_t addr, int flags) 125 { 126 u_int32_t pte; 127 128 /* 129 * Bits 11:4 (physical start address extension) should be zero. 130 * Flag bits 3:0 should be zero too. 131 * 132 * XXX This should be a kassert -- no reason for this routine 133 * to allow failure. 134 */ 135 if ((addr & 0xfff) != 0) 136 return EINVAL; 137 KASSERT(flags == (flags & 0x7)); 138 139 pte = (u_int32_t)addr; 140 /* 141 * We need to massage the pte if bus_addr_t is wider than 32 bits. 142 * The compiler isn't smart enough, hence the casts to uintmax_t. 143 */ 144 if (sizeof(bus_addr_t) > sizeof(u_int32_t)) { 145 /* 965+ can do 36-bit addressing, add in the extra bits. */ 146 if (isc->chiptype == CHIP_I965 || 147 isc->chiptype == CHIP_G33 || 148 isc->chiptype == CHIP_G4X) { 149 if (((uintmax_t)addr >> 36) != 0) 150 return EINVAL; 151 pte |= (addr >> 28) & 0xf0; 152 } else { 153 if (((uintmax_t)addr >> 32) != 0) 154 return EINVAL; 155 } 156 } 157 158 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, 159 4*(off >> AGP_PAGE_SHIFT), pte | flags); 160 161 return 0; 162 } 163 164 void 165 agp_i810_post_gtt_entry(struct agp_i810_softc *isc, off_t off) 166 { 167 168 /* 169 * See <https://bugs.freedesktop.org/show_bug.cgi?id=88191>. 170 * Out of paranoia, let's do the write barrier and posting 171 * read, because I don't have enough time or hardware to 172 * conduct conclusive tests. 173 */ 174 membar_producer(); 175 (void)bus_space_read_4(isc->gtt_bst, isc->gtt_bsh, 176 4*(off >> AGP_PAGE_SHIFT)); 177 } 178 179 static void 180 agp_flush_cache_xc(void *a __unused, void *b __unused) 181 { 182 183 agp_flush_cache(); 184 } 185 186 void 187 agp_i810_chipset_flush(struct agp_i810_softc *isc) 188 { 189 unsigned int timo = 20000; /* * 50 us = 1 s */ 190 191 switch (isc->chiptype) { 192 case CHIP_I810: 193 break; 194 case CHIP_I830: 195 case CHIP_I855: 196 /* 197 * Flush all CPU caches. If we're cold, we can't run 198 * xcalls, but there should be only one CPU up, so 199 * flushing only the local CPU's cache should suffice. 200 * 201 * XXX Come to think of it, do these chipsets appear in 202 * any multi-CPU systems? 203 */ 204 if (cold) 205 agp_flush_cache(); 206 else 207 xc_wait(xc_broadcast(0, &agp_flush_cache_xc, 208 NULL, NULL)); 209 WRITE4(AGP_I830_HIC, READ4(AGP_I830_HIC) | __BIT(31)); 210 while (ISSET(READ4(AGP_I830_HIC), __BIT(31))) { 211 if (timo-- == 0) 212 break; 213 DELAY(50); 214 } 215 break; 216 case CHIP_I915: 217 case CHIP_I965: 218 case CHIP_G33: 219 case CHIP_G4X: 220 bus_space_write_4(isc->flush_bst, isc->flush_bsh, 0, 1); 221 break; 222 } 223 } 224 225 /* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */ 226 static int 227 agp_i810_vgamatch(const struct pci_attach_args *pa) 228 { 229 230 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 231 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 232 return (0); 233 234 switch (PCI_PRODUCT(pa->pa_id)) { 235 case PCI_PRODUCT_INTEL_82810_GC: 236 case PCI_PRODUCT_INTEL_82810_DC100_GC: 237 case PCI_PRODUCT_INTEL_82810E_GC: 238 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 239 case PCI_PRODUCT_INTEL_82830MP_IV: 240 case PCI_PRODUCT_INTEL_82845G_IGD: 241 case PCI_PRODUCT_INTEL_82855GM_IGD: 242 case PCI_PRODUCT_INTEL_82865_IGD: 243 case PCI_PRODUCT_INTEL_82915G_IGD: 244 case PCI_PRODUCT_INTEL_82915GM_IGD: 245 case PCI_PRODUCT_INTEL_82945P_IGD: 246 case PCI_PRODUCT_INTEL_82945GM_IGD: 247 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 248 case PCI_PRODUCT_INTEL_82945GME_IGD: 249 case PCI_PRODUCT_INTEL_E7221_IGD: 250 case PCI_PRODUCT_INTEL_82965Q_IGD: 251 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 252 case PCI_PRODUCT_INTEL_82965PM_IGD: 253 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 254 case PCI_PRODUCT_INTEL_82G33_IGD: 255 case PCI_PRODUCT_INTEL_82G33_IGD_1: 256 case PCI_PRODUCT_INTEL_82965G_IGD: 257 case PCI_PRODUCT_INTEL_82965G_IGD_1: 258 case PCI_PRODUCT_INTEL_82965GME_IGD: 259 case PCI_PRODUCT_INTEL_82Q35_IGD: 260 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 261 case PCI_PRODUCT_INTEL_82Q33_IGD: 262 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 263 case PCI_PRODUCT_INTEL_82G35_IGD: 264 case PCI_PRODUCT_INTEL_82G35_IGD_1: 265 case PCI_PRODUCT_INTEL_82946GZ_IGD: 266 case PCI_PRODUCT_INTEL_82GM45_IGD: 267 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 268 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 269 case PCI_PRODUCT_INTEL_82Q45_IGD: 270 case PCI_PRODUCT_INTEL_82G45_IGD: 271 case PCI_PRODUCT_INTEL_82G41_IGD: 272 case PCI_PRODUCT_INTEL_82B43_IGD: 273 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 274 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 275 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 276 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 277 return (1); 278 } 279 280 return (0); 281 } 282 283 static int 284 agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg) 285 { 286 /* 287 * Find the aperture. Don't map it (yet), this would 288 * eat KVA. 289 */ 290 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 291 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize, 292 &sc->as_apflags) != 0) 293 return ENXIO; 294 295 sc->as_apt = pa->pa_memt; 296 297 return 0; 298 } 299 300 int 301 agp_i810_attach(device_t parent, device_t self, void *aux) 302 { 303 struct agp_softc *sc = device_private(self); 304 struct agp_i810_softc *isc; 305 int apbase, mmadr_bar, gtt_bar; 306 int mmadr_type, mmadr_flags; 307 bus_addr_t mmadr; 308 bus_size_t mmadr_size, gtt_off; 309 int error; 310 311 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 312 if (isc == NULL) { 313 aprint_error(": can't allocate chipset-specific softc\n"); 314 error = ENOMEM; 315 goto fail0; 316 } 317 sc->as_chipc = isc; 318 sc->as_methods = &agp_i810_methods; 319 320 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) { 321 #if NAGP_INTEL > 0 322 const struct pci_attach_args *pa = aux; 323 324 switch (PCI_PRODUCT(pa->pa_id)) { 325 case PCI_PRODUCT_INTEL_82840_HB: 326 case PCI_PRODUCT_INTEL_82865_HB: 327 case PCI_PRODUCT_INTEL_82845G_DRAM: 328 case PCI_PRODUCT_INTEL_82815_FULL_HUB: 329 case PCI_PRODUCT_INTEL_82855GM_MCH: 330 free(isc, M_AGP); 331 return agp_intel_attach(parent, self, aux); 332 } 333 #endif 334 aprint_error(": can't find internal VGA" 335 " config space\n"); 336 error = ENOENT; 337 goto fail1; 338 } 339 340 /* XXXfvdl */ 341 sc->as_dmat = isc->vga_pa.pa_dmat; 342 343 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 344 case PCI_PRODUCT_INTEL_82810_GC: 345 case PCI_PRODUCT_INTEL_82810_DC100_GC: 346 case PCI_PRODUCT_INTEL_82810E_GC: 347 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 348 isc->chiptype = CHIP_I810; 349 aprint_normal(": i810-family chipset\n"); 350 break; 351 case PCI_PRODUCT_INTEL_82830MP_IV: 352 case PCI_PRODUCT_INTEL_82845G_IGD: 353 isc->chiptype = CHIP_I830; 354 aprint_normal(": i830-family chipset\n"); 355 break; 356 case PCI_PRODUCT_INTEL_82855GM_IGD: 357 case PCI_PRODUCT_INTEL_82865_IGD: 358 isc->chiptype = CHIP_I855; 359 aprint_normal(": i855-family chipset\n"); 360 break; 361 case PCI_PRODUCT_INTEL_82915G_IGD: 362 case PCI_PRODUCT_INTEL_82915GM_IGD: 363 case PCI_PRODUCT_INTEL_82945P_IGD: 364 case PCI_PRODUCT_INTEL_82945GM_IGD: 365 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 366 case PCI_PRODUCT_INTEL_82945GME_IGD: 367 case PCI_PRODUCT_INTEL_E7221_IGD: 368 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 369 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 370 isc->chiptype = CHIP_I915; 371 aprint_normal(": i915-family chipset\n"); 372 break; 373 case PCI_PRODUCT_INTEL_82965Q_IGD: 374 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 375 case PCI_PRODUCT_INTEL_82965PM_IGD: 376 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 377 case PCI_PRODUCT_INTEL_82965G_IGD: 378 case PCI_PRODUCT_INTEL_82965G_IGD_1: 379 case PCI_PRODUCT_INTEL_82965GME_IGD: 380 case PCI_PRODUCT_INTEL_82946GZ_IGD: 381 case PCI_PRODUCT_INTEL_82G35_IGD: 382 case PCI_PRODUCT_INTEL_82G35_IGD_1: 383 isc->chiptype = CHIP_I965; 384 aprint_normal(": i965-family chipset\n"); 385 break; 386 case PCI_PRODUCT_INTEL_82Q35_IGD: 387 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 388 case PCI_PRODUCT_INTEL_82G33_IGD: 389 case PCI_PRODUCT_INTEL_82G33_IGD_1: 390 case PCI_PRODUCT_INTEL_82Q33_IGD: 391 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 392 isc->chiptype = CHIP_G33; 393 aprint_normal(": G33-family chipset\n"); 394 break; 395 case PCI_PRODUCT_INTEL_82GM45_IGD: 396 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 397 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 398 case PCI_PRODUCT_INTEL_82Q45_IGD: 399 case PCI_PRODUCT_INTEL_82G45_IGD: 400 case PCI_PRODUCT_INTEL_82G41_IGD: 401 case PCI_PRODUCT_INTEL_82B43_IGD: 402 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 403 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 404 isc->chiptype = CHIP_G4X; 405 aprint_normal(": G4X-family chipset\n"); 406 break; 407 } 408 aprint_naive("\n"); 409 410 /* Discriminate on the chipset to choose the relevant BARs. */ 411 switch (isc->chiptype) { 412 case CHIP_I915: 413 case CHIP_G33: 414 apbase = AGP_I915_GMADR; 415 mmadr_bar = AGP_I915_MMADR; 416 gtt_bar = AGP_I915_GTTADR; 417 gtt_off = ~(bus_size_t)0; /* XXXGCC */ 418 break; 419 case CHIP_I965: 420 apbase = AGP_I965_GMADR; 421 mmadr_bar = AGP_I965_MMADR; 422 gtt_bar = 0; 423 gtt_off = AGP_I965_GTT; 424 break; 425 case CHIP_G4X: 426 apbase = AGP_I965_GMADR; 427 mmadr_bar = AGP_I965_MMADR; 428 gtt_bar = 0; 429 gtt_off = AGP_G4X_GTT; 430 break; 431 default: 432 apbase = AGP_I810_GMADR; 433 mmadr_bar = AGP_I810_MMADR; 434 gtt_bar = 0; 435 gtt_off = AGP_I810_GTT; 436 break; 437 } 438 439 /* 440 * Ensure the MMIO BAR is, in fact, a memory BAR. 441 * 442 * XXX This is required because we use pa_memt below. It is 443 * not a priori clear to me there is any other reason to 444 * require this. 445 */ 446 mmadr_type = pci_mapreg_type(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, 447 mmadr_bar); 448 if (PCI_MAPREG_TYPE(mmadr_type) != PCI_MAPREG_TYPE_MEM) { 449 aprint_error_dev(self, "non-memory device MMIO registers\n"); 450 error = ENXIO; 451 goto fail1; 452 } 453 454 /* 455 * Determine the size of the MMIO registers. 456 * 457 * XXX The size of the MMIO registers we use is statically 458 * determined, as a function of the chipset, by the driver's 459 * implementation. 460 * 461 * On some chipsets, the GTT is part of the MMIO register BAR. 462 * We would like to map the GTT separately, so that we can map 463 * it prefetchable, which we can't do with the MMIO registers. 464 * Consequently, we would especially like to map a fixed size 465 * of MMIO registers, not just whatever size the BAR says. 466 * 467 * However, old drm assumes that the combined GTT/MMIO register 468 * space is a single bus space mapping, so mapping them 469 * separately breaks that. Once we rip out old drm, we can 470 * replace the pci_mapreg_info call by the chipset switch. 471 */ 472 #if notyet 473 switch (isc->chiptype) { 474 case CHIP_I810: 475 case CHIP_I830: 476 case CHIP_I855: 477 case CHIP_I915: 478 case CHIP_G33: 479 case CHIP_I965: 480 case CHIP_G4X: 481 isc->size = 512*1024; 482 break; 483 case CHIP_SANDYBRIDGE: 484 case CHIP_IVYBRIDGE: 485 case CHIP_HASWELL: 486 isc->size = 2*1024*1024; 487 break; 488 } 489 #else 490 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, 491 mmadr_bar, mmadr_type, NULL, &isc->size, NULL)) 492 isc->size = 512*1024; 493 #endif /* notyet */ 494 495 /* Map (or, rather, find the address and size of) the aperture. */ 496 if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) 497 error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase); 498 else 499 error = agp_map_aperture(&isc->vga_pa, sc, apbase); 500 if (error) { 501 aprint_error_dev(self, "can't map aperture: %d\n", error); 502 goto fail1; 503 } 504 505 /* Map the memory-mapped I/O registers, or the non-GTT part. */ 506 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, mmadr_bar, 507 mmadr_type, &mmadr, &mmadr_size, &mmadr_flags)) { 508 aprint_error_dev(self, "can't find MMIO registers\n"); 509 error = ENXIO; 510 goto fail1; 511 } 512 if (mmadr_size < isc->size) { 513 aprint_error_dev(self, "MMIO registers too small" 514 ": %"PRIuMAX" < %"PRIuMAX"\n", 515 (uintmax_t)mmadr_size, (uintmax_t)isc->size); 516 error = ENXIO; 517 goto fail1; 518 } 519 isc->bst = isc->vga_pa.pa_memt; 520 error = bus_space_map(isc->bst, mmadr, isc->size, mmadr_flags, 521 &isc->bsh); 522 if (error) { 523 aprint_error_dev(self, "can't map MMIO registers: %d\n", 524 error); 525 error = ENXIO; 526 goto fail1; 527 } 528 529 /* Set up a chipset flush page if necessary. */ 530 switch (isc->chiptype) { 531 case CHIP_I915: 532 case CHIP_I965: 533 case CHIP_G33: 534 case CHIP_G4X: 535 error = agp_i810_setup_chipset_flush_page(sc); 536 if (error) { 537 aprint_error_dev(self, 538 "can't set up chipset flush page: %d\n", error); 539 goto fail2; 540 } 541 break; 542 } 543 544 /* 545 * XXX horrible hack to allow drm code to use our mapping 546 * of VGA chip registers 547 */ 548 agp_i810_vga_regbase = mmadr; 549 agp_i810_vga_regsize = isc->size; 550 agp_i810_vga_bst = isc->bst; 551 agp_i810_vga_bsh = isc->bsh; 552 553 /* Initialize the chipset. */ 554 error = agp_i810_init(sc); 555 if (error) 556 goto fail3; 557 558 /* Map the GTT, from either part of the MMIO region or its own BAR. */ 559 if (gtt_bar == 0) { 560 isc->gtt_bst = isc->bst; 561 if ((mmadr_size - gtt_off) < isc->gtt_size) { 562 aprint_error_dev(self, "GTTMMADR too small for GTT" 563 ": (%"PRIxMAX" - %"PRIxMAX") < %"PRIxMAX"\n", 564 (uintmax_t)mmadr_size, 565 (uintmax_t)gtt_off, 566 (uintmax_t)isc->gtt_size); 567 error = ENXIO; 568 goto fail4; 569 } 570 /* 571 * Map the GTT separately if we can, so that we can map 572 * it prefetchable, but in early models, there are MMIO 573 * registers before and after the GTT, so we can only 574 * take a subregion. 575 */ 576 if (isc->size < gtt_off) 577 error = bus_space_map(isc->gtt_bst, (mmadr + gtt_off), 578 isc->gtt_size, mmadr_flags, &isc->gtt_bsh); 579 else 580 error = bus_space_subregion(isc->bst, isc->bsh, 581 gtt_off, isc->gtt_size, &isc->gtt_bsh); 582 if (error) { 583 aprint_error_dev(self, "can't map GTT: %d\n", error); 584 error = ENXIO; 585 goto fail4; 586 } 587 } else { 588 bus_size_t gtt_bar_size; 589 /* 590 * All chipsets with a separate BAR for the GTT, namely 591 * the i915 and G33 families, have 32-bit GTT BARs. 592 * 593 * XXX [citation needed] 594 */ 595 if (pci_mapreg_map(&isc->vga_pa, gtt_bar, PCI_MAPREG_TYPE_MEM, 596 0, 597 &isc->gtt_bst, &isc->gtt_bsh, NULL, >t_bar_size)) { 598 aprint_error_dev(self, "can't map GTT\n"); 599 error = ENXIO; 600 goto fail4; 601 } 602 if (gtt_bar_size != isc->gtt_size) { 603 aprint_error_dev(self, 604 "BAR size %"PRIxMAX 605 " mismatches detected GTT size %"PRIxMAX 606 "; trusting BAR\n", 607 (uintmax_t)gtt_bar_size, 608 (uintmax_t)isc->gtt_size); 609 isc->gtt_size = gtt_bar_size; 610 } 611 } 612 613 /* Power management. (XXX Nothing to save on suspend? Fishy...) */ 614 if (!pmf_device_register(self, NULL, agp_i810_resume)) 615 aprint_error_dev(self, "can't establish power handler\n"); 616 617 /* Match the generic AGP code's autoconf output format. */ 618 aprint_normal("%s", device_xname(self)); 619 620 /* Success! */ 621 return 0; 622 623 fail5: __unused 624 pmf_device_deregister(self); 625 if ((gtt_bar != 0) || (isc->size < gtt_off)) 626 bus_space_unmap(isc->gtt_bst, isc->gtt_bsh, isc->gtt_size); 627 isc->gtt_size = 0; 628 fail4: 629 #if notyet 630 agp_i810_fini(sc); 631 #endif 632 fail3: switch (isc->chiptype) { 633 case CHIP_I915: 634 case CHIP_I965: 635 case CHIP_G33: 636 case CHIP_G4X: 637 agp_i810_teardown_chipset_flush_page(sc); 638 break; 639 } 640 fail2: bus_space_unmap(isc->bst, isc->bsh, isc->size); 641 isc->size = 0; 642 fail1: free(isc, M_AGP); 643 sc->as_chipc = NULL; 644 fail0: agp_generic_detach(sc); 645 KASSERT(error); 646 return error; 647 } 648 649 /* 650 * Skip pages reserved by the BIOS. Notably, skip 0xa0000-0xfffff, 651 * which includes the video BIOS at 0xc0000-0xdffff which the display 652 * drivers need for video mode detection. 653 * 654 * XXX Is there an MI name for this, or a conventional x86 name? Or 655 * should we really use bus_dma instead? 656 */ 657 #define PCIBIOS_MIN_MEM 0x100000 658 659 static int 660 agp_i810_setup_chipset_flush_page(struct agp_softc *sc) 661 { 662 struct agp_i810_softc *const isc = sc->as_chipc; 663 const pci_chipset_tag_t pc = sc->as_pc; 664 const pcitag_t tag = sc->as_tag; 665 pcireg_t lo, hi; 666 bus_addr_t addr, minaddr, maxaddr; 667 int error; 668 669 /* We always use memory-mapped I/O. */ 670 isc->flush_bst = isc->vga_pa.pa_memt; 671 672 /* No page allocated yet. */ 673 isc->flush_addr = 0; 674 675 /* Read the PCI config register: 4-byte on gen3, 8-byte on gen>=4. */ 676 if (isc->chiptype == CHIP_I915) { 677 addr = pci_conf_read(pc, tag, AGP_I915_IFPADDR); 678 minaddr = PCIBIOS_MIN_MEM; 679 maxaddr = UINT32_MAX; 680 } else { 681 hi = pci_conf_read(pc, tag, AGP_I965_IFPADDR+4); 682 lo = pci_conf_read(pc, tag, AGP_I965_IFPADDR); 683 /* 684 * Convert to uint64_t, rather than bus_addr_t which 685 * may be 32-bit, to avoid undefined behaviour with a 686 * too-wide shift. Since the BIOS doesn't know whether 687 * the OS will run 64-bit or with PAE, it ought to 688 * configure at most a 32-bit physical address, so 689 * let's print a warning in case that happens. 690 */ 691 addr = ((uint64_t)hi << 32) | lo; 692 if (hi) { 693 aprint_error_dev(sc->as_dev, 694 "BIOS configured >32-bit flush page address" 695 ": %"PRIx64"\n", ((uint64_t)hi << 32) | lo); 696 #if __i386__ && !PAE 697 return EIO; 698 #endif 699 } 700 minaddr = PCIBIOS_MIN_MEM; 701 maxaddr = MIN(UINT64_MAX, ~(bus_addr_t)0); 702 } 703 704 /* Allocate or map a pre-allocated a page for it. */ 705 if (ISSET(addr, 1)) { 706 /* BIOS allocated it for us. Use that. */ 707 error = bus_space_map(isc->flush_bst, addr & ~1, PAGE_SIZE, 0, 708 &isc->flush_bsh); 709 if (error) 710 return error; 711 } else { 712 /* None allocated. Allocate one. */ 713 error = bus_space_alloc(isc->flush_bst, minaddr, maxaddr, 714 PAGE_SIZE, PAGE_SIZE, 0, 0, 715 &isc->flush_addr, &isc->flush_bsh); 716 if (error) 717 return error; 718 KASSERT(isc->flush_addr != 0); 719 /* Write it into the PCI config register. */ 720 addr = isc->flush_addr | 1; 721 if (isc->chiptype == CHIP_I915) { 722 pci_conf_write(pc, tag, AGP_I915_IFPADDR, addr); 723 } else { 724 hi = __SHIFTOUT(addr, __BITS(63, 32)); 725 lo = __SHIFTOUT(addr, __BITS(31, 0)); 726 pci_conf_write(pc, tag, AGP_I965_IFPADDR+4, hi); 727 pci_conf_write(pc, tag, AGP_I965_IFPADDR, lo); 728 } 729 } 730 731 /* Success! */ 732 return 0; 733 } 734 735 static void 736 agp_i810_teardown_chipset_flush_page(struct agp_softc *sc) 737 { 738 struct agp_i810_softc *const isc = sc->as_chipc; 739 740 if (isc->flush_addr) { 741 /* If we allocated a page, clear it. */ 742 if (isc->chiptype == CHIP_I915) { 743 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR, 744 0); 745 } else { 746 pci_conf_write(sc->as_pc, sc->as_tag, 747 AGP_I965_IFPADDR, 0); 748 pci_conf_write(sc->as_pc, sc->as_tag, 749 AGP_I965_IFPADDR + 4, 0); 750 } 751 isc->flush_addr = 0; 752 bus_space_free(isc->flush_bst, isc->flush_bsh, PAGE_SIZE); 753 } else { 754 /* Otherwise, just unmap the pre-allocated page. */ 755 bus_space_unmap(isc->flush_bst, isc->flush_bsh, PAGE_SIZE); 756 } 757 } 758 759 /* 760 * XXX horrible hack to allow drm code to use our mapping 761 * of VGA chip registers 762 */ 763 int 764 agp_i810_borrow(bus_addr_t base, bus_size_t size, bus_space_handle_t *hdlp) 765 { 766 767 if (agp_i810_vga_regbase == 0) 768 return 0; 769 if (base < agp_i810_vga_regbase) 770 return 0; 771 if (agp_i810_vga_regsize < size) 772 return 0; 773 if ((base - agp_i810_vga_regbase) > (agp_i810_vga_regsize - size)) 774 return 0; 775 if (bus_space_subregion(agp_i810_vga_bst, agp_i810_vga_bsh, 776 (base - agp_i810_vga_regbase), (agp_i810_vga_regsize - size), 777 hdlp)) 778 return 0; 779 return 1; 780 } 781 782 static int 783 agp_i810_init(struct agp_softc *sc) 784 { 785 struct agp_i810_softc *isc; 786 int error; 787 788 isc = sc->as_chipc; 789 790 if (isc->chiptype == CHIP_I810) { 791 struct agp_gatt *gatt; 792 void *virtual; 793 int dummyseg; 794 795 /* Some i810s have on-chip memory called dcache */ 796 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 797 isc->dcache_size = 4 * 1024 * 1024; 798 else 799 isc->dcache_size = 0; 800 801 /* According to the specs the gatt on the i810 must be 64k */ 802 isc->gtt_size = 64 * 1024; 803 gatt = malloc(sizeof(*gatt), M_AGP, M_NOWAIT); 804 if (gatt == NULL) { 805 aprint_error_dev(sc->as_dev, 806 "can't malloc GATT record\n"); 807 error = ENOMEM; 808 goto fail0; 809 } 810 gatt->ag_entries = isc->gtt_size / sizeof(uint32_t); 811 error = agp_alloc_dmamem(sc->as_dmat, isc->gtt_size, 812 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical, 813 &gatt->ag_dmaseg, 1, &dummyseg); 814 if (error) { 815 aprint_error_dev(sc->as_dev, 816 "can't allocate memory for GTT: %d\n", error); 817 free(gatt, M_AGP); 818 goto fail0; 819 } 820 821 gatt->ag_virtual = (uint32_t *)virtual; 822 gatt->ag_size = gatt->ag_entries * sizeof(uint32_t); 823 memset(gatt->ag_virtual, 0, gatt->ag_size); 824 agp_flush_cache(); 825 826 /* Install the GATT. */ 827 isc->pgtblctl = gatt->ag_physical | 1; 828 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 829 isc->gatt = gatt; 830 } else if (isc->chiptype == CHIP_I830) { 831 /* The i830 automatically initializes the 128k gatt on boot. */ 832 /* XXX [citation needed] */ 833 pcireg_t reg; 834 u_int16_t gcc1; 835 836 isc->gtt_size = 128 * 1024; 837 838 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 839 gcc1 = (u_int16_t)(reg >> 16); 840 switch (gcc1 & AGP_I830_GCC1_GMS) { 841 case AGP_I830_GCC1_GMS_STOLEN_512: 842 isc->stolen = (512 - 132) * 1024 / 4096; 843 break; 844 case AGP_I830_GCC1_GMS_STOLEN_1024: 845 isc->stolen = (1024 - 132) * 1024 / 4096; 846 break; 847 case AGP_I830_GCC1_GMS_STOLEN_8192: 848 isc->stolen = (8192 - 132) * 1024 / 4096; 849 break; 850 default: 851 isc->stolen = 0; 852 aprint_error_dev(sc->as_dev, 853 "unknown memory configuration, disabling\n"); 854 error = ENXIO; 855 goto fail0; 856 } 857 858 if (isc->stolen > 0) { 859 aprint_normal_dev(sc->as_dev, 860 "detected %dk stolen memory\n", 861 isc->stolen * 4); 862 } 863 864 /* GATT address is already in there, make sure it's enabled */ 865 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 866 isc->pgtblctl |= 1; 867 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 868 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 869 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 || 870 isc->chiptype == CHIP_G4X) { 871 pcireg_t reg; 872 u_int32_t gtt_size, stolen; /* XXX kilobytes */ 873 u_int16_t gcc1; 874 875 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1); 876 gcc1 = (u_int16_t)(reg >> 16); 877 878 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 879 880 /* Stolen memory is set up at the beginning of the aperture by 881 * the BIOS, consisting of the GATT followed by 4kb for the 882 * BIOS display. 883 */ 884 switch (isc->chiptype) { 885 case CHIP_I855: 886 gtt_size = 128; 887 break; 888 case CHIP_I915: 889 gtt_size = 256; 890 break; 891 case CHIP_I965: 892 switch (isc->pgtblctl & AGP_I810_PGTBL_SIZE_MASK) { 893 case AGP_I810_PGTBL_SIZE_128KB: 894 case AGP_I810_PGTBL_SIZE_512KB: 895 gtt_size = 512; 896 break; 897 case AGP_I965_PGTBL_SIZE_1MB: 898 gtt_size = 1024; 899 break; 900 case AGP_I965_PGTBL_SIZE_2MB: 901 gtt_size = 2048; 902 break; 903 case AGP_I965_PGTBL_SIZE_1_5MB: 904 gtt_size = 1024 + 512; 905 break; 906 default: 907 aprint_error_dev(sc->as_dev, 908 "bad PGTBL size\n"); 909 error = ENXIO; 910 goto fail0; 911 } 912 break; 913 case CHIP_G33: 914 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 915 case AGP_G33_PGTBL_SIZE_1M: 916 gtt_size = 1024; 917 break; 918 case AGP_G33_PGTBL_SIZE_2M: 919 gtt_size = 2048; 920 break; 921 default: 922 aprint_error_dev(sc->as_dev, 923 "bad PGTBL size\n"); 924 error = ENXIO; 925 goto fail0; 926 } 927 break; 928 case CHIP_G4X: 929 switch (isc->pgtblctl & AGP_G4X_PGTBL_SIZE_MASK) { 930 case AGP_G4X_PGTBL_SIZE_512K: 931 gtt_size = 512; 932 break; 933 case AGP_G4X_PGTBL_SIZE_256K: 934 gtt_size = 256; 935 break; 936 case AGP_G4X_PGTBL_SIZE_128K: 937 gtt_size = 128; 938 break; 939 case AGP_G4X_PGTBL_SIZE_1M: 940 gtt_size = 1*1024; 941 break; 942 case AGP_G4X_PGTBL_SIZE_2M: 943 gtt_size = 2*1024; 944 break; 945 case AGP_G4X_PGTBL_SIZE_1_5M: 946 gtt_size = 1*1024 + 512; 947 break; 948 default: 949 aprint_error_dev(sc->as_dev, 950 "bad PGTBL size\n"); 951 error = ENXIO; 952 goto fail0; 953 } 954 break; 955 default: 956 panic("impossible chiptype %d", isc->chiptype); 957 } 958 959 /* 960 * XXX If I'm reading the datasheets right, this stolen 961 * memory detection logic is totally wrong. 962 */ 963 switch (gcc1 & AGP_I855_GCC1_GMS) { 964 case AGP_I855_GCC1_GMS_STOLEN_1M: 965 stolen = 1024; 966 break; 967 case AGP_I855_GCC1_GMS_STOLEN_4M: 968 stolen = 4 * 1024; 969 break; 970 case AGP_I855_GCC1_GMS_STOLEN_8M: 971 stolen = 8 * 1024; 972 break; 973 case AGP_I855_GCC1_GMS_STOLEN_16M: 974 stolen = 16 * 1024; 975 break; 976 case AGP_I855_GCC1_GMS_STOLEN_32M: 977 stolen = 32 * 1024; 978 break; 979 case AGP_I915_GCC1_GMS_STOLEN_48M: 980 stolen = 48 * 1024; 981 break; 982 case AGP_I915_GCC1_GMS_STOLEN_64M: 983 stolen = 64 * 1024; 984 break; 985 case AGP_G33_GCC1_GMS_STOLEN_128M: 986 stolen = 128 * 1024; 987 break; 988 case AGP_G33_GCC1_GMS_STOLEN_256M: 989 stolen = 256 * 1024; 990 break; 991 case AGP_G4X_GCC1_GMS_STOLEN_96M: 992 stolen = 96 * 1024; 993 break; 994 case AGP_G4X_GCC1_GMS_STOLEN_160M: 995 stolen = 160 * 1024; 996 break; 997 case AGP_G4X_GCC1_GMS_STOLEN_224M: 998 stolen = 224 * 1024; 999 break; 1000 case AGP_G4X_GCC1_GMS_STOLEN_352M: 1001 stolen = 352 * 1024; 1002 break; 1003 default: 1004 aprint_error_dev(sc->as_dev, 1005 "unknown memory configuration, disabling\n"); 1006 error = ENXIO; 1007 goto fail0; 1008 } 1009 1010 switch (gcc1 & AGP_I855_GCC1_GMS) { 1011 case AGP_I915_GCC1_GMS_STOLEN_48M: 1012 case AGP_I915_GCC1_GMS_STOLEN_64M: 1013 if (isc->chiptype != CHIP_I915 && 1014 isc->chiptype != CHIP_I965 && 1015 isc->chiptype != CHIP_G33 && 1016 isc->chiptype != CHIP_G4X) 1017 stolen = 0; 1018 break; 1019 case AGP_G33_GCC1_GMS_STOLEN_128M: 1020 case AGP_G33_GCC1_GMS_STOLEN_256M: 1021 if (isc->chiptype != CHIP_I965 && 1022 isc->chiptype != CHIP_G33 && 1023 isc->chiptype != CHIP_G4X) 1024 stolen = 0; 1025 break; 1026 case AGP_G4X_GCC1_GMS_STOLEN_96M: 1027 case AGP_G4X_GCC1_GMS_STOLEN_160M: 1028 case AGP_G4X_GCC1_GMS_STOLEN_224M: 1029 case AGP_G4X_GCC1_GMS_STOLEN_352M: 1030 if (isc->chiptype != CHIP_I965 && 1031 isc->chiptype != CHIP_G4X) 1032 stolen = 0; 1033 break; 1034 } 1035 1036 isc->gtt_size = gtt_size * 1024; 1037 1038 /* BIOS space */ 1039 /* XXX [citation needed] */ 1040 gtt_size += 4; 1041 1042 /* XXX [citation needed] for this subtraction */ 1043 isc->stolen = (stolen - gtt_size) * 1024 / 4096; 1044 1045 if (isc->stolen > 0) { 1046 aprint_normal_dev(sc->as_dev, 1047 "detected %dk stolen memory\n", 1048 isc->stolen * 4); 1049 } 1050 1051 /* GATT address is already in there, make sure it's enabled */ 1052 isc->pgtblctl |= 1; 1053 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 1054 } 1055 1056 /* 1057 * Make sure the chipset can see everything. 1058 */ 1059 agp_flush_cache(); 1060 1061 /* 1062 * Publish what we found for kludgey drivers (I'm looking at 1063 * you, drm). 1064 */ 1065 if (agp_i810_sc == NULL) 1066 agp_i810_sc = sc; 1067 else 1068 aprint_error_dev(sc->as_dev, "agp already attached\n"); 1069 1070 /* Success! */ 1071 return 0; 1072 1073 fail0: KASSERT(error); 1074 return error; 1075 } 1076 1077 #if 0 1078 static int 1079 agp_i810_detach(struct agp_softc *sc) 1080 { 1081 int error; 1082 struct agp_i810_softc *isc = sc->as_chipc; 1083 1084 error = agp_generic_detach(sc); 1085 if (error) 1086 return error; 1087 1088 switch (isc->chiptype) { 1089 case CHIP_I915: 1090 case CHIP_I965: 1091 case CHIP_G33: 1092 case CHIP_G4X: 1093 agp_i810_teardown_chipset_flush_page(sc); 1094 break; 1095 } 1096 1097 /* Clear the GATT base. */ 1098 if (sc->chiptype == CHIP_I810) { 1099 WRITE4(AGP_I810_PGTBL_CTL, 0); 1100 } else { 1101 unsigned int pgtblctl; 1102 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 1103 pgtblctl &= ~1; 1104 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 1105 } 1106 1107 if (sc->chiptype == CHIP_I810) { 1108 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap, 1109 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 1110 free(isc->gatt, M_AGP); 1111 } 1112 1113 return 0; 1114 } 1115 #endif 1116 1117 static u_int32_t 1118 agp_i810_get_aperture(struct agp_softc *sc) 1119 { 1120 struct agp_i810_softc *isc = sc->as_chipc; 1121 pcireg_t reg; 1122 u_int32_t size; 1123 u_int16_t miscc, gcc1; 1124 1125 size = 0; 1126 1127 switch (isc->chiptype) { 1128 case CHIP_I810: 1129 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 1130 miscc = (u_int16_t)(reg >> 16); 1131 if ((miscc & AGP_I810_MISCC_WINSIZE) == 1132 AGP_I810_MISCC_WINSIZE_32) 1133 size = 32 * 1024 * 1024; 1134 else 1135 size = 64 * 1024 * 1024; 1136 break; 1137 case CHIP_I830: 1138 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 1139 gcc1 = (u_int16_t)(reg >> 16); 1140 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 1141 size = 64 * 1024 * 1024; 1142 else 1143 size = 128 * 1024 * 1024; 1144 break; 1145 case CHIP_I855: 1146 size = 128 * 1024 * 1024; 1147 break; 1148 case CHIP_I915: 1149 case CHIP_G33: 1150 case CHIP_G4X: 1151 size = sc->as_apsize; 1152 break; 1153 case CHIP_I965: 1154 size = 512 * 1024 * 1024; 1155 break; 1156 default: 1157 aprint_error(": Unknown chipset\n"); 1158 } 1159 1160 return size; 1161 } 1162 1163 static int 1164 agp_i810_set_aperture(struct agp_softc *sc __unused, 1165 uint32_t aperture __unused) 1166 { 1167 1168 return ENOSYS; 1169 } 1170 1171 static int 1172 agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 1173 { 1174 struct agp_i810_softc *isc = sc->as_chipc; 1175 1176 if (offset < 0 || offset >= ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) { 1177 DPRINTF(sc, "failed" 1178 ": offset 0x%"PRIxMAX", shift %u, entries %"PRIuMAX"\n", 1179 (uintmax_t)offset, 1180 (unsigned)AGP_PAGE_SHIFT, 1181 (uintmax_t)isc->gtt_size/4); 1182 return EINVAL; 1183 } 1184 1185 if (isc->chiptype != CHIP_I810) { 1186 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1187 DPRINTF(sc, "trying to bind into stolen memory\n"); 1188 return EINVAL; 1189 } 1190 } 1191 1192 return agp_i810_write_gtt_entry(isc, offset, physical, 1193 AGP_I810_GTT_VALID); 1194 } 1195 1196 static int 1197 agp_i810_unbind_page(struct agp_softc *sc, off_t offset) 1198 { 1199 struct agp_i810_softc *isc = sc->as_chipc; 1200 1201 if (offset < 0 || offset >= ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) 1202 return EINVAL; 1203 1204 if (isc->chiptype != CHIP_I810 ) { 1205 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1206 DPRINTF(sc, "trying to unbind from stolen memory\n"); 1207 return EINVAL; 1208 } 1209 } 1210 1211 return agp_i810_write_gtt_entry(isc, offset, 0, 0); 1212 } 1213 1214 /* 1215 * Writing via memory mapped registers already flushes all TLBs. 1216 */ 1217 static void 1218 agp_i810_flush_tlb(struct agp_softc *sc) 1219 { 1220 } 1221 1222 static int 1223 agp_i810_enable(struct agp_softc *sc, u_int32_t mode) 1224 { 1225 1226 return 0; 1227 } 1228 1229 #define AGP_I810_MEMTYPE_MAIN 0 1230 #define AGP_I810_MEMTYPE_DCACHE 1 1231 #define AGP_I810_MEMTYPE_HWCURSOR 2 1232 1233 static struct agp_memory * 1234 agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size) 1235 { 1236 struct agp_i810_softc *isc = sc->as_chipc; 1237 struct agp_memory *mem; 1238 int error; 1239 1240 DPRINTF(sc, "AGP: alloc(%d, 0x%"PRIxMAX")\n", type, (uintmax_t)size); 1241 1242 if (size <= 0) 1243 return NULL; 1244 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 1245 return NULL; 1246 KASSERT(sc->as_allocated <= sc->as_maxmem); 1247 if (size > (sc->as_maxmem - sc->as_allocated)) 1248 return NULL; 1249 if (size > ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) 1250 return NULL; 1251 1252 switch (type) { 1253 case AGP_I810_MEMTYPE_MAIN: 1254 break; 1255 case AGP_I810_MEMTYPE_DCACHE: 1256 if (isc->chiptype != CHIP_I810) 1257 return NULL; 1258 if (size != isc->dcache_size) 1259 return NULL; 1260 break; 1261 case AGP_I810_MEMTYPE_HWCURSOR: 1262 if ((size != AGP_PAGE_SIZE) && 1263 (size != AGP_PAGE_SIZE*4)) 1264 return NULL; 1265 break; 1266 default: 1267 return NULL; 1268 } 1269 1270 mem = malloc(sizeof(*mem), M_AGP, M_WAITOK|M_ZERO); 1271 if (mem == NULL) 1272 goto fail0; 1273 mem->am_id = sc->as_nextid++; 1274 mem->am_size = size; 1275 mem->am_type = type; 1276 1277 switch (type) { 1278 case AGP_I810_MEMTYPE_MAIN: 1279 error = bus_dmamap_create(sc->as_dmat, size, 1280 (size >> AGP_PAGE_SHIFT) + 1, size, 0, BUS_DMA_WAITOK, 1281 &mem->am_dmamap); 1282 if (error) 1283 goto fail1; 1284 break; 1285 case AGP_I810_MEMTYPE_DCACHE: 1286 break; 1287 case AGP_I810_MEMTYPE_HWCURSOR: 1288 mem->am_dmaseg = malloc(sizeof(*mem->am_dmaseg), M_AGP, 1289 M_WAITOK); 1290 error = agp_alloc_dmamem(sc->as_dmat, size, 0, &mem->am_dmamap, 1291 &mem->am_virtual, &mem->am_physical, mem->am_dmaseg, 1, 1292 &mem->am_nseg); 1293 if (error) { 1294 free(mem->am_dmaseg, M_AGP); 1295 goto fail1; 1296 } 1297 (void)memset(mem->am_virtual, 0, size); 1298 break; 1299 default: 1300 panic("invalid agp memory type: %d", type); 1301 } 1302 1303 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link); 1304 sc->as_allocated += size; 1305 1306 return mem; 1307 1308 fail1: free(mem, M_AGP); 1309 fail0: return NULL; 1310 } 1311 1312 static int 1313 agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem) 1314 { 1315 1316 if (mem->am_is_bound) 1317 return EBUSY; 1318 1319 switch (mem->am_type) { 1320 case AGP_I810_MEMTYPE_MAIN: 1321 bus_dmamap_destroy(sc->as_dmat, mem->am_dmamap); 1322 break; 1323 case AGP_I810_MEMTYPE_DCACHE: 1324 break; 1325 case AGP_I810_MEMTYPE_HWCURSOR: 1326 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap, 1327 mem->am_virtual, mem->am_dmaseg, mem->am_nseg); 1328 free(mem->am_dmaseg, M_AGP); 1329 break; 1330 default: 1331 panic("invalid agp i810 memory type: %d", mem->am_type); 1332 } 1333 1334 sc->as_allocated -= mem->am_size; 1335 TAILQ_REMOVE(&sc->as_memory, mem, am_link); 1336 free(mem, M_AGP); 1337 1338 return 0; 1339 } 1340 1341 static int 1342 agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem, 1343 off_t offset) 1344 { 1345 struct agp_i810_softc *isc = sc->as_chipc; 1346 uint32_t pgtblctl; 1347 int error; 1348 1349 if (mem->am_is_bound) 1350 return EINVAL; 1351 1352 /* 1353 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 1354 * X server for mysterious reasons which leads to crashes if we write 1355 * to the GTT through the MMIO window. 1356 * Until the issue is solved, simply restore it. 1357 */ 1358 pgtblctl = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL); 1359 if (pgtblctl != isc->pgtblctl) { 1360 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%"PRIx32 1361 " - fixing\n", pgtblctl); 1362 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 1363 isc->pgtblctl); 1364 } 1365 1366 switch (mem->am_type) { 1367 case AGP_I810_MEMTYPE_MAIN: 1368 return agp_generic_bind_memory_bounded(sc, mem, offset, 1369 0, (isc->gtt_size/4) << AGP_PAGE_SHIFT); 1370 case AGP_I810_MEMTYPE_DCACHE: 1371 error = agp_i810_bind_memory_dcache(sc, mem, offset); 1372 break; 1373 case AGP_I810_MEMTYPE_HWCURSOR: 1374 error = agp_i810_bind_memory_hwcursor(sc, mem, offset); 1375 break; 1376 default: 1377 panic("invalid agp i810 memory type: %d", mem->am_type); 1378 } 1379 if (error) 1380 return error; 1381 1382 /* Success! */ 1383 mem->am_is_bound = 1; 1384 return 0; 1385 } 1386 1387 static int 1388 agp_i810_bind_memory_dcache(struct agp_softc *sc, struct agp_memory *mem, 1389 off_t offset) 1390 { 1391 struct agp_i810_softc *const isc __diagused = sc->as_chipc; 1392 uint32_t i, j; 1393 int error; 1394 1395 KASSERT(isc->chiptype == CHIP_I810); 1396 1397 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0); 1398 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 1399 error = agp_i810_write_gtt_entry(isc, offset + i, 1400 i, AGP_I810_GTT_VALID | AGP_I810_GTT_I810_DCACHE); 1401 if (error) 1402 goto fail0; 1403 } 1404 1405 /* Success! */ 1406 mem->am_offset = offset; 1407 return 0; 1408 1409 fail0: for (j = 0; j < i; j += AGP_PAGE_SIZE) 1410 (void)agp_i810_unbind_page(sc, offset + j); 1411 return error; 1412 } 1413 1414 static int 1415 agp_i810_bind_memory_hwcursor(struct agp_softc *sc, struct agp_memory *mem, 1416 off_t offset) 1417 { 1418 const bus_addr_t pa = mem->am_physical; 1419 uint32_t i, j; 1420 int error; 1421 1422 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0); 1423 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 1424 error = agp_i810_bind_page(sc, offset + i, pa + i); 1425 if (error) 1426 goto fail0; 1427 } 1428 1429 /* Success! */ 1430 mem->am_offset = offset; 1431 return 0; 1432 1433 fail0: for (j = 0; j < i; j += AGP_PAGE_SIZE) 1434 (void)agp_i810_unbind_page(sc, offset + j); 1435 return error; 1436 } 1437 1438 static int 1439 agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem) 1440 { 1441 struct agp_i810_softc *isc __diagused = sc->as_chipc; 1442 u_int32_t i; 1443 1444 if (!mem->am_is_bound) 1445 return EINVAL; 1446 1447 switch (mem->am_type) { 1448 case AGP_I810_MEMTYPE_MAIN: 1449 return agp_generic_unbind_memory(sc, mem); 1450 case AGP_I810_MEMTYPE_DCACHE: 1451 KASSERT(isc->chiptype == CHIP_I810); 1452 /* FALLTHROUGH */ 1453 case AGP_I810_MEMTYPE_HWCURSOR: 1454 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1455 (void)agp_i810_unbind_page(sc, mem->am_offset + i); 1456 mem->am_offset = 0; 1457 break; 1458 default: 1459 panic("invalid agp i810 memory type: %d", mem->am_type); 1460 } 1461 1462 mem->am_is_bound = 0; 1463 return 0; 1464 } 1465 1466 static bool 1467 agp_i810_resume(device_t dv, const pmf_qual_t *qual) 1468 { 1469 struct agp_softc *sc = device_private(dv); 1470 struct agp_i810_softc *isc = sc->as_chipc; 1471 1472 /* 1473 * XXX Nothing uses this! Save on suspend, restore on resume? 1474 */ 1475 isc->pgtblctl_resume_hack = READ4(AGP_I810_PGTBL_CTL); 1476 agp_flush_cache(); 1477 1478 return true; 1479 } 1480
Indexes created Sun Sep 28 16:09:52 GMT 2025