agp_i810.c revision 1.122.18.2
1 /* $NetBSD: agp_i810.c,v 1.122.18.2 2020/04/13 08:04:26 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.122.18.2 2020/04/13 08:04:26 martin Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/atomic.h> 38 #include <sys/malloc.h> 39 #include <sys/kernel.h> 40 #include <sys/proc.h> 41 #include <sys/device.h> 42 #include <sys/conf.h> 43 #include <sys/xcall.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/agpvar.h> 49 #include <dev/pci/agpreg.h> 50 #include <dev/pci/agp_i810var.h> 51 52 #include <sys/agpio.h> 53 54 #include <sys/bus.h> 55 56 #include "agp_intel.h" 57 58 #ifdef AGP_DEBUG 59 #define DPRINTF(sc, fmt, ...) \ 60 device_printf((sc)->as_dev, "%s: " fmt, __func__, ##__VA_ARGS__) 61 #else 62 #define DPRINTF(sc, fmt, ...) do {} while (0) 63 #endif 64 65 struct agp_softc *agp_i810_sc = NULL; 66 67 #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off) 68 #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off) 69 #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v) 70 71 #define CHIP_I810 0 /* i810/i815 */ 72 #define CHIP_I830 1 /* 830M/845G */ 73 #define CHIP_I855 2 /* 852GM/855GM/865G */ 74 #define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */ 75 #define CHIP_I965 4 /* 965Q/965PM */ 76 #define CHIP_G33 5 /* G33/Q33/Q35 */ 77 #define CHIP_G4X 6 /* G45/Q45 */ 78 #define CHIP_PINEVIEW 7 /* Pineview */ 79 80 /* XXX hack, see below */ 81 static bus_addr_t agp_i810_vga_regbase; 82 static bus_size_t agp_i810_vga_regsize; 83 static bus_space_tag_t agp_i810_vga_bst; 84 static bus_space_handle_t agp_i810_vga_bsh; 85 86 static u_int32_t agp_i810_get_aperture(struct agp_softc *); 87 static int agp_i810_set_aperture(struct agp_softc *, u_int32_t); 88 static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t); 89 static int agp_i810_unbind_page(struct agp_softc *, off_t); 90 static void agp_i810_flush_tlb(struct agp_softc *); 91 static int agp_i810_enable(struct agp_softc *, u_int32_t mode); 92 static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int, 93 vsize_t); 94 static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *); 95 static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, 96 off_t); 97 static int agp_i810_bind_memory_dcache(struct agp_softc *, struct agp_memory *, 98 off_t); 99 static int agp_i810_bind_memory_hwcursor(struct agp_softc *, 100 struct agp_memory *, off_t); 101 static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *); 102 103 static bool agp_i810_resume(device_t, const pmf_qual_t *); 104 static int agp_i810_init(struct agp_softc *); 105 106 static int agp_i810_setup_chipset_flush_page(struct agp_softc *); 107 static void agp_i810_teardown_chipset_flush_page(struct agp_softc *); 108 static int agp_i810_init(struct agp_softc *); 109 110 static struct agp_methods agp_i810_methods = { 111 agp_i810_get_aperture, 112 agp_i810_set_aperture, 113 agp_i810_bind_page, 114 agp_i810_unbind_page, 115 agp_i810_flush_tlb, 116 agp_i810_enable, 117 agp_i810_alloc_memory, 118 agp_i810_free_memory, 119 agp_i810_bind_memory, 120 agp_i810_unbind_memory, 121 }; 122 123 int 124 agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, 125 bus_addr_t addr, int flags) 126 { 127 u_int32_t pte; 128 129 /* 130 * Bits 11:4 (physical start address extension) should be zero. 131 * Flag bits 3:0 should be zero too. 132 * 133 * XXX This should be a kassert -- no reason for this routine 134 * to allow failure. 135 */ 136 if ((addr & 0xfff) != 0) 137 return EINVAL; 138 KASSERT(flags == (flags & 0x7)); 139 140 pte = (u_int32_t)addr; 141 /* 142 * We need to massage the pte if bus_addr_t is wider than 32 bits. 143 * The compiler isn't smart enough, hence the casts to uintmax_t. 144 */ 145 if (sizeof(bus_addr_t) > sizeof(u_int32_t)) { 146 /* 965+ can do 36-bit addressing, add in the extra bits. */ 147 if (isc->chiptype == CHIP_I965 || 148 isc->chiptype == CHIP_G33 || 149 isc->chiptype == CHIP_PINEVIEW || 150 isc->chiptype == CHIP_G4X) { 151 if (((uintmax_t)addr >> 36) != 0) 152 return EINVAL; 153 pte |= (addr >> 28) & 0xf0; 154 } else { 155 if (((uintmax_t)addr >> 32) != 0) 156 return EINVAL; 157 } 158 } 159 160 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, 161 4*(off >> AGP_PAGE_SHIFT), pte | flags); 162 163 return 0; 164 } 165 166 void 167 agp_i810_post_gtt_entry(struct agp_i810_softc *isc, off_t off) 168 { 169 170 /* 171 * See <https://bugs.freedesktop.org/show_bug.cgi?id=88191>. 172 * Out of paranoia, let's do the write barrier and posting 173 * read, because I don't have enough time or hardware to 174 * conduct conclusive tests. 175 */ 176 membar_producer(); 177 (void)bus_space_read_4(isc->gtt_bst, isc->gtt_bsh, 178 4*(off >> AGP_PAGE_SHIFT)); 179 } 180 181 static void 182 agp_flush_cache_xc(void *a __unused, void *b __unused) 183 { 184 185 agp_flush_cache(); 186 } 187 188 void 189 agp_i810_chipset_flush(struct agp_i810_softc *isc) 190 { 191 unsigned int timo = 20000; /* * 50 us = 1 s */ 192 193 switch (isc->chiptype) { 194 case CHIP_I810: 195 break; 196 case CHIP_I830: 197 case CHIP_I855: 198 /* 199 * Flush all CPU caches. If we're cold, we can't run 200 * xcalls, but there should be only one CPU up, so 201 * flushing only the local CPU's cache should suffice. 202 * 203 * XXX Come to think of it, do these chipsets appear in 204 * any multi-CPU systems? 205 */ 206 if (cold) 207 agp_flush_cache(); 208 else 209 xc_wait(xc_broadcast(0, &agp_flush_cache_xc, 210 NULL, NULL)); 211 WRITE4(AGP_I830_HIC, READ4(AGP_I830_HIC) | __BIT(31)); 212 while (ISSET(READ4(AGP_I830_HIC), __BIT(31))) { 213 if (timo-- == 0) 214 break; 215 DELAY(50); 216 } 217 break; 218 case CHIP_I915: 219 case CHIP_I965: 220 case CHIP_G33: 221 case CHIP_PINEVIEW: 222 case CHIP_G4X: 223 bus_space_write_4(isc->flush_bst, isc->flush_bsh, 0, 1); 224 break; 225 } 226 } 227 228 /* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */ 229 static int 230 agp_i810_vgamatch(const struct pci_attach_args *pa) 231 { 232 233 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 234 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 235 return (0); 236 237 switch (PCI_PRODUCT(pa->pa_id)) { 238 case PCI_PRODUCT_INTEL_82810_GC: 239 case PCI_PRODUCT_INTEL_82810_DC100_GC: 240 case PCI_PRODUCT_INTEL_82810E_GC: 241 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 242 case PCI_PRODUCT_INTEL_82830MP_IV: 243 case PCI_PRODUCT_INTEL_82845G_IGD: 244 case PCI_PRODUCT_INTEL_82855GM_IGD: 245 case PCI_PRODUCT_INTEL_82865_IGD: 246 case PCI_PRODUCT_INTEL_82915G_IGD: 247 case PCI_PRODUCT_INTEL_82915GM_IGD: 248 case PCI_PRODUCT_INTEL_82945P_IGD: 249 case PCI_PRODUCT_INTEL_82945GM_IGD: 250 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 251 case PCI_PRODUCT_INTEL_82945GME_IGD: 252 case PCI_PRODUCT_INTEL_E7221_IGD: 253 case PCI_PRODUCT_INTEL_82965Q_IGD: 254 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 255 case PCI_PRODUCT_INTEL_82965PM_IGD: 256 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 257 case PCI_PRODUCT_INTEL_82G33_IGD: 258 case PCI_PRODUCT_INTEL_82G33_IGD_1: 259 case PCI_PRODUCT_INTEL_82965G_IGD: 260 case PCI_PRODUCT_INTEL_82965G_IGD_1: 261 case PCI_PRODUCT_INTEL_82965GME_IGD: 262 case PCI_PRODUCT_INTEL_82Q35_IGD: 263 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 264 case PCI_PRODUCT_INTEL_82Q33_IGD: 265 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 266 case PCI_PRODUCT_INTEL_82G35_IGD: 267 case PCI_PRODUCT_INTEL_82G35_IGD_1: 268 case PCI_PRODUCT_INTEL_82946GZ_IGD: 269 case PCI_PRODUCT_INTEL_82GM45_IGD: 270 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 271 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 272 case PCI_PRODUCT_INTEL_82Q45_IGD: 273 case PCI_PRODUCT_INTEL_82G45_IGD: 274 case PCI_PRODUCT_INTEL_82G41_IGD: 275 case PCI_PRODUCT_INTEL_82B43_IGD: 276 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 277 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 278 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 279 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 280 return (1); 281 } 282 283 return (0); 284 } 285 286 static int 287 agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg) 288 { 289 /* 290 * Find the aperture. Don't map it (yet), this would 291 * eat KVA. 292 */ 293 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 294 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize, 295 &sc->as_apflags) != 0) 296 return ENXIO; 297 298 sc->as_apt = pa->pa_memt; 299 300 return 0; 301 } 302 303 int 304 agp_i810_attach(device_t parent, device_t self, void *aux) 305 { 306 struct agp_softc *sc = device_private(self); 307 struct agp_i810_softc *isc; 308 int apbase, mmadr_bar, gtt_bar; 309 int mmadr_type, mmadr_flags; 310 bus_addr_t mmadr; 311 bus_size_t mmadr_size, gtt_off; 312 int error; 313 314 isc = malloc(sizeof *isc, M_AGP, M_WAITOK|M_ZERO); 315 sc->as_chipc = isc; 316 sc->as_methods = &agp_i810_methods; 317 318 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) { 319 #if NAGP_INTEL > 0 320 const struct pci_attach_args *pa = aux; 321 322 switch (PCI_PRODUCT(pa->pa_id)) { 323 case PCI_PRODUCT_INTEL_82840_HB: 324 case PCI_PRODUCT_INTEL_82865_HB: 325 case PCI_PRODUCT_INTEL_82845G_DRAM: 326 case PCI_PRODUCT_INTEL_82815_FULL_HUB: 327 case PCI_PRODUCT_INTEL_82855GM_MCH: 328 free(isc, M_AGP); 329 return agp_intel_attach(parent, self, aux); 330 } 331 #endif 332 aprint_error(": can't find internal VGA" 333 " config space\n"); 334 error = ENOENT; 335 goto fail1; 336 } 337 338 /* XXXfvdl */ 339 sc->as_dmat = isc->vga_pa.pa_dmat; 340 341 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 342 case PCI_PRODUCT_INTEL_82810_GC: 343 case PCI_PRODUCT_INTEL_82810_DC100_GC: 344 case PCI_PRODUCT_INTEL_82810E_GC: 345 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 346 isc->chiptype = CHIP_I810; 347 aprint_normal(": i810-family chipset\n"); 348 break; 349 case PCI_PRODUCT_INTEL_82830MP_IV: 350 case PCI_PRODUCT_INTEL_82845G_IGD: 351 isc->chiptype = CHIP_I830; 352 aprint_normal(": i830-family chipset\n"); 353 break; 354 case PCI_PRODUCT_INTEL_82855GM_IGD: 355 case PCI_PRODUCT_INTEL_82865_IGD: 356 isc->chiptype = CHIP_I855; 357 aprint_normal(": i855-family chipset\n"); 358 break; 359 case PCI_PRODUCT_INTEL_82915G_IGD: 360 case PCI_PRODUCT_INTEL_82915GM_IGD: 361 case PCI_PRODUCT_INTEL_82945P_IGD: 362 case PCI_PRODUCT_INTEL_82945GM_IGD: 363 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 364 case PCI_PRODUCT_INTEL_82945GME_IGD: 365 case PCI_PRODUCT_INTEL_E7221_IGD: 366 isc->chiptype = CHIP_I915; 367 aprint_normal(": i915-family chipset\n"); 368 break; 369 case PCI_PRODUCT_INTEL_82965Q_IGD: 370 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 371 case PCI_PRODUCT_INTEL_82965PM_IGD: 372 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 373 case PCI_PRODUCT_INTEL_82965G_IGD: 374 case PCI_PRODUCT_INTEL_82965G_IGD_1: 375 case PCI_PRODUCT_INTEL_82965GME_IGD: 376 case PCI_PRODUCT_INTEL_82946GZ_IGD: 377 case PCI_PRODUCT_INTEL_82G35_IGD: 378 case PCI_PRODUCT_INTEL_82G35_IGD_1: 379 isc->chiptype = CHIP_I965; 380 aprint_normal(": i965-family chipset\n"); 381 break; 382 case PCI_PRODUCT_INTEL_82Q35_IGD: 383 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 384 case PCI_PRODUCT_INTEL_82G33_IGD: 385 case PCI_PRODUCT_INTEL_82G33_IGD_1: 386 case PCI_PRODUCT_INTEL_82Q33_IGD: 387 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 388 isc->chiptype = CHIP_G33; 389 aprint_normal(": G33-family chipset\n"); 390 break; 391 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 392 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 393 isc->chiptype = CHIP_PINEVIEW; 394 aprint_normal(": Pineview chipset\n"); 395 break; 396 case PCI_PRODUCT_INTEL_82GM45_IGD: 397 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 398 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 399 case PCI_PRODUCT_INTEL_82Q45_IGD: 400 case PCI_PRODUCT_INTEL_82G45_IGD: 401 case PCI_PRODUCT_INTEL_82G41_IGD: 402 case PCI_PRODUCT_INTEL_82B43_IGD: 403 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 404 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 405 isc->chiptype = CHIP_G4X; 406 aprint_normal(": G4X-family chipset\n"); 407 break; 408 } 409 aprint_naive("\n"); 410 411 /* Discriminate on the chipset to choose the relevant BARs. */ 412 switch (isc->chiptype) { 413 case CHIP_I915: 414 case CHIP_G33: 415 case CHIP_PINEVIEW: 416 apbase = AGP_I915_GMADR; 417 mmadr_bar = AGP_I915_MMADR; 418 gtt_bar = AGP_I915_GTTADR; 419 gtt_off = ~(bus_size_t)0; /* XXXGCC */ 420 break; 421 case CHIP_I965: 422 apbase = AGP_I965_GMADR; 423 mmadr_bar = AGP_I965_MMADR; 424 gtt_bar = 0; 425 gtt_off = AGP_I965_GTT; 426 break; 427 case CHIP_G4X: 428 apbase = AGP_I965_GMADR; 429 mmadr_bar = AGP_I965_MMADR; 430 gtt_bar = 0; 431 gtt_off = AGP_G4X_GTT; 432 break; 433 default: 434 apbase = AGP_I810_GMADR; 435 mmadr_bar = AGP_I810_MMADR; 436 gtt_bar = 0; 437 gtt_off = AGP_I810_GTT; 438 break; 439 } 440 441 /* 442 * Ensure the MMIO BAR is, in fact, a memory BAR. 443 * 444 * XXX This is required because we use pa_memt below. It is 445 * not a priori clear to me there is any other reason to 446 * require this. 447 */ 448 mmadr_type = pci_mapreg_type(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, 449 mmadr_bar); 450 if (PCI_MAPREG_TYPE(mmadr_type) != PCI_MAPREG_TYPE_MEM) { 451 aprint_error_dev(self, "non-memory device MMIO registers\n"); 452 error = ENXIO; 453 goto fail1; 454 } 455 456 /* 457 * Determine the size of the MMIO registers. 458 * 459 * XXX The size of the MMIO registers we use is statically 460 * determined, as a function of the chipset, by the driver's 461 * implementation. 462 * 463 * On some chipsets, the GTT is part of the MMIO register BAR. 464 * We would like to map the GTT separately, so that we can map 465 * it prefetchable, which we can't do with the MMIO registers. 466 * Consequently, we would especially like to map a fixed size 467 * of MMIO registers, not just whatever size the BAR says. 468 * 469 * However, old drm assumes that the combined GTT/MMIO register 470 * space is a single bus space mapping, so mapping them 471 * separately breaks that. Once we rip out old drm, we can 472 * replace the pci_mapreg_info call by the chipset switch. 473 */ 474 #if notyet 475 switch (isc->chiptype) { 476 case CHIP_I810: 477 case CHIP_I830: 478 case CHIP_I855: 479 case CHIP_I915: 480 case CHIP_I965: 481 case CHIP_G33: 482 case CHIP_PINEVIEW: 483 case CHIP_G4X: 484 isc->size = 512*1024; 485 break; 486 case CHIP_SANDYBRIDGE: 487 case CHIP_IVYBRIDGE: 488 case CHIP_HASWELL: 489 isc->size = 2*1024*1024; 490 break; 491 } 492 #else 493 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, 494 mmadr_bar, mmadr_type, NULL, &isc->size, NULL)) 495 isc->size = 512*1024; 496 #endif /* notyet */ 497 498 /* Map (or, rather, find the address and size of) the aperture. */ 499 if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) 500 error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase); 501 else 502 error = agp_map_aperture(&isc->vga_pa, sc, apbase); 503 if (error) { 504 aprint_error_dev(self, "can't map aperture: %d\n", error); 505 goto fail1; 506 } 507 508 /* Map the memory-mapped I/O registers, or the non-GTT part. */ 509 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, mmadr_bar, 510 mmadr_type, &mmadr, &mmadr_size, &mmadr_flags)) { 511 aprint_error_dev(self, "can't find MMIO registers\n"); 512 error = ENXIO; 513 goto fail1; 514 } 515 if (mmadr_size < isc->size) { 516 aprint_error_dev(self, "MMIO registers too small" 517 ": %"PRIuMAX" < %"PRIuMAX"\n", 518 (uintmax_t)mmadr_size, (uintmax_t)isc->size); 519 error = ENXIO; 520 goto fail1; 521 } 522 isc->bst = isc->vga_pa.pa_memt; 523 error = bus_space_map(isc->bst, mmadr, isc->size, mmadr_flags, 524 &isc->bsh); 525 if (error) { 526 aprint_error_dev(self, "can't map MMIO registers: %d\n", 527 error); 528 error = ENXIO; 529 goto fail1; 530 } 531 532 /* Set up a chipset flush page if necessary. */ 533 switch (isc->chiptype) { 534 case CHIP_I915: 535 case CHIP_I965: 536 case CHIP_G33: 537 case CHIP_PINEVIEW: 538 case CHIP_G4X: 539 error = agp_i810_setup_chipset_flush_page(sc); 540 if (error) { 541 aprint_error_dev(self, 542 "can't set up chipset flush page: %d\n", error); 543 goto fail2; 544 } 545 break; 546 } 547 548 /* 549 * XXX horrible hack to allow drm code to use our mapping 550 * of VGA chip registers 551 */ 552 agp_i810_vga_regbase = mmadr; 553 agp_i810_vga_regsize = isc->size; 554 agp_i810_vga_bst = isc->bst; 555 agp_i810_vga_bsh = isc->bsh; 556 557 /* Initialize the chipset. */ 558 error = agp_i810_init(sc); 559 if (error) 560 goto fail3; 561 562 /* Map the GTT, from either part of the MMIO region or its own BAR. */ 563 if (gtt_bar == 0) { 564 isc->gtt_bst = isc->bst; 565 if ((mmadr_size - gtt_off) < isc->gtt_size) { 566 aprint_error_dev(self, "GTTMMADR too small for GTT" 567 ": (%"PRIxMAX" - %"PRIxMAX") < %"PRIxMAX"\n", 568 (uintmax_t)mmadr_size, 569 (uintmax_t)gtt_off, 570 (uintmax_t)isc->gtt_size); 571 error = ENXIO; 572 goto fail4; 573 } 574 /* 575 * Map the GTT separately if we can, so that we can map 576 * it prefetchable, but in early models, there are MMIO 577 * registers before and after the GTT, so we can only 578 * take a subregion. 579 */ 580 if (isc->size < gtt_off) 581 error = bus_space_map(isc->gtt_bst, (mmadr + gtt_off), 582 isc->gtt_size, mmadr_flags, &isc->gtt_bsh); 583 else 584 error = bus_space_subregion(isc->bst, isc->bsh, 585 gtt_off, isc->gtt_size, &isc->gtt_bsh); 586 if (error) { 587 aprint_error_dev(self, "can't map GTT: %d\n", error); 588 error = ENXIO; 589 goto fail4; 590 } 591 } else { 592 bus_size_t gtt_bar_size; 593 /* 594 * All chipsets with a separate BAR for the GTT, namely 595 * the i915 and G33 families, have 32-bit GTT BARs. 596 * 597 * XXX [citation needed] 598 */ 599 if (pci_mapreg_map(&isc->vga_pa, gtt_bar, PCI_MAPREG_TYPE_MEM, 600 0, 601 &isc->gtt_bst, &isc->gtt_bsh, NULL, >t_bar_size)) { 602 aprint_error_dev(self, "can't map GTT\n"); 603 error = ENXIO; 604 goto fail4; 605 } 606 if (gtt_bar_size != isc->gtt_size) { 607 aprint_error_dev(self, 608 "BAR size %"PRIxMAX 609 " mismatches detected GTT size %"PRIxMAX 610 "; trusting BAR\n", 611 (uintmax_t)gtt_bar_size, 612 (uintmax_t)isc->gtt_size); 613 isc->gtt_size = gtt_bar_size; 614 } 615 } 616 617 /* Power management. (XXX Nothing to save on suspend? Fishy...) */ 618 if (!pmf_device_register(self, NULL, agp_i810_resume)) 619 aprint_error_dev(self, "can't establish power handler\n"); 620 621 /* Match the generic AGP code's autoconf output format. */ 622 aprint_normal("%s", device_xname(self)); 623 624 /* Success! */ 625 return 0; 626 627 fail5: __unused 628 pmf_device_deregister(self); 629 if ((gtt_bar != 0) || (isc->size < gtt_off)) 630 bus_space_unmap(isc->gtt_bst, isc->gtt_bsh, isc->gtt_size); 631 isc->gtt_size = 0; 632 fail4: 633 #if notyet 634 agp_i810_fini(sc); 635 #endif 636 fail3: switch (isc->chiptype) { 637 case CHIP_I915: 638 case CHIP_I965: 639 case CHIP_G33: 640 case CHIP_PINEVIEW: 641 case CHIP_G4X: 642 agp_i810_teardown_chipset_flush_page(sc); 643 break; 644 } 645 fail2: bus_space_unmap(isc->bst, isc->bsh, isc->size); 646 isc->size = 0; 647 fail1: free(isc, M_AGP); 648 sc->as_chipc = NULL; 649 agp_generic_detach(sc); 650 KASSERT(error); 651 return error; 652 } 653 654 /* 655 * Skip pages reserved by the BIOS. Notably, skip 0xa0000-0xfffff, 656 * which includes the video BIOS at 0xc0000-0xdffff which the display 657 * drivers need for video mode detection. 658 * 659 * XXX Is there an MI name for this, or a conventional x86 name? Or 660 * should we really use bus_dma instead? 661 */ 662 #define PCIBIOS_MIN_MEM 0x100000 663 664 static int 665 agp_i810_setup_chipset_flush_page(struct agp_softc *sc) 666 { 667 struct agp_i810_softc *const isc = sc->as_chipc; 668 const pci_chipset_tag_t pc = sc->as_pc; 669 const pcitag_t tag = sc->as_tag; 670 pcireg_t lo, hi; 671 bus_addr_t addr, minaddr, maxaddr; 672 int error; 673 674 /* We always use memory-mapped I/O. */ 675 isc->flush_bst = isc->vga_pa.pa_memt; 676 677 /* No page allocated yet. */ 678 isc->flush_addr = 0; 679 680 /* Read the PCI config register: 4-byte on gen3, 8-byte on gen>=4. */ 681 if (isc->chiptype == CHIP_I915) { 682 addr = pci_conf_read(pc, tag, AGP_I915_IFPADDR); 683 minaddr = PCIBIOS_MIN_MEM; 684 maxaddr = UINT32_MAX; 685 } else { 686 hi = pci_conf_read(pc, tag, AGP_I965_IFPADDR+4); 687 lo = pci_conf_read(pc, tag, AGP_I965_IFPADDR); 688 /* 689 * Convert to uint64_t, rather than bus_addr_t which 690 * may be 32-bit, to avoid undefined behaviour with a 691 * too-wide shift. Since the BIOS doesn't know whether 692 * the OS will run 64-bit or with PAE, it ought to 693 * configure at most a 32-bit physical address, so 694 * let's print a warning in case that happens. 695 */ 696 addr = ((uint64_t)hi << 32) | lo; 697 if (hi) { 698 aprint_error_dev(sc->as_dev, 699 "BIOS configured >32-bit flush page address" 700 ": %"PRIx64"\n", ((uint64_t)hi << 32) | lo); 701 #if __i386__ && !PAE 702 return EIO; 703 #endif 704 } 705 minaddr = PCIBIOS_MIN_MEM; 706 maxaddr = MIN(UINT64_MAX, ~(bus_addr_t)0); 707 } 708 709 /* Allocate or map a pre-allocated a page for it. */ 710 if (ISSET(addr, 1)) { 711 /* BIOS allocated it for us. Use that. */ 712 error = bus_space_map(isc->flush_bst, addr & ~1, PAGE_SIZE, 0, 713 &isc->flush_bsh); 714 if (error) 715 return error; 716 } else { 717 /* None allocated. Allocate one. */ 718 error = bus_space_alloc(isc->flush_bst, minaddr, maxaddr, 719 PAGE_SIZE, PAGE_SIZE, 0, 0, 720 &isc->flush_addr, &isc->flush_bsh); 721 if (error) 722 return error; 723 KASSERT(isc->flush_addr != 0); 724 /* Write it into the PCI config register. */ 725 addr = isc->flush_addr | 1; 726 if (isc->chiptype == CHIP_I915) { 727 pci_conf_write(pc, tag, AGP_I915_IFPADDR, addr); 728 } else { 729 hi = __SHIFTOUT(addr, __BITS(63, 32)); 730 lo = __SHIFTOUT(addr, __BITS(31, 0)); 731 pci_conf_write(pc, tag, AGP_I965_IFPADDR+4, hi); 732 pci_conf_write(pc, tag, AGP_I965_IFPADDR, lo); 733 } 734 } 735 736 /* Success! */ 737 return 0; 738 } 739 740 static void 741 agp_i810_teardown_chipset_flush_page(struct agp_softc *sc) 742 { 743 struct agp_i810_softc *const isc = sc->as_chipc; 744 745 if (isc->flush_addr) { 746 /* If we allocated a page, clear it. */ 747 if (isc->chiptype == CHIP_I915) { 748 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR, 749 0); 750 } else { 751 pci_conf_write(sc->as_pc, sc->as_tag, 752 AGP_I965_IFPADDR, 0); 753 pci_conf_write(sc->as_pc, sc->as_tag, 754 AGP_I965_IFPADDR + 4, 0); 755 } 756 isc->flush_addr = 0; 757 bus_space_free(isc->flush_bst, isc->flush_bsh, PAGE_SIZE); 758 } else { 759 /* Otherwise, just unmap the pre-allocated page. */ 760 bus_space_unmap(isc->flush_bst, isc->flush_bsh, PAGE_SIZE); 761 } 762 } 763 764 /* 765 * XXX horrible hack to allow drm code to use our mapping 766 * of VGA chip registers 767 */ 768 int 769 agp_i810_borrow(bus_addr_t base, bus_size_t size, bus_space_handle_t *hdlp) 770 { 771 772 if (agp_i810_vga_regbase == 0) 773 return 0; 774 if (base < agp_i810_vga_regbase) 775 return 0; 776 if (agp_i810_vga_regsize < size) 777 return 0; 778 if ((base - agp_i810_vga_regbase) > (agp_i810_vga_regsize - size)) 779 return 0; 780 if (bus_space_subregion(agp_i810_vga_bst, agp_i810_vga_bsh, 781 (base - agp_i810_vga_regbase), (agp_i810_vga_regsize - size), 782 hdlp)) 783 return 0; 784 return 1; 785 } 786 787 static int 788 agp_i810_init(struct agp_softc *sc) 789 { 790 struct agp_i810_softc *isc; 791 int error; 792 793 isc = sc->as_chipc; 794 795 if (isc->chiptype == CHIP_I810) { 796 struct agp_gatt *gatt; 797 void *virtual; 798 int dummyseg; 799 800 /* Some i810s have on-chip memory called dcache */ 801 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 802 isc->dcache_size = 4 * 1024 * 1024; 803 else 804 isc->dcache_size = 0; 805 806 /* According to the specs the gatt on the i810 must be 64k */ 807 isc->gtt_size = 64 * 1024; 808 gatt = malloc(sizeof(*gatt), M_AGP, M_WAITOK); 809 gatt->ag_entries = isc->gtt_size / sizeof(uint32_t); 810 error = agp_alloc_dmamem(sc->as_dmat, isc->gtt_size, 811 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical, 812 &gatt->ag_dmaseg, 1, &dummyseg); 813 if (error) { 814 aprint_error_dev(sc->as_dev, 815 "can't allocate memory for GTT: %d\n", error); 816 free(gatt, M_AGP); 817 goto fail0; 818 } 819 820 gatt->ag_virtual = (uint32_t *)virtual; 821 gatt->ag_size = gatt->ag_entries * sizeof(uint32_t); 822 memset(gatt->ag_virtual, 0, gatt->ag_size); 823 agp_flush_cache(); 824 825 /* Install the GATT. */ 826 isc->pgtblctl = gatt->ag_physical | 1; 827 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 828 isc->gatt = gatt; 829 } else if (isc->chiptype == CHIP_I830) { 830 /* The i830 automatically initializes the 128k gatt on boot. */ 831 /* XXX [citation needed] */ 832 pcireg_t reg; 833 u_int16_t gcc1; 834 835 isc->gtt_size = 128 * 1024; 836 837 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 838 gcc1 = (u_int16_t)(reg >> 16); 839 switch (gcc1 & AGP_I830_GCC1_GMS) { 840 case AGP_I830_GCC1_GMS_STOLEN_512: 841 isc->stolen = (512 - 132) * 1024 / 4096; 842 break; 843 case AGP_I830_GCC1_GMS_STOLEN_1024: 844 isc->stolen = (1024 - 132) * 1024 / 4096; 845 break; 846 case AGP_I830_GCC1_GMS_STOLEN_8192: 847 isc->stolen = (8192 - 132) * 1024 / 4096; 848 break; 849 default: 850 isc->stolen = 0; 851 aprint_error_dev(sc->as_dev, 852 "unknown memory configuration, disabling\n"); 853 error = ENXIO; 854 goto fail0; 855 } 856 857 if (isc->stolen > 0) { 858 aprint_normal_dev(sc->as_dev, 859 "detected %dk stolen memory\n", 860 isc->stolen * 4); 861 } 862 863 /* GATT address is already in there, make sure it's enabled */ 864 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 865 isc->pgtblctl |= 1; 866 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 867 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 868 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 || 869 isc->chiptype == CHIP_PINEVIEW || 870 isc->chiptype == CHIP_G4X) { 871 pcireg_t reg; 872 u_int32_t gtt_size, stolen; /* XXX kilobytes */ 873 u_int16_t gcc1; 874 875 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1); 876 gcc1 = (u_int16_t)(reg >> 16); 877 878 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 879 880 /* Stolen memory is set up at the beginning of the aperture by 881 * the BIOS, consisting of the GATT followed by 4kb for the 882 * BIOS display. 883 */ 884 switch (isc->chiptype) { 885 case CHIP_I855: 886 gtt_size = 128; 887 break; 888 case CHIP_I915: 889 gtt_size = 256; 890 break; 891 case CHIP_I965: 892 switch (isc->pgtblctl & AGP_I810_PGTBL_SIZE_MASK) { 893 case AGP_I810_PGTBL_SIZE_128KB: 894 case AGP_I810_PGTBL_SIZE_512KB: 895 gtt_size = 512; 896 break; 897 case AGP_I965_PGTBL_SIZE_1MB: 898 gtt_size = 1024; 899 break; 900 case AGP_I965_PGTBL_SIZE_2MB: 901 gtt_size = 2048; 902 break; 903 case AGP_I965_PGTBL_SIZE_1_5MB: 904 gtt_size = 1024 + 512; 905 break; 906 default: 907 aprint_error_dev(sc->as_dev, 908 "bad PGTBL size\n"); 909 error = ENXIO; 910 goto fail0; 911 } 912 break; 913 case CHIP_G33: 914 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 915 case AGP_G33_PGTBL_SIZE_1M: 916 gtt_size = 1024; 917 break; 918 case AGP_G33_PGTBL_SIZE_2M: 919 gtt_size = 2048; 920 break; 921 default: 922 aprint_error_dev(sc->as_dev, 923 "bad PGTBL size\n"); 924 error = ENXIO; 925 goto fail0; 926 } 927 break; 928 case CHIP_PINEVIEW: 929 switch (gcc1 & AGP_PINEVIEW_PGTBL_SIZE_MASK) { 930 case AGP_PINEVIEW_PGTBL_SIZE_1M: 931 gtt_size = 1024; 932 break; 933 default: 934 aprint_error_dev(sc->as_dev, 935 "bad PGTBL size\n"); 936 error = ENXIO; 937 goto fail0; 938 } 939 break; 940 case CHIP_G4X: 941 switch (isc->pgtblctl & AGP_G4X_PGTBL_SIZE_MASK) { 942 case AGP_G4X_PGTBL_SIZE_512K: 943 gtt_size = 512; 944 break; 945 case AGP_G4X_PGTBL_SIZE_256K: 946 gtt_size = 256; 947 break; 948 case AGP_G4X_PGTBL_SIZE_128K: 949 gtt_size = 128; 950 break; 951 case AGP_G4X_PGTBL_SIZE_1M: 952 gtt_size = 1*1024; 953 break; 954 case AGP_G4X_PGTBL_SIZE_2M: 955 gtt_size = 2*1024; 956 break; 957 case AGP_G4X_PGTBL_SIZE_1_5M: 958 gtt_size = 1*1024 + 512; 959 break; 960 default: 961 aprint_error_dev(sc->as_dev, 962 "bad PGTBL size\n"); 963 error = ENXIO; 964 goto fail0; 965 } 966 break; 967 default: 968 panic("impossible chiptype %d", isc->chiptype); 969 } 970 971 /* 972 * XXX If I'm reading the datasheets right, this stolen 973 * memory detection logic is totally wrong. 974 */ 975 switch (gcc1 & AGP_I855_GCC1_GMS) { 976 case AGP_I855_GCC1_GMS_STOLEN_1M: 977 stolen = 1024; 978 break; 979 case AGP_I855_GCC1_GMS_STOLEN_4M: 980 stolen = 4 * 1024; 981 break; 982 case AGP_I855_GCC1_GMS_STOLEN_8M: 983 stolen = 8 * 1024; 984 break; 985 case AGP_I855_GCC1_GMS_STOLEN_16M: 986 stolen = 16 * 1024; 987 break; 988 case AGP_I855_GCC1_GMS_STOLEN_32M: 989 stolen = 32 * 1024; 990 break; 991 case AGP_I915_GCC1_GMS_STOLEN_48M: 992 stolen = 48 * 1024; 993 break; 994 case AGP_I915_GCC1_GMS_STOLEN_64M: 995 stolen = 64 * 1024; 996 break; 997 case AGP_G33_GCC1_GMS_STOLEN_128M: 998 stolen = 128 * 1024; 999 break; 1000 case AGP_G33_GCC1_GMS_STOLEN_256M: 1001 stolen = 256 * 1024; 1002 break; 1003 case AGP_G4X_GCC1_GMS_STOLEN_96M: 1004 stolen = 96 * 1024; 1005 break; 1006 case AGP_G4X_GCC1_GMS_STOLEN_160M: 1007 stolen = 160 * 1024; 1008 break; 1009 case AGP_G4X_GCC1_GMS_STOLEN_224M: 1010 stolen = 224 * 1024; 1011 break; 1012 case AGP_G4X_GCC1_GMS_STOLEN_352M: 1013 stolen = 352 * 1024; 1014 break; 1015 default: 1016 aprint_error_dev(sc->as_dev, 1017 "unknown memory configuration, disabling\n"); 1018 error = ENXIO; 1019 goto fail0; 1020 } 1021 1022 switch (gcc1 & AGP_I855_GCC1_GMS) { 1023 case AGP_I915_GCC1_GMS_STOLEN_48M: 1024 case AGP_I915_GCC1_GMS_STOLEN_64M: 1025 if (isc->chiptype != CHIP_I915 && 1026 isc->chiptype != CHIP_I965 && 1027 isc->chiptype != CHIP_G33 && 1028 isc->chiptype != CHIP_PINEVIEW && 1029 isc->chiptype != CHIP_G4X) 1030 stolen = 0; 1031 break; 1032 case AGP_G33_GCC1_GMS_STOLEN_128M: 1033 case AGP_G33_GCC1_GMS_STOLEN_256M: 1034 if (isc->chiptype != CHIP_I965 && 1035 isc->chiptype != CHIP_G33 && 1036 isc->chiptype != CHIP_PINEVIEW && 1037 isc->chiptype != CHIP_G4X) 1038 stolen = 0; 1039 break; 1040 case AGP_G4X_GCC1_GMS_STOLEN_96M: 1041 case AGP_G4X_GCC1_GMS_STOLEN_160M: 1042 case AGP_G4X_GCC1_GMS_STOLEN_224M: 1043 case AGP_G4X_GCC1_GMS_STOLEN_352M: 1044 if (isc->chiptype != CHIP_I965 && 1045 isc->chiptype != CHIP_G4X) 1046 stolen = 0; 1047 break; 1048 } 1049 1050 isc->gtt_size = gtt_size * 1024; 1051 1052 /* BIOS space */ 1053 /* XXX [citation needed] */ 1054 gtt_size += 4; 1055 1056 /* XXX [citation needed] for this subtraction */ 1057 isc->stolen = (stolen - gtt_size) * 1024 / 4096; 1058 1059 if (isc->stolen > 0) { 1060 aprint_normal_dev(sc->as_dev, 1061 "detected %dk stolen memory\n", 1062 isc->stolen * 4); 1063 } 1064 1065 /* GATT address is already in there, make sure it's enabled */ 1066 isc->pgtblctl |= 1; 1067 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 1068 } 1069 1070 /* 1071 * Make sure the chipset can see everything. 1072 */ 1073 agp_flush_cache(); 1074 1075 /* 1076 * Publish what we found for kludgey drivers (I'm looking at 1077 * you, drm). 1078 */ 1079 if (agp_i810_sc == NULL) 1080 agp_i810_sc = sc; 1081 else 1082 aprint_error_dev(sc->as_dev, "agp already attached\n"); 1083 1084 /* Success! */ 1085 return 0; 1086 1087 fail0: KASSERT(error); 1088 return error; 1089 } 1090 1091 #if 0 1092 static int 1093 agp_i810_detach(struct agp_softc *sc) 1094 { 1095 int error; 1096 struct agp_i810_softc *isc = sc->as_chipc; 1097 1098 error = agp_generic_detach(sc); 1099 if (error) 1100 return error; 1101 1102 switch (isc->chiptype) { 1103 case CHIP_I915: 1104 case CHIP_I965: 1105 case CHIP_G33: 1106 case CHIP_PINEVIEW: 1107 case CHIP_G4X: 1108 agp_i810_teardown_chipset_flush_page(sc); 1109 break; 1110 } 1111 1112 /* Clear the GATT base. */ 1113 if (sc->chiptype == CHIP_I810) { 1114 WRITE4(AGP_I810_PGTBL_CTL, 0); 1115 } else { 1116 unsigned int pgtblctl; 1117 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 1118 pgtblctl &= ~1; 1119 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 1120 } 1121 1122 if (sc->chiptype == CHIP_I810) { 1123 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap, 1124 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 1125 free(isc->gatt, M_AGP); 1126 } 1127 1128 return 0; 1129 } 1130 #endif 1131 1132 static u_int32_t 1133 agp_i810_get_aperture(struct agp_softc *sc) 1134 { 1135 struct agp_i810_softc *isc = sc->as_chipc; 1136 pcireg_t reg; 1137 u_int32_t size; 1138 u_int16_t miscc, gcc1; 1139 1140 size = 0; 1141 1142 switch (isc->chiptype) { 1143 case CHIP_I810: 1144 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 1145 miscc = (u_int16_t)(reg >> 16); 1146 if ((miscc & AGP_I810_MISCC_WINSIZE) == 1147 AGP_I810_MISCC_WINSIZE_32) 1148 size = 32 * 1024 * 1024; 1149 else 1150 size = 64 * 1024 * 1024; 1151 break; 1152 case CHIP_I830: 1153 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 1154 gcc1 = (u_int16_t)(reg >> 16); 1155 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 1156 size = 64 * 1024 * 1024; 1157 else 1158 size = 128 * 1024 * 1024; 1159 break; 1160 case CHIP_I855: 1161 size = 128 * 1024 * 1024; 1162 break; 1163 case CHIP_I915: 1164 case CHIP_G33: 1165 case CHIP_PINEVIEW: 1166 case CHIP_G4X: 1167 size = sc->as_apsize; 1168 break; 1169 case CHIP_I965: 1170 size = 512 * 1024 * 1024; 1171 break; 1172 default: 1173 aprint_error(": Unknown chipset\n"); 1174 } 1175 1176 return size; 1177 } 1178 1179 static int 1180 agp_i810_set_aperture(struct agp_softc *sc __unused, 1181 uint32_t aperture __unused) 1182 { 1183 1184 return ENOSYS; 1185 } 1186 1187 static int 1188 agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 1189 { 1190 struct agp_i810_softc *isc = sc->as_chipc; 1191 1192 if (offset < 0 || offset >= ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) { 1193 DPRINTF(sc, "failed" 1194 ": offset 0x%"PRIxMAX", shift %u, entries %"PRIuMAX"\n", 1195 (uintmax_t)offset, 1196 (unsigned)AGP_PAGE_SHIFT, 1197 (uintmax_t)isc->gtt_size/4); 1198 return EINVAL; 1199 } 1200 1201 if (isc->chiptype != CHIP_I810) { 1202 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1203 DPRINTF(sc, "trying to bind into stolen memory\n"); 1204 return EINVAL; 1205 } 1206 } 1207 1208 return agp_i810_write_gtt_entry(isc, offset, physical, 1209 AGP_I810_GTT_VALID); 1210 } 1211 1212 static int 1213 agp_i810_unbind_page(struct agp_softc *sc, off_t offset) 1214 { 1215 struct agp_i810_softc *isc = sc->as_chipc; 1216 1217 if (offset < 0 || offset >= ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) 1218 return EINVAL; 1219 1220 if (isc->chiptype != CHIP_I810 ) { 1221 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1222 DPRINTF(sc, "trying to unbind from stolen memory\n"); 1223 return EINVAL; 1224 } 1225 } 1226 1227 return agp_i810_write_gtt_entry(isc, offset, 0, 0); 1228 } 1229 1230 /* 1231 * Writing via memory mapped registers already flushes all TLBs. 1232 */ 1233 static void 1234 agp_i810_flush_tlb(struct agp_softc *sc) 1235 { 1236 } 1237 1238 static int 1239 agp_i810_enable(struct agp_softc *sc, u_int32_t mode) 1240 { 1241 1242 return 0; 1243 } 1244 1245 #define AGP_I810_MEMTYPE_MAIN 0 1246 #define AGP_I810_MEMTYPE_DCACHE 1 1247 #define AGP_I810_MEMTYPE_HWCURSOR 2 1248 1249 static struct agp_memory * 1250 agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size) 1251 { 1252 struct agp_i810_softc *isc = sc->as_chipc; 1253 struct agp_memory *mem; 1254 int error; 1255 1256 DPRINTF(sc, "AGP: alloc(%d, 0x%"PRIxMAX")\n", type, (uintmax_t)size); 1257 1258 if (size <= 0) 1259 return NULL; 1260 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 1261 return NULL; 1262 KASSERT(sc->as_allocated <= sc->as_maxmem); 1263 if (size > (sc->as_maxmem - sc->as_allocated)) 1264 return NULL; 1265 if (size > ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) 1266 return NULL; 1267 1268 switch (type) { 1269 case AGP_I810_MEMTYPE_MAIN: 1270 break; 1271 case AGP_I810_MEMTYPE_DCACHE: 1272 if (isc->chiptype != CHIP_I810) 1273 return NULL; 1274 if (size != isc->dcache_size) 1275 return NULL; 1276 break; 1277 case AGP_I810_MEMTYPE_HWCURSOR: 1278 if ((size != AGP_PAGE_SIZE) && 1279 (size != AGP_PAGE_SIZE*4)) 1280 return NULL; 1281 break; 1282 default: 1283 return NULL; 1284 } 1285 1286 mem = malloc(sizeof(*mem), M_AGP, M_WAITOK|M_ZERO); 1287 if (mem == NULL) 1288 goto fail0; 1289 mem->am_id = sc->as_nextid++; 1290 mem->am_size = size; 1291 mem->am_type = type; 1292 1293 switch (type) { 1294 case AGP_I810_MEMTYPE_MAIN: 1295 error = bus_dmamap_create(sc->as_dmat, size, 1296 (size >> AGP_PAGE_SHIFT) + 1, size, 0, BUS_DMA_WAITOK, 1297 &mem->am_dmamap); 1298 if (error) 1299 goto fail1; 1300 break; 1301 case AGP_I810_MEMTYPE_DCACHE: 1302 break; 1303 case AGP_I810_MEMTYPE_HWCURSOR: 1304 mem->am_dmaseg = malloc(sizeof(*mem->am_dmaseg), M_AGP, 1305 M_WAITOK); 1306 error = agp_alloc_dmamem(sc->as_dmat, size, 0, &mem->am_dmamap, 1307 &mem->am_virtual, &mem->am_physical, mem->am_dmaseg, 1, 1308 &mem->am_nseg); 1309 if (error) { 1310 free(mem->am_dmaseg, M_AGP); 1311 goto fail1; 1312 } 1313 (void)memset(mem->am_virtual, 0, size); 1314 break; 1315 default: 1316 panic("invalid agp memory type: %d", type); 1317 } 1318 1319 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link); 1320 sc->as_allocated += size; 1321 1322 return mem; 1323 1324 fail1: free(mem, M_AGP); 1325 fail0: return NULL; 1326 } 1327 1328 static int 1329 agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem) 1330 { 1331 1332 if (mem->am_is_bound) 1333 return EBUSY; 1334 1335 switch (mem->am_type) { 1336 case AGP_I810_MEMTYPE_MAIN: 1337 bus_dmamap_destroy(sc->as_dmat, mem->am_dmamap); 1338 break; 1339 case AGP_I810_MEMTYPE_DCACHE: 1340 break; 1341 case AGP_I810_MEMTYPE_HWCURSOR: 1342 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap, 1343 mem->am_virtual, mem->am_dmaseg, mem->am_nseg); 1344 free(mem->am_dmaseg, M_AGP); 1345 break; 1346 default: 1347 panic("invalid agp i810 memory type: %d", mem->am_type); 1348 } 1349 1350 sc->as_allocated -= mem->am_size; 1351 TAILQ_REMOVE(&sc->as_memory, mem, am_link); 1352 free(mem, M_AGP); 1353 1354 return 0; 1355 } 1356 1357 static int 1358 agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem, 1359 off_t offset) 1360 { 1361 struct agp_i810_softc *isc = sc->as_chipc; 1362 uint32_t pgtblctl; 1363 int error; 1364 1365 if (mem->am_is_bound) 1366 return EINVAL; 1367 1368 /* 1369 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 1370 * X server for mysterious reasons which leads to crashes if we write 1371 * to the GTT through the MMIO window. 1372 * Until the issue is solved, simply restore it. 1373 */ 1374 pgtblctl = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL); 1375 if (pgtblctl != isc->pgtblctl) { 1376 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%"PRIx32 1377 " - fixing\n", pgtblctl); 1378 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 1379 isc->pgtblctl); 1380 } 1381 1382 switch (mem->am_type) { 1383 case AGP_I810_MEMTYPE_MAIN: 1384 return agp_generic_bind_memory_bounded(sc, mem, offset, 1385 0, (isc->gtt_size/4) << AGP_PAGE_SHIFT); 1386 case AGP_I810_MEMTYPE_DCACHE: 1387 error = agp_i810_bind_memory_dcache(sc, mem, offset); 1388 break; 1389 case AGP_I810_MEMTYPE_HWCURSOR: 1390 error = agp_i810_bind_memory_hwcursor(sc, mem, offset); 1391 break; 1392 default: 1393 panic("invalid agp i810 memory type: %d", mem->am_type); 1394 } 1395 if (error) 1396 return error; 1397 1398 /* Success! */ 1399 mem->am_is_bound = 1; 1400 return 0; 1401 } 1402 1403 static int 1404 agp_i810_bind_memory_dcache(struct agp_softc *sc, struct agp_memory *mem, 1405 off_t offset) 1406 { 1407 struct agp_i810_softc *const isc __diagused = sc->as_chipc; 1408 uint32_t i, j; 1409 int error; 1410 1411 KASSERT(isc->chiptype == CHIP_I810); 1412 1413 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0); 1414 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 1415 error = agp_i810_write_gtt_entry(isc, offset + i, 1416 i, AGP_I810_GTT_VALID | AGP_I810_GTT_I810_DCACHE); 1417 if (error) 1418 goto fail0; 1419 } 1420 1421 /* Success! */ 1422 mem->am_offset = offset; 1423 return 0; 1424 1425 fail0: for (j = 0; j < i; j += AGP_PAGE_SIZE) 1426 (void)agp_i810_unbind_page(sc, offset + j); 1427 return error; 1428 } 1429 1430 static int 1431 agp_i810_bind_memory_hwcursor(struct agp_softc *sc, struct agp_memory *mem, 1432 off_t offset) 1433 { 1434 const bus_addr_t pa = mem->am_physical; 1435 uint32_t i, j; 1436 int error; 1437 1438 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0); 1439 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 1440 error = agp_i810_bind_page(sc, offset + i, pa + i); 1441 if (error) 1442 goto fail0; 1443 } 1444 1445 /* Success! */ 1446 mem->am_offset = offset; 1447 return 0; 1448 1449 fail0: for (j = 0; j < i; j += AGP_PAGE_SIZE) 1450 (void)agp_i810_unbind_page(sc, offset + j); 1451 return error; 1452 } 1453 1454 static int 1455 agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem) 1456 { 1457 struct agp_i810_softc *isc __diagused = sc->as_chipc; 1458 u_int32_t i; 1459 1460 if (!mem->am_is_bound) 1461 return EINVAL; 1462 1463 switch (mem->am_type) { 1464 case AGP_I810_MEMTYPE_MAIN: 1465 return agp_generic_unbind_memory(sc, mem); 1466 case AGP_I810_MEMTYPE_DCACHE: 1467 KASSERT(isc->chiptype == CHIP_I810); 1468 /* FALLTHROUGH */ 1469 case AGP_I810_MEMTYPE_HWCURSOR: 1470 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1471 (void)agp_i810_unbind_page(sc, mem->am_offset + i); 1472 mem->am_offset = 0; 1473 break; 1474 default: 1475 panic("invalid agp i810 memory type: %d", mem->am_type); 1476 } 1477 1478 mem->am_is_bound = 0; 1479 return 0; 1480 } 1481 1482 void 1483 agp_i810_reset(struct agp_i810_softc *isc) 1484 { 1485 1486 /* Restore the page table control register. */ 1487 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 1488 isc->pgtblctl); 1489 1490 agp_flush_cache(); 1491 } 1492 1493 static bool 1494 agp_i810_resume(device_t dv, const pmf_qual_t *qual) 1495 { 1496 struct agp_softc *sc = device_private(dv); 1497 struct agp_i810_softc *isc = sc->as_chipc; 1498 1499 agp_i810_reset(isc); 1500 1501 return true; 1502 } 1503
Indexes created Tue Oct 07 21:09:53 GMT 2025