agp_i810.c revision 1.26.2.7
1 /* $NetBSD: agp_i810.c,v 1.26.2.7 2008/01/21 09:43:33 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/pci/agp_i810.c,v 1.4 2001/07/05 21:28:47 jhb Exp $ 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.26.2.7 2008/01/21 09:43:33 yamt Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/proc.h> 40 #include <sys/device.h> 41 #include <sys/conf.h> 42 43 #include <uvm/uvm_extern.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/agpvar.h> 49 #include <dev/pci/agpreg.h> 50 51 #include <sys/agpio.h> 52 53 #include <sys/bus.h> 54 55 #include "agp_intel.h" 56 57 #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off) 58 #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off) 59 #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v) 60 #define WRITEGTT(off, v) \ 61 do { \ 62 if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33) { \ 63 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, \ 64 (u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4, \ 65 (v)); \ 66 } else if (isc->chiptype == CHIP_I965) { \ 67 WRITE4(AGP_I965_GTT + \ 68 (u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4, \ 69 (v)); \ 70 } else { \ 71 WRITE4(AGP_I810_GTT + \ 72 (u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4, \ 73 (v)); \ 74 } \ 75 } while (0) 76 77 #define CHIP_I810 0 /* i810/i815 */ 78 #define CHIP_I830 1 /* 830M/845G */ 79 #define CHIP_I855 2 /* 852GM/855GM/865G */ 80 #define CHIP_I915 3 /* 915G/915GM/945G/945GM */ 81 #define CHIP_I965 4 /* 965Q/965PM */ 82 #define CHIP_G33 5 /* G33/Q33/Q35 */ 83 84 struct agp_i810_softc { 85 u_int32_t initial_aperture; /* aperture size at startup */ 86 struct agp_gatt *gatt; 87 int chiptype; /* i810-like or i830 */ 88 u_int32_t dcache_size; /* i810 only */ 89 u_int32_t stolen; /* number of i830/845 gtt entries 90 for stolen memory */ 91 bus_space_tag_t bst; /* register bus_space tag */ 92 bus_space_handle_t bsh; /* register bus_space handle */ 93 bus_space_tag_t gtt_bst; /* GTT bus_space tag */ 94 bus_space_handle_t gtt_bsh; /* GTT bus_space handle */ 95 struct pci_attach_args vga_pa; 96 97 u_int32_t pgtblctl; 98 }; 99 100 static u_int32_t agp_i810_get_aperture(struct agp_softc *); 101 static int agp_i810_set_aperture(struct agp_softc *, u_int32_t); 102 static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t); 103 static int agp_i810_unbind_page(struct agp_softc *, off_t); 104 static void agp_i810_flush_tlb(struct agp_softc *); 105 static int agp_i810_enable(struct agp_softc *, u_int32_t mode); 106 static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int, 107 vsize_t); 108 static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *); 109 static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, off_t); 110 static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *); 111 112 static bool agp_i810_resume(device_t); 113 static int agp_i810_init(struct agp_softc *); 114 115 static int agp_i810_init(struct agp_softc *); 116 117 static struct agp_methods agp_i810_methods = { 118 agp_i810_get_aperture, 119 agp_i810_set_aperture, 120 agp_i810_bind_page, 121 agp_i810_unbind_page, 122 agp_i810_flush_tlb, 123 agp_i810_enable, 124 agp_i810_alloc_memory, 125 agp_i810_free_memory, 126 agp_i810_bind_memory, 127 agp_i810_unbind_memory, 128 }; 129 130 /* XXXthorpej -- duplicated code (see arch/i386/pci/pchb.c) */ 131 static int 132 agp_i810_vgamatch(struct pci_attach_args *pa) 133 { 134 135 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 136 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 137 return (0); 138 139 switch (PCI_PRODUCT(pa->pa_id)) { 140 case PCI_PRODUCT_INTEL_82810_GC: 141 case PCI_PRODUCT_INTEL_82810_DC100_GC: 142 case PCI_PRODUCT_INTEL_82810E_GC: 143 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 144 case PCI_PRODUCT_INTEL_82830MP_IV: 145 case PCI_PRODUCT_INTEL_82845G_IGD: 146 case PCI_PRODUCT_INTEL_82855GM_IGD: 147 case PCI_PRODUCT_INTEL_82865_IGD: 148 case PCI_PRODUCT_INTEL_82915G_IGD: 149 case PCI_PRODUCT_INTEL_82915GM_IGD: 150 case PCI_PRODUCT_INTEL_82945P_IGD: 151 case PCI_PRODUCT_INTEL_82945GM_IGD: 152 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 153 case PCI_PRODUCT_INTEL_82965Q_IGD: 154 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 155 case PCI_PRODUCT_INTEL_82965PM_IGD: 156 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 157 case PCI_PRODUCT_INTEL_82G33_IGD: 158 case PCI_PRODUCT_INTEL_82G33_IGD_1: 159 case PCI_PRODUCT_INTEL_82965G_IGD: 160 case PCI_PRODUCT_INTEL_82965G_IGD_1: 161 case PCI_PRODUCT_INTEL_82Q35_IGD: 162 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 163 case PCI_PRODUCT_INTEL_82Q33_IGD: 164 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 165 return (1); 166 } 167 168 return (0); 169 } 170 171 static int 172 agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg) 173 { 174 /* 175 * Find the aperture. Don't map it (yet), this would 176 * eat KVA. 177 */ 178 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 179 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize, 180 &sc->as_apflags) != 0) 181 return ENXIO; 182 183 sc->as_apt = pa->pa_memt; 184 185 return 0; 186 } 187 188 int 189 agp_i810_attach(struct device *parent, struct device *self, void *aux) 190 { 191 struct agp_softc *sc = (void *)self; 192 struct agp_i810_softc *isc; 193 struct agp_gatt *gatt; 194 int error, apbase; 195 bus_size_t mmadrsize; 196 197 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 198 if (isc == NULL) { 199 aprint_error(": can't allocate chipset-specific softc\n"); 200 return ENOMEM; 201 } 202 sc->as_chipc = isc; 203 sc->as_methods = &agp_i810_methods; 204 205 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) { 206 #if NAGP_INTEL > 0 207 const struct pci_attach_args *pa = aux; 208 209 switch (PCI_PRODUCT(pa->pa_id)) { 210 case PCI_PRODUCT_INTEL_82840_HB: 211 case PCI_PRODUCT_INTEL_82865_HB: 212 case PCI_PRODUCT_INTEL_82845G_DRAM: 213 case PCI_PRODUCT_INTEL_82815_FULL_HUB: 214 return agp_intel_attach(parent, self, aux); 215 } 216 #endif 217 aprint_error(": can't find internal VGA device config space\n"); 218 free(isc, M_AGP); 219 return ENOENT; 220 } 221 222 /* XXXfvdl */ 223 sc->as_dmat = isc->vga_pa.pa_dmat; 224 225 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 226 case PCI_PRODUCT_INTEL_82810_GC: 227 case PCI_PRODUCT_INTEL_82810_DC100_GC: 228 case PCI_PRODUCT_INTEL_82810E_GC: 229 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 230 isc->chiptype = CHIP_I810; 231 break; 232 case PCI_PRODUCT_INTEL_82830MP_IV: 233 case PCI_PRODUCT_INTEL_82845G_IGD: 234 isc->chiptype = CHIP_I830; 235 break; 236 case PCI_PRODUCT_INTEL_82855GM_IGD: 237 case PCI_PRODUCT_INTEL_82865_IGD: 238 isc->chiptype = CHIP_I855; 239 break; 240 case PCI_PRODUCT_INTEL_82915G_IGD: 241 case PCI_PRODUCT_INTEL_82915GM_IGD: 242 case PCI_PRODUCT_INTEL_82945P_IGD: 243 case PCI_PRODUCT_INTEL_82945GM_IGD: 244 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 245 isc->chiptype = CHIP_I915; 246 break; 247 case PCI_PRODUCT_INTEL_82965Q_IGD: 248 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 249 case PCI_PRODUCT_INTEL_82965PM_IGD: 250 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 251 case PCI_PRODUCT_INTEL_82965G_IGD: 252 case PCI_PRODUCT_INTEL_82965G_IGD_1: 253 isc->chiptype = CHIP_I965; 254 break; 255 case PCI_PRODUCT_INTEL_82Q35_IGD: 256 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 257 case PCI_PRODUCT_INTEL_82G33_IGD: 258 case PCI_PRODUCT_INTEL_82G33_IGD_1: 259 case PCI_PRODUCT_INTEL_82Q33_IGD: 260 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 261 isc->chiptype = CHIP_G33; 262 break; 263 } 264 265 switch (isc->chiptype) { 266 case CHIP_I915: 267 case CHIP_G33: 268 apbase = AGP_I915_GMADR; 269 break; 270 default: 271 apbase = AGP_I810_GMADR; 272 break; 273 } 274 if (isc->chiptype == CHIP_I965) { 275 error = agp_i965_map_aperture(&isc->vga_pa, sc, AGP_I965_GMADR); 276 } else { 277 error = agp_map_aperture(&isc->vga_pa, sc, apbase); 278 } 279 if (error != 0) { 280 aprint_error(": can't map aperture\n"); 281 free(isc, M_AGP); 282 return error; 283 } 284 285 if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33) { 286 error = pci_mapreg_map(&isc->vga_pa, AGP_I915_MMADR, 287 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 288 NULL, &mmadrsize); 289 if (error != 0) { 290 aprint_error(": can't map mmadr registers\n"); 291 agp_generic_detach(sc); 292 return error; 293 } 294 error = pci_mapreg_map(&isc->vga_pa, AGP_I915_GTTADR, 295 PCI_MAPREG_TYPE_MEM, 0, &isc->gtt_bst, &isc->gtt_bsh, 296 NULL, NULL); 297 if (error != 0) { 298 aprint_error(": can't map gttadr registers\n"); 299 /* XXX we should release mmadr here */ 300 agp_generic_detach(sc); 301 return error; 302 } 303 } else if (isc->chiptype == CHIP_I965) { 304 error = pci_mapreg_map(&isc->vga_pa, AGP_I965_MMADR, 305 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 306 NULL, &mmadrsize); 307 if (error != 0) { 308 aprint_error(": can't map mmadr registers\n"); 309 agp_generic_detach(sc); 310 return error; 311 } 312 } else { 313 error = pci_mapreg_map(&isc->vga_pa, AGP_I810_MMADR, 314 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 315 NULL, &mmadrsize); 316 if (error != 0) { 317 aprint_error(": can't map mmadr registers\n"); 318 agp_generic_detach(sc); 319 return error; 320 } 321 } 322 323 isc->initial_aperture = AGP_GET_APERTURE(sc); 324 325 gatt = malloc(sizeof(struct agp_gatt), M_AGP, M_NOWAIT); 326 if (!gatt) { 327 agp_generic_detach(sc); 328 return ENOMEM; 329 } 330 isc->gatt = gatt; 331 332 gatt->ag_entries = AGP_GET_APERTURE(sc) >> AGP_PAGE_SHIFT; 333 334 if (!pmf_device_register(self, NULL, agp_i810_resume)) 335 aprint_error_dev(self, "couldn't establish power handler\n"); 336 337 return agp_i810_init(sc); 338 } 339 340 static int agp_i810_init(struct agp_softc *sc) 341 { 342 struct agp_i810_softc *isc; 343 struct agp_gatt *gatt; 344 345 isc = sc->as_chipc; 346 gatt = isc->gatt; 347 348 if (isc->chiptype == CHIP_I810) { 349 void *virtual; 350 int dummyseg; 351 352 /* Some i810s have on-chip memory called dcache */ 353 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 354 isc->dcache_size = 4 * 1024 * 1024; 355 else 356 isc->dcache_size = 0; 357 358 /* According to the specs the gatt on the i810 must be 64k */ 359 if (agp_alloc_dmamem(sc->as_dmat, 64 * 1024, 360 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical, 361 &gatt->ag_dmaseg, 1, &dummyseg) != 0) { 362 free(gatt, M_AGP); 363 agp_generic_detach(sc); 364 return ENOMEM; 365 } 366 gatt->ag_virtual = (uint32_t *)virtual; 367 gatt->ag_size = gatt->ag_entries * sizeof(u_int32_t); 368 memset(gatt->ag_virtual, 0, gatt->ag_size); 369 370 agp_flush_cache(); 371 /* Install the GATT. */ 372 WRITE4(AGP_I810_PGTBL_CTL, gatt->ag_physical | 1); 373 } else if (isc->chiptype == CHIP_I830) { 374 /* The i830 automatically initializes the 128k gatt on boot. */ 375 pcireg_t reg; 376 u_int32_t pgtblctl; 377 u_int16_t gcc1; 378 379 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 380 gcc1 = (u_int16_t)(reg >> 16); 381 switch (gcc1 & AGP_I830_GCC1_GMS) { 382 case AGP_I830_GCC1_GMS_STOLEN_512: 383 isc->stolen = (512 - 132) * 1024 / 4096; 384 break; 385 case AGP_I830_GCC1_GMS_STOLEN_1024: 386 isc->stolen = (1024 - 132) * 1024 / 4096; 387 break; 388 case AGP_I830_GCC1_GMS_STOLEN_8192: 389 isc->stolen = (8192 - 132) * 1024 / 4096; 390 break; 391 default: 392 isc->stolen = 0; 393 aprint_error( 394 ": unknown memory configuration, disabling\n"); 395 agp_generic_detach(sc); 396 return EINVAL; 397 } 398 399 if (isc->stolen > 0) { 400 aprint_error(": detected %dk stolen memory\n%s", 401 isc->stolen * 4, sc->as_dev.dv_xname); 402 } 403 404 /* GATT address is already in there, make sure it's enabled */ 405 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 406 pgtblctl |= 1; 407 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 408 409 gatt->ag_physical = pgtblctl & ~1; 410 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 411 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33) { 412 pcireg_t reg; 413 u_int32_t pgtblctl, stolen; 414 u_int16_t gcc1; 415 416 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1); 417 gcc1 = (u_int16_t)(reg >> 16); 418 419 /* Stolen memory is set up at the beginning of the aperture by 420 * the BIOS, consisting of the GATT followed by 4kb for the 421 * BIOS display. 422 */ 423 switch (isc->chiptype) { 424 case CHIP_I855: 425 stolen = 128 + 4; 426 break; 427 case CHIP_I915: 428 stolen = 256 + 4; 429 break; 430 case CHIP_I965: 431 stolen = 512 + 4; 432 break; 433 case CHIP_G33: 434 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 435 case AGP_G33_PGTBL_SIZE_1M: 436 stolen = 1024 + 4; 437 break; 438 case AGP_G33_PGTBL_SIZE_2M: 439 stolen = 2048 + 4; 440 break; 441 default: 442 aprint_error(": bad gtt size\n"); 443 agp_generic_detach(sc); 444 return EINVAL; 445 } 446 break; 447 default: 448 aprint_error(": bad chiptype\n"); 449 agp_generic_detach(sc); 450 return EINVAL; 451 } 452 453 switch (gcc1 & AGP_I855_GCC1_GMS) { 454 case AGP_I855_GCC1_GMS_STOLEN_1M: 455 isc->stolen = (1024 - stolen) * 1024 / 4096; 456 break; 457 case AGP_I855_GCC1_GMS_STOLEN_4M: 458 isc->stolen = (4096 - stolen) * 1024 / 4096; 459 break; 460 case AGP_I855_GCC1_GMS_STOLEN_8M: 461 isc->stolen = (8192 - stolen) * 1024 / 4096; 462 break; 463 case AGP_I855_GCC1_GMS_STOLEN_16M: 464 isc->stolen = (16384 - stolen) * 1024 / 4096; 465 break; 466 case AGP_I855_GCC1_GMS_STOLEN_32M: 467 isc->stolen = (32768 - stolen) * 1024 / 4096; 468 break; 469 case AGP_I915_GCC1_GMS_STOLEN_48M: 470 isc->stolen = (49152 - stolen) * 1024 / 4096; 471 break; 472 case AGP_I915_GCC1_GMS_STOLEN_64M: 473 isc->stolen = (65536 - stolen) * 1024 / 4096; 474 break; 475 case AGP_G33_GCC1_GMS_STOLEN_128M: 476 isc->stolen = ((128 * 1024) - stolen) * 1024 / 4096; 477 break; 478 case AGP_G33_GCC1_GMS_STOLEN_256M: 479 isc->stolen = ((256 * 1024) - stolen) * 1024 / 4096; 480 break; 481 default: 482 isc->stolen = 0; 483 aprint_error( 484 ": unknown memory configuration, disabling\n"); 485 agp_generic_detach(sc); 486 return EINVAL; 487 } 488 if (isc->stolen > 0) { 489 aprint_error(": detected %dk stolen memory\n%s", 490 isc->stolen * 4, sc->as_dev.dv_xname); 491 } 492 493 /* GATT address is already in there, make sure it's enabled */ 494 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 495 pgtblctl |= 1; 496 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 497 498 gatt->ag_physical = pgtblctl & ~1; 499 } 500 501 /* 502 * Make sure the chipset can see everything. 503 */ 504 agp_flush_cache(); 505 506 #if 0 507 /* 508 * another device (drm) may need access to this region 509 * we do not need it anymore 510 */ 511 bus_space_unmap(isc->bst, isc->bsh, mmadrsize); 512 #endif 513 514 return 0; 515 } 516 517 #if 0 518 static int 519 agp_i810_detach(struct agp_softc *sc) 520 { 521 int error; 522 struct agp_i810_softc *isc = sc->as_chipc; 523 524 error = agp_generic_detach(sc); 525 if (error) 526 return error; 527 528 /* Clear the GATT base. */ 529 if (sc->chiptype == CHIP_I810) { 530 WRITE4(AGP_I810_PGTBL_CTL, 0); 531 } else { 532 unsigned int pgtblctl; 533 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 534 pgtblctl &= ~1; 535 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 536 } 537 538 /* Put the aperture back the way it started. */ 539 AGP_SET_APERTURE(sc, isc->initial_aperture); 540 541 if (sc->chiptype == CHIP_I810) { 542 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap, 543 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 544 } 545 free(sc->gatt, M_AGP); 546 547 return 0; 548 } 549 #endif 550 551 static u_int32_t 552 agp_i810_get_aperture(struct agp_softc *sc) 553 { 554 struct agp_i810_softc *isc = sc->as_chipc; 555 pcireg_t reg; 556 u_int16_t miscc, gcc1, msac; 557 558 switch (isc->chiptype) { 559 case CHIP_I810: 560 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 561 miscc = (u_int16_t)(reg >> 16); 562 if ((miscc & AGP_I810_MISCC_WINSIZE) == 563 AGP_I810_MISCC_WINSIZE_32) 564 return 32 * 1024 * 1024; 565 else 566 return 64 * 1024 * 1024; 567 case CHIP_I830: 568 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 569 gcc1 = (u_int16_t)(reg >> 16); 570 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 571 return 64 * 1024 * 1024; 572 else 573 return 128 * 1024 * 1024; 574 case CHIP_I855: 575 return 128 * 1024 * 1024; 576 case CHIP_I915: 577 case CHIP_G33: 578 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I915_MSAC); 579 msac = (u_int16_t)(reg >> 16); 580 if (msac & AGP_I915_MSAC_APER_128M) 581 return 128 * 1024 * 1024; 582 else 583 return 256 * 1024 * 1024; 584 case CHIP_I965: 585 return 512 * 1024 * 1024; 586 default: 587 aprint_error(": Unknown chipset\n"); 588 } 589 590 return 0; 591 } 592 593 static int 594 agp_i810_set_aperture(struct agp_softc *sc, u_int32_t aperture) 595 { 596 struct agp_i810_softc *isc = sc->as_chipc; 597 pcireg_t reg; 598 u_int16_t miscc, gcc1; 599 600 switch (isc->chiptype) { 601 case CHIP_I810: 602 /* 603 * Double check for sanity. 604 */ 605 if (aperture != (32 * 1024 * 1024) && 606 aperture != (64 * 1024 * 1024)) { 607 printf("%s: bad aperture size %d\n", 608 sc->as_dev.dv_xname, aperture); 609 return EINVAL; 610 } 611 612 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 613 miscc = (u_int16_t)(reg >> 16); 614 miscc &= ~AGP_I810_MISCC_WINSIZE; 615 if (aperture == 32 * 1024 * 1024) 616 miscc |= AGP_I810_MISCC_WINSIZE_32; 617 else 618 miscc |= AGP_I810_MISCC_WINSIZE_64; 619 620 reg &= 0x0000ffff; 621 reg |= ((pcireg_t)miscc) << 16; 622 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I810_SMRAM, reg); 623 break; 624 case CHIP_I830: 625 if (aperture != (64 * 1024 * 1024) && 626 aperture != (128 * 1024 * 1024)) { 627 printf("%s: bad aperture size %d\n", 628 sc->as_dev.dv_xname, aperture); 629 return EINVAL; 630 } 631 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 632 gcc1 = (u_int16_t)(reg >> 16); 633 gcc1 &= ~AGP_I830_GCC1_GMASIZE; 634 if (aperture == 64 * 1024 * 1024) 635 gcc1 |= AGP_I830_GCC1_GMASIZE_64; 636 else 637 gcc1 |= AGP_I830_GCC1_GMASIZE_128; 638 639 reg &= 0x0000ffff; 640 reg |= ((pcireg_t)gcc1) << 16; 641 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I830_GCC0, reg); 642 break; 643 case CHIP_I855: 644 case CHIP_I915: 645 if (aperture != agp_i810_get_aperture(sc)) { 646 printf("%s: bad aperture size %d\n", 647 sc->as_dev.dv_xname, aperture); 648 return EINVAL; 649 } 650 break; 651 case CHIP_I965: 652 if (aperture != 512 * 1024 * 1024) { 653 printf("%s: bad aperture size %d\n", 654 sc->as_dev.dv_xname, aperture); 655 return EINVAL; 656 } 657 break; 658 } 659 660 return 0; 661 } 662 663 static int 664 agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 665 { 666 struct agp_i810_softc *isc = sc->as_chipc; 667 668 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) { 669 #ifdef AGP_DEBUG 670 printf("%s: failed: offset 0x%08x, shift %d, entries %d\n", 671 sc->as_dev.dv_xname, (int)offset, AGP_PAGE_SHIFT, 672 isc->gatt->ag_entries); 673 #endif 674 return EINVAL; 675 } 676 677 if (isc->chiptype != CHIP_I830) { 678 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 679 #ifdef AGP_DEBUG 680 printf("%s: trying to bind into stolen memory", 681 sc->as_dev.dv_xname); 682 #endif 683 return EINVAL; 684 } 685 } 686 687 WRITEGTT(offset, physical | 1); 688 return 0; 689 } 690 691 static int 692 agp_i810_unbind_page(struct agp_softc *sc, off_t offset) 693 { 694 struct agp_i810_softc *isc = sc->as_chipc; 695 696 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 697 return EINVAL; 698 699 if (isc->chiptype != CHIP_I810 ) { 700 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 701 #ifdef AGP_DEBUG 702 printf("%s: trying to unbind from stolen memory", 703 sc->as_dev.dv_xname); 704 #endif 705 return EINVAL; 706 } 707 } 708 709 WRITEGTT(offset, 0); 710 return 0; 711 } 712 713 /* 714 * Writing via memory mapped registers already flushes all TLBs. 715 */ 716 static void 717 agp_i810_flush_tlb(struct agp_softc *sc) 718 { 719 } 720 721 static int 722 agp_i810_enable(struct agp_softc *sc, u_int32_t mode) 723 { 724 725 return 0; 726 } 727 728 static struct agp_memory * 729 agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size) 730 { 731 struct agp_i810_softc *isc = sc->as_chipc; 732 struct agp_memory *mem; 733 734 #ifdef AGP_DEBUG 735 printf("AGP: alloc(%d, 0x%x)\n", type, (int) size); 736 #endif 737 738 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 739 return 0; 740 741 if (sc->as_allocated + size > sc->as_maxmem) 742 return 0; 743 744 if (type == 1) { 745 /* 746 * Mapping local DRAM into GATT. 747 */ 748 if (isc->chiptype != CHIP_I810 ) 749 return 0; 750 if (size != isc->dcache_size) 751 return 0; 752 } else if (type == 2) { 753 /* 754 * Bogus mapping for the hardware cursor. 755 */ 756 if (size != AGP_PAGE_SIZE && size != 4 * AGP_PAGE_SIZE) 757 return 0; 758 } 759 760 mem = malloc(sizeof *mem, M_AGP, M_WAITOK|M_ZERO); 761 if (mem == NULL) 762 return NULL; 763 mem->am_id = sc->as_nextid++; 764 mem->am_size = size; 765 mem->am_type = type; 766 767 if (type == 2) { 768 /* 769 * Allocate and wire down the memory now so that we can 770 * get its physical address. 771 */ 772 mem->am_dmaseg = malloc(sizeof *mem->am_dmaseg, M_AGP, 773 M_WAITOK); 774 if (mem->am_dmaseg == NULL) { 775 free(mem, M_AGP); 776 return NULL; 777 } 778 if (agp_alloc_dmamem(sc->as_dmat, size, 0, 779 &mem->am_dmamap, &mem->am_virtual, &mem->am_physical, 780 mem->am_dmaseg, 1, &mem->am_nseg) != 0) { 781 free(mem->am_dmaseg, M_AGP); 782 free(mem, M_AGP); 783 return NULL; 784 } 785 memset(mem->am_virtual, 0, size); 786 } else if (type != 1) { 787 if (bus_dmamap_create(sc->as_dmat, size, size / PAGE_SIZE + 1, 788 size, 0, BUS_DMA_NOWAIT, 789 &mem->am_dmamap) != 0) { 790 free(mem, M_AGP); 791 return NULL; 792 } 793 } 794 795 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link); 796 sc->as_allocated += size; 797 798 return mem; 799 } 800 801 static int 802 agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem) 803 { 804 if (mem->am_is_bound) 805 return EBUSY; 806 807 if (mem->am_type == 2) { 808 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap, 809 mem->am_virtual, mem->am_dmaseg, mem->am_nseg); 810 free(mem->am_dmaseg, M_AGP); 811 } 812 813 sc->as_allocated -= mem->am_size; 814 TAILQ_REMOVE(&sc->as_memory, mem, am_link); 815 free(mem, M_AGP); 816 return 0; 817 } 818 819 static int 820 agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem, 821 off_t offset) 822 { 823 struct agp_i810_softc *isc = sc->as_chipc; 824 u_int32_t regval, i; 825 826 /* 827 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 828 * X server for mysterious reasons which leads to crashes if we write 829 * to the GTT through the MMIO window. 830 * Until the issue is solved, simply restore it. 831 */ 832 833 #if 0 834 regval = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL); 835 if (regval != (isc->gatt->ag_physical | 1)) { 836 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%x - fixing\n", 837 regval); 838 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 839 isc->gatt->ag_physical | 1); 840 } 841 #endif 842 regval = 0; 843 844 if (mem->am_type == 2) { 845 WRITEGTT(offset, mem->am_physical | 1); 846 mem->am_offset = offset; 847 mem->am_is_bound = 1; 848 return 0; 849 } 850 851 if (mem->am_type != 1) 852 return agp_generic_bind_memory(sc, mem, offset); 853 854 if (isc->chiptype != CHIP_I810) 855 return EINVAL; 856 857 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 858 WRITEGTT(offset, i | 3); 859 mem->am_is_bound = 1; 860 return 0; 861 } 862 863 static int 864 agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem) 865 { 866 struct agp_i810_softc *isc = sc->as_chipc; 867 u_int32_t i; 868 869 if (mem->am_type == 2) { 870 WRITEGTT(mem->am_offset, 0); 871 mem->am_offset = 0; 872 mem->am_is_bound = 0; 873 return 0; 874 } 875 876 if (mem->am_type != 1) 877 return agp_generic_unbind_memory(sc, mem); 878 879 if (isc->chiptype != CHIP_I810) 880 return EINVAL; 881 882 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 883 WRITEGTT(i, 0); 884 mem->am_is_bound = 0; 885 return 0; 886 } 887 888 static bool 889 agp_i810_resume(device_t dv) 890 { 891 struct agp_softc *sc = device_private(dv); 892 struct agp_i810_softc *isc = sc->as_chipc; 893 894 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 895 agp_flush_cache(); 896 897 return true; 898 } 899
Indexes created Tue Oct 07 21:09:53 GMT 2025