agp_i810.c revision 1.41.6.6
1 /* $NetBSD: agp_i810.c,v 1.41.6.6 2007/09/06 22:12:53 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/pci/agp_i810.c,v 1.4 2001/07/05 21:28:47 jhb Exp $ 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.41.6.6 2007/09/06 22:12:53 jmcneill Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/lock.h> 40 #include <sys/proc.h> 41 #include <sys/device.h> 42 #include <sys/conf.h> 43 44 #include <uvm/uvm_extern.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcidevs.h> 49 #include <dev/pci/agpvar.h> 50 #include <dev/pci/agpreg.h> 51 52 #include <sys/agpio.h> 53 54 #include <machine/bus.h> 55 56 #include "agp_intel.h" 57 58 #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off) 59 #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off) 60 #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v) 61 #define WRITEGTT(off, v) \ 62 do { \ 63 if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33) { \ 64 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, \ 65 (u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4, \ 66 (v)); \ 67 } else if (isc->chiptype == CHIP_I965) { \ 68 WRITE4(AGP_I965_GTT + \ 69 (u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4, \ 70 (v)); \ 71 } else { \ 72 WRITE4(AGP_I810_GTT + \ 73 (u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4, \ 74 (v)); \ 75 } \ 76 } while (0) 77 78 #define CHIP_I810 0 /* i810/i815 */ 79 #define CHIP_I830 1 /* 830M/845G */ 80 #define CHIP_I855 2 /* 852GM/855GM/865G */ 81 #define CHIP_I915 3 /* 915G/915GM/945G/945GM */ 82 #define CHIP_I965 4 /* 965Q/965PM */ 83 #define CHIP_G33 5 /* G33/Q33/Q35 */ 84 85 struct agp_i810_softc { 86 u_int32_t initial_aperture; /* aperture size at startup */ 87 struct agp_gatt *gatt; 88 int chiptype; /* i810-like or i830 */ 89 u_int32_t dcache_size; /* i810 only */ 90 u_int32_t stolen; /* number of i830/845 gtt entries 91 for stolen memory */ 92 bus_space_tag_t bst; /* register bus_space tag */ 93 bus_space_handle_t bsh; /* register bus_space handle */ 94 bus_space_tag_t gtt_bst; /* GTT bus_space tag */ 95 bus_space_handle_t gtt_bsh; /* GTT bus_space handle */ 96 struct pci_attach_args vga_pa; 97 98 u_int32_t pgtblctl; 99 }; 100 101 static u_int32_t agp_i810_get_aperture(struct agp_softc *); 102 static int agp_i810_set_aperture(struct agp_softc *, u_int32_t); 103 static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t); 104 static int agp_i810_unbind_page(struct agp_softc *, off_t); 105 static void agp_i810_flush_tlb(struct agp_softc *); 106 static int agp_i810_enable(struct agp_softc *, u_int32_t mode); 107 static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int, 108 vsize_t); 109 static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *); 110 static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, off_t); 111 static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *); 112 113 static pnp_status_t agp_i810_power(device_t, pnp_request_t, void *); 114 static int agp_i810_init(struct agp_softc *); 115 116 static struct agp_methods agp_i810_methods = { 117 agp_i810_get_aperture, 118 agp_i810_set_aperture, 119 agp_i810_bind_page, 120 agp_i810_unbind_page, 121 agp_i810_flush_tlb, 122 agp_i810_enable, 123 agp_i810_alloc_memory, 124 agp_i810_free_memory, 125 agp_i810_bind_memory, 126 agp_i810_unbind_memory, 127 }; 128 129 /* XXXthorpej -- duplicated code (see arch/i386/pci/pchb.c) */ 130 static int 131 agp_i810_vgamatch(struct pci_attach_args *pa) 132 { 133 134 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 135 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 136 return (0); 137 138 switch (PCI_PRODUCT(pa->pa_id)) { 139 case PCI_PRODUCT_INTEL_82810_GC: 140 case PCI_PRODUCT_INTEL_82810_DC100_GC: 141 case PCI_PRODUCT_INTEL_82810E_GC: 142 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 143 case PCI_PRODUCT_INTEL_82830MP_IV: 144 case PCI_PRODUCT_INTEL_82845G_IGD: 145 case PCI_PRODUCT_INTEL_82855GM_IGD: 146 case PCI_PRODUCT_INTEL_82865_IGD: 147 case PCI_PRODUCT_INTEL_82915G_IGD: 148 case PCI_PRODUCT_INTEL_82915GM_IGD: 149 case PCI_PRODUCT_INTEL_82945P_IGD: 150 case PCI_PRODUCT_INTEL_82945GM_IGD: 151 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 152 case PCI_PRODUCT_INTEL_82965Q_IGD: 153 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 154 case PCI_PRODUCT_INTEL_82965PM_IGD: 155 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 156 case PCI_PRODUCT_INTEL_82G33_IGD: 157 case PCI_PRODUCT_INTEL_82G33_IGD_1: 158 return (1); 159 } 160 161 return (0); 162 } 163 164 static int 165 agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg) 166 { 167 /* 168 * Find the aperture. Don't map it (yet), this would 169 * eat KVA. 170 */ 171 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 172 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize, 173 &sc->as_apflags) != 0) 174 return ENXIO; 175 176 sc->as_apt = pa->pa_memt; 177 178 return 0; 179 } 180 181 int 182 agp_i810_attach(struct device *parent, struct device *self, void *aux) 183 { 184 struct agp_softc *sc = (void *)self; 185 struct agp_i810_softc *isc; 186 struct agp_gatt *gatt; 187 int error, apbase; 188 bus_size_t mmadrsize; 189 190 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 191 if (isc == NULL) { 192 aprint_error(": can't allocate chipset-specific softc\n"); 193 return ENOMEM; 194 } 195 sc->as_chipc = isc; 196 sc->as_methods = &agp_i810_methods; 197 198 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) { 199 #if NAGP_INTEL > 0 200 const struct pci_attach_args *pa = aux; 201 202 switch (PCI_PRODUCT(pa->pa_id)) { 203 case PCI_PRODUCT_INTEL_82840_HB: 204 case PCI_PRODUCT_INTEL_82865_HB: 205 case PCI_PRODUCT_INTEL_82845G_DRAM: 206 case PCI_PRODUCT_INTEL_82815_FULL_HUB: 207 return agp_intel_attach(parent, self, aux); 208 } 209 #endif 210 aprint_error(": can't find internal VGA device config space\n"); 211 free(isc, M_AGP); 212 return ENOENT; 213 } 214 215 /* XXXfvdl */ 216 sc->as_dmat = isc->vga_pa.pa_dmat; 217 218 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 219 case PCI_PRODUCT_INTEL_82810_GC: 220 case PCI_PRODUCT_INTEL_82810_DC100_GC: 221 case PCI_PRODUCT_INTEL_82810E_GC: 222 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 223 isc->chiptype = CHIP_I810; 224 break; 225 case PCI_PRODUCT_INTEL_82830MP_IV: 226 case PCI_PRODUCT_INTEL_82845G_IGD: 227 isc->chiptype = CHIP_I830; 228 break; 229 case PCI_PRODUCT_INTEL_82855GM_IGD: 230 case PCI_PRODUCT_INTEL_82865_IGD: 231 isc->chiptype = CHIP_I855; 232 break; 233 case PCI_PRODUCT_INTEL_82915G_IGD: 234 case PCI_PRODUCT_INTEL_82915GM_IGD: 235 case PCI_PRODUCT_INTEL_82945P_IGD: 236 case PCI_PRODUCT_INTEL_82945GM_IGD: 237 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 238 isc->chiptype = CHIP_I915; 239 break; 240 case PCI_PRODUCT_INTEL_82965Q_IGD: 241 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 242 case PCI_PRODUCT_INTEL_82965PM_IGD: 243 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 244 isc->chiptype = CHIP_I965; 245 break; 246 case PCI_PRODUCT_INTEL_82G33_IGD: 247 case PCI_PRODUCT_INTEL_82G33_IGD_1: 248 isc->chiptype = CHIP_G33; 249 break; 250 } 251 252 switch (isc->chiptype) { 253 case CHIP_I915: 254 case CHIP_G33: 255 apbase = AGP_I915_GMADR; 256 break; 257 default: 258 apbase = AGP_I810_GMADR; 259 break; 260 } 261 if (isc->chiptype == CHIP_I965) { 262 error = agp_i965_map_aperture(&isc->vga_pa, sc, AGP_I965_GMADR); 263 } else { 264 error = agp_map_aperture(&isc->vga_pa, sc, apbase); 265 } 266 if (error != 0) { 267 aprint_error(": can't map aperture\n"); 268 free(isc, M_AGP); 269 return error; 270 } 271 272 if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33) { 273 error = pci_mapreg_map(&isc->vga_pa, AGP_I915_MMADR, 274 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 275 NULL, &mmadrsize); 276 if (error != 0) { 277 aprint_error(": can't map mmadr registers\n"); 278 agp_generic_detach(sc); 279 return error; 280 } 281 error = pci_mapreg_map(&isc->vga_pa, AGP_I915_GTTADR, 282 PCI_MAPREG_TYPE_MEM, 0, &isc->gtt_bst, &isc->gtt_bsh, 283 NULL, NULL); 284 if (error != 0) { 285 aprint_error(": can't map gttadr registers\n"); 286 /* XXX we should release mmadr here */ 287 agp_generic_detach(sc); 288 return error; 289 } 290 } else if (isc->chiptype == CHIP_I965) { 291 error = pci_mapreg_map(&isc->vga_pa, AGP_I965_MMADR, 292 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 293 NULL, &mmadrsize); 294 if (error != 0) { 295 aprint_error(": can't map mmadr registers\n"); 296 agp_generic_detach(sc); 297 return error; 298 } 299 } else { 300 error = pci_mapreg_map(&isc->vga_pa, AGP_I810_MMADR, 301 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 302 NULL, &mmadrsize); 303 if (error != 0) { 304 aprint_error(": can't map mmadr registers\n"); 305 agp_generic_detach(sc); 306 return error; 307 } 308 } 309 310 isc->initial_aperture = AGP_GET_APERTURE(sc); 311 312 gatt = malloc(sizeof(struct agp_gatt), M_AGP, M_NOWAIT); 313 if (!gatt) { 314 agp_generic_detach(sc); 315 return ENOMEM; 316 } 317 isc->gatt = gatt; 318 319 gatt->ag_entries = AGP_GET_APERTURE(sc) >> AGP_PAGE_SHIFT; 320 321 if (pnp_register(self, agp_i810_power) != PNP_STATUS_SUCCESS) 322 aprint_error("%s: couldn't establish power handler\n", 323 device_xname(&sc->as_dev)); 324 325 return agp_i810_init(sc); 326 } 327 328 static int agp_i810_init(struct agp_softc *sc) 329 { 330 struct agp_i810_softc *isc; 331 struct agp_gatt *gatt; 332 333 isc = sc->as_chipc; 334 gatt = isc->gatt; 335 336 if (isc->chiptype == CHIP_I810) { 337 void *virtual; 338 int dummyseg; 339 340 /* Some i810s have on-chip memory called dcache */ 341 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 342 isc->dcache_size = 4 * 1024 * 1024; 343 else 344 isc->dcache_size = 0; 345 346 /* According to the specs the gatt on the i810 must be 64k */ 347 if (agp_alloc_dmamem(sc->as_dmat, 64 * 1024, 348 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical, 349 &gatt->ag_dmaseg, 1, &dummyseg) != 0) { 350 free(gatt, M_AGP); 351 agp_generic_detach(sc); 352 return ENOMEM; 353 } 354 gatt->ag_virtual = (uint32_t *)virtual; 355 gatt->ag_size = gatt->ag_entries * sizeof(u_int32_t); 356 memset(gatt->ag_virtual, 0, gatt->ag_size); 357 358 agp_flush_cache(); 359 /* Install the GATT. */ 360 WRITE4(AGP_I810_PGTBL_CTL, gatt->ag_physical | 1); 361 } else if (isc->chiptype == CHIP_I830) { 362 /* The i830 automatically initializes the 128k gatt on boot. */ 363 pcireg_t reg; 364 u_int32_t pgtblctl; 365 u_int16_t gcc1; 366 367 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 368 gcc1 = (u_int16_t)(reg >> 16); 369 switch (gcc1 & AGP_I830_GCC1_GMS) { 370 case AGP_I830_GCC1_GMS_STOLEN_512: 371 isc->stolen = (512 - 132) * 1024 / 4096; 372 break; 373 case AGP_I830_GCC1_GMS_STOLEN_1024: 374 isc->stolen = (1024 - 132) * 1024 / 4096; 375 break; 376 case AGP_I830_GCC1_GMS_STOLEN_8192: 377 isc->stolen = (8192 - 132) * 1024 / 4096; 378 break; 379 default: 380 isc->stolen = 0; 381 aprint_error( 382 ": unknown memory configuration, disabling\n"); 383 agp_generic_detach(sc); 384 return EINVAL; 385 } 386 387 if (isc->stolen > 0) { 388 aprint_error(": detected %dk stolen memory\n%s", 389 isc->stolen * 4, sc->as_dev.dv_xname); 390 } 391 392 /* GATT address is already in there, make sure it's enabled */ 393 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 394 pgtblctl |= 1; 395 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 396 397 gatt->ag_physical = pgtblctl & ~1; 398 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 399 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33) { 400 pcireg_t reg; 401 u_int32_t pgtblctl, stolen; 402 u_int16_t gcc1; 403 404 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1); 405 gcc1 = (u_int16_t)(reg >> 16); 406 407 /* Stolen memory is set up at the beginning of the aperture by 408 * the BIOS, consisting of the GATT followed by 4kb for the 409 * BIOS display. 410 */ 411 switch (isc->chiptype) { 412 case CHIP_I855: 413 stolen = 128 + 4; 414 break; 415 case CHIP_I915: 416 stolen = 256 + 4; 417 break; 418 case CHIP_I965: 419 stolen = 512 + 4; 420 break; 421 case CHIP_G33: 422 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 423 case AGP_G33_PGTBL_SIZE_1M: 424 stolen = 1024 + 4; 425 break; 426 case AGP_G33_PGTBL_SIZE_2M: 427 stolen = 2048 + 4; 428 break; 429 default: 430 aprint_error(": bad gtt size\n"); 431 agp_generic_detach(sc); 432 return EINVAL; 433 } 434 break; 435 default: 436 aprint_error(": bad chiptype\n"); 437 agp_generic_detach(sc); 438 return EINVAL; 439 } 440 441 switch (gcc1 & AGP_I855_GCC1_GMS) { 442 case AGP_I855_GCC1_GMS_STOLEN_1M: 443 isc->stolen = (1024 - stolen) * 1024 / 4096; 444 break; 445 case AGP_I855_GCC1_GMS_STOLEN_4M: 446 isc->stolen = (4096 - stolen) * 1024 / 4096; 447 break; 448 case AGP_I855_GCC1_GMS_STOLEN_8M: 449 isc->stolen = (8192 - stolen) * 1024 / 4096; 450 break; 451 case AGP_I855_GCC1_GMS_STOLEN_16M: 452 isc->stolen = (16384 - stolen) * 1024 / 4096; 453 break; 454 case AGP_I855_GCC1_GMS_STOLEN_32M: 455 isc->stolen = (32768 - stolen) * 1024 / 4096; 456 break; 457 case AGP_I915_GCC1_GMS_STOLEN_48M: 458 isc->stolen = (49152 - stolen) * 1024 / 4096; 459 break; 460 case AGP_I915_GCC1_GMS_STOLEN_64M: 461 isc->stolen = (65536 - stolen) * 1024 / 4096; 462 break; 463 default: 464 isc->stolen = 0; 465 aprint_error( 466 ": unknown memory configuration, disabling\n"); 467 agp_generic_detach(sc); 468 return EINVAL; 469 } 470 if (isc->stolen > 0) { 471 aprint_error(": detected %dk stolen memory\n%s", 472 isc->stolen * 4, sc->as_dev.dv_xname); 473 } 474 475 /* GATT address is already in there, make sure it's enabled */ 476 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 477 pgtblctl |= 1; 478 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 479 480 gatt->ag_physical = pgtblctl & ~1; 481 } 482 483 /* 484 * Make sure the chipset can see everything. 485 */ 486 agp_flush_cache(); 487 488 #if 0 489 /* 490 * another device (drm) may need access to this region 491 * we do not need it anymore 492 */ 493 bus_space_unmap(isc->bst, isc->bsh, mmadrsize); 494 #endif 495 496 return 0; 497 } 498 499 #if 0 500 static int 501 agp_i810_detach(struct agp_softc *sc) 502 { 503 int error; 504 struct agp_i810_softc *isc = sc->as_chipc; 505 506 error = agp_generic_detach(sc); 507 if (error) 508 return error; 509 510 /* Clear the GATT base. */ 511 if (sc->chiptype == CHIP_I810) { 512 WRITE4(AGP_I810_PGTBL_CTL, 0); 513 } else { 514 unsigned int pgtblctl; 515 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 516 pgtblctl &= ~1; 517 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 518 } 519 520 /* Put the aperture back the way it started. */ 521 AGP_SET_APERTURE(sc, isc->initial_aperture); 522 523 if (sc->chiptype == CHIP_I810) { 524 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap, 525 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 526 } 527 free(sc->gatt, M_AGP); 528 529 return 0; 530 } 531 #endif 532 533 static u_int32_t 534 agp_i810_get_aperture(struct agp_softc *sc) 535 { 536 struct agp_i810_softc *isc = sc->as_chipc; 537 pcireg_t reg; 538 u_int16_t miscc, gcc1, msac; 539 540 switch (isc->chiptype) { 541 case CHIP_I810: 542 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 543 miscc = (u_int16_t)(reg >> 16); 544 if ((miscc & AGP_I810_MISCC_WINSIZE) == 545 AGP_I810_MISCC_WINSIZE_32) 546 return 32 * 1024 * 1024; 547 else 548 return 64 * 1024 * 1024; 549 case CHIP_I830: 550 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 551 gcc1 = (u_int16_t)(reg >> 16); 552 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 553 return 64 * 1024 * 1024; 554 else 555 return 128 * 1024 * 1024; 556 case CHIP_I855: 557 return 128 * 1024 * 1024; 558 case CHIP_I915: 559 case CHIP_G33: 560 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I915_MSAC); 561 msac = (u_int16_t)(reg >> 16); 562 if (msac & AGP_I915_MSAC_APER_128M) 563 return 128 * 1024 * 1024; 564 else 565 return 256 * 1024 * 1024; 566 case CHIP_I965: 567 return 512 * 1024 * 1024; 568 default: 569 aprint_error(": Unknown chipset\n"); 570 } 571 572 return 0; 573 } 574 575 static int 576 agp_i810_set_aperture(struct agp_softc *sc, u_int32_t aperture) 577 { 578 struct agp_i810_softc *isc = sc->as_chipc; 579 pcireg_t reg; 580 u_int16_t miscc, gcc1; 581 582 switch (isc->chiptype) { 583 case CHIP_I810: 584 /* 585 * Double check for sanity. 586 */ 587 if (aperture != (32 * 1024 * 1024) && 588 aperture != (64 * 1024 * 1024)) { 589 printf("%s: bad aperture size %d\n", 590 sc->as_dev.dv_xname, aperture); 591 return EINVAL; 592 } 593 594 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 595 miscc = (u_int16_t)(reg >> 16); 596 miscc &= ~AGP_I810_MISCC_WINSIZE; 597 if (aperture == 32 * 1024 * 1024) 598 miscc |= AGP_I810_MISCC_WINSIZE_32; 599 else 600 miscc |= AGP_I810_MISCC_WINSIZE_64; 601 602 reg &= 0x0000ffff; 603 reg |= ((pcireg_t)miscc) << 16; 604 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I810_SMRAM, reg); 605 break; 606 case CHIP_I830: 607 if (aperture != (64 * 1024 * 1024) && 608 aperture != (128 * 1024 * 1024)) { 609 printf("%s: bad aperture size %d\n", 610 sc->as_dev.dv_xname, aperture); 611 return EINVAL; 612 } 613 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 614 gcc1 = (u_int16_t)(reg >> 16); 615 gcc1 &= ~AGP_I830_GCC1_GMASIZE; 616 if (aperture == 64 * 1024 * 1024) 617 gcc1 |= AGP_I830_GCC1_GMASIZE_64; 618 else 619 gcc1 |= AGP_I830_GCC1_GMASIZE_128; 620 621 reg &= 0x0000ffff; 622 reg |= ((pcireg_t)gcc1) << 16; 623 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I830_GCC0, reg); 624 break; 625 case CHIP_I855: 626 case CHIP_I915: 627 if (aperture != agp_i810_get_aperture(sc)) { 628 printf("%s: bad aperture size %d\n", 629 sc->as_dev.dv_xname, aperture); 630 return EINVAL; 631 } 632 break; 633 case CHIP_I965: 634 if (aperture != 512 * 1024 * 1024) { 635 printf("%s: bad aperture size %d\n", 636 sc->as_dev.dv_xname, aperture); 637 return EINVAL; 638 } 639 break; 640 } 641 642 return 0; 643 } 644 645 static int 646 agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 647 { 648 struct agp_i810_softc *isc = sc->as_chipc; 649 650 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) { 651 #ifdef AGP_DEBUG 652 printf("%s: failed: offset 0x%08x, shift %d, entries %d\n", 653 sc->as_dev.dv_xname, (int)offset, AGP_PAGE_SHIFT, 654 isc->gatt->ag_entries); 655 #endif 656 return EINVAL; 657 } 658 659 if (isc->chiptype != CHIP_I830) { 660 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 661 #ifdef AGP_DEBUG 662 printf("%s: trying to bind into stolen memory", 663 sc->as_dev.dv_xname); 664 #endif 665 return EINVAL; 666 } 667 } 668 669 WRITEGTT(offset, physical | 1); 670 return 0; 671 } 672 673 static int 674 agp_i810_unbind_page(struct agp_softc *sc, off_t offset) 675 { 676 struct agp_i810_softc *isc = sc->as_chipc; 677 678 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 679 return EINVAL; 680 681 if (isc->chiptype != CHIP_I810 ) { 682 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 683 #ifdef AGP_DEBUG 684 printf("%s: trying to unbind from stolen memory", 685 sc->as_dev.dv_xname); 686 #endif 687 return EINVAL; 688 } 689 } 690 691 WRITEGTT(offset, 0); 692 return 0; 693 } 694 695 /* 696 * Writing via memory mapped registers already flushes all TLBs. 697 */ 698 static void 699 agp_i810_flush_tlb(struct agp_softc *sc) 700 { 701 } 702 703 static int 704 agp_i810_enable(struct agp_softc *sc, u_int32_t mode) 705 { 706 707 return 0; 708 } 709 710 static struct agp_memory * 711 agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size) 712 { 713 struct agp_i810_softc *isc = sc->as_chipc; 714 struct agp_memory *mem; 715 716 #ifdef AGP_DEBUG 717 printf("AGP: alloc(%d, 0x%x)\n", type, (int) size); 718 #endif 719 720 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 721 return 0; 722 723 if (sc->as_allocated + size > sc->as_maxmem) 724 return 0; 725 726 if (type == 1) { 727 /* 728 * Mapping local DRAM into GATT. 729 */ 730 if (isc->chiptype != CHIP_I810 ) 731 return 0; 732 if (size != isc->dcache_size) 733 return 0; 734 } else if (type == 2) { 735 /* 736 * Bogus mapping for the hardware cursor. 737 */ 738 if (size != AGP_PAGE_SIZE && size != 4 * AGP_PAGE_SIZE) 739 return 0; 740 } 741 742 mem = malloc(sizeof *mem, M_AGP, M_WAITOK|M_ZERO); 743 if (mem == NULL) 744 return NULL; 745 mem->am_id = sc->as_nextid++; 746 mem->am_size = size; 747 mem->am_type = type; 748 749 if (type == 2) { 750 /* 751 * Allocate and wire down the memory now so that we can 752 * get its physical address. 753 */ 754 mem->am_dmaseg = malloc(sizeof *mem->am_dmaseg, M_AGP, 755 M_WAITOK); 756 if (mem->am_dmaseg == NULL) { 757 free(mem, M_AGP); 758 return NULL; 759 } 760 if (agp_alloc_dmamem(sc->as_dmat, size, 0, 761 &mem->am_dmamap, &mem->am_virtual, &mem->am_physical, 762 mem->am_dmaseg, 1, &mem->am_nseg) != 0) { 763 free(mem->am_dmaseg, M_AGP); 764 free(mem, M_AGP); 765 return NULL; 766 } 767 memset(mem->am_virtual, 0, size); 768 } else if (type != 1) { 769 if (bus_dmamap_create(sc->as_dmat, size, size / PAGE_SIZE + 1, 770 size, 0, BUS_DMA_NOWAIT, 771 &mem->am_dmamap) != 0) { 772 free(mem, M_AGP); 773 return NULL; 774 } 775 } 776 777 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link); 778 sc->as_allocated += size; 779 780 return mem; 781 } 782 783 static int 784 agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem) 785 { 786 if (mem->am_is_bound) 787 return EBUSY; 788 789 if (mem->am_type == 2) { 790 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap, 791 mem->am_virtual, mem->am_dmaseg, mem->am_nseg); 792 free(mem->am_dmaseg, M_AGP); 793 } 794 795 sc->as_allocated -= mem->am_size; 796 TAILQ_REMOVE(&sc->as_memory, mem, am_link); 797 free(mem, M_AGP); 798 return 0; 799 } 800 801 static int 802 agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem, 803 off_t offset) 804 { 805 struct agp_i810_softc *isc = sc->as_chipc; 806 u_int32_t regval, i; 807 808 /* 809 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 810 * X server for mysterious reasons which leads to crashes if we write 811 * to the GTT through the MMIO window. 812 * Until the issue is solved, simply restore it. 813 */ 814 815 #if 0 816 regval = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL); 817 if (regval != (isc->gatt->ag_physical | 1)) { 818 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%x - fixing\n", 819 regval); 820 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 821 isc->gatt->ag_physical | 1); 822 } 823 #endif 824 regval = 0; 825 826 if (mem->am_type == 2) { 827 WRITEGTT(offset, mem->am_physical | 1); 828 mem->am_offset = offset; 829 mem->am_is_bound = 1; 830 return 0; 831 } 832 833 if (mem->am_type != 1) 834 return agp_generic_bind_memory(sc, mem, offset); 835 836 if (isc->chiptype != CHIP_I810) 837 return EINVAL; 838 839 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 840 WRITEGTT(offset, i | 3); 841 mem->am_is_bound = 1; 842 return 0; 843 } 844 845 static int 846 agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem) 847 { 848 struct agp_i810_softc *isc = sc->as_chipc; 849 u_int32_t i; 850 851 if (mem->am_type == 2) { 852 WRITEGTT(mem->am_offset, 0); 853 mem->am_offset = 0; 854 mem->am_is_bound = 0; 855 return 0; 856 } 857 858 if (mem->am_type != 1) 859 return agp_generic_unbind_memory(sc, mem); 860 861 if (isc->chiptype != CHIP_I810) 862 return EINVAL; 863 864 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 865 WRITEGTT(i, 0); 866 mem->am_is_bound = 0; 867 return 0; 868 } 869 870 static pnp_status_t 871 agp_i810_power(device_t dv, pnp_request_t req, void *opaque) 872 { 873 struct agp_softc *sc; 874 struct agp_i810_softc *isc; 875 pnp_state_t *pstate; 876 877 sc = (struct agp_softc *)dv; 878 isc = sc->as_chipc; 879 880 switch (req) { 881 case PNP_REQUEST_GET_CAPABILITIES: 882 case PNP_REQUEST_GET_STATE: 883 return agp_power(dv, req, opaque); 884 case PNP_REQUEST_SET_STATE: 885 pstate = opaque; 886 switch (*pstate) { 887 case PNP_STATE_D0: 888 agp_power(dv, req, opaque); 889 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 890 break; 891 case PNP_STATE_D3: 892 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 893 agp_power(dv, req, opaque); 894 break; 895 default: 896 return PNP_STATUS_UNSUPPORTED; 897 } 898 break; 899 default: 900 return agp_power(dv, req, opaque); 901 } 902 903 return PNP_STATUS_SUCCESS; 904 } 905
Indexes created Tue Oct 07 21:09:53 GMT 2025