agp_i810.c revision 1.52.4.5
1 /* $NetBSD: agp_i810.c,v 1.52.4.5 2010/08/11 22:53:41 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/pci/agp_i810.c,v 1.4 2001/07/05 21:28:47 jhb Exp $ 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.52.4.5 2010/08/11 22:53:41 yamt Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/proc.h> 40 #include <sys/device.h> 41 #include <sys/conf.h> 42 43 #include <uvm/uvm_extern.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/agpvar.h> 49 #include <dev/pci/agpreg.h> 50 51 #include <sys/agpio.h> 52 53 #include <sys/bus.h> 54 55 #include "agp_intel.h" 56 57 #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off) 58 #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off) 59 #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v) 60 61 #define CHIP_I810 0 /* i810/i815 */ 62 #define CHIP_I830 1 /* 830M/845G */ 63 #define CHIP_I855 2 /* 852GM/855GM/865G */ 64 #define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */ 65 #define CHIP_I965 4 /* 965Q/965PM */ 66 #define CHIP_G33 5 /* G33/Q33/Q35 */ 67 #define CHIP_G4X 6 /* G45/Q45 */ 68 69 struct agp_i810_softc { 70 u_int32_t initial_aperture; /* aperture size at startup */ 71 struct agp_gatt *gatt; 72 int chiptype; /* i810-like or i830 */ 73 u_int32_t dcache_size; /* i810 only */ 74 u_int32_t stolen; /* number of i830/845 gtt entries 75 for stolen memory */ 76 bus_space_tag_t bst; /* register bus_space tag */ 77 bus_space_handle_t bsh; /* register bus_space handle */ 78 bus_space_tag_t gtt_bst; /* GTT bus_space tag */ 79 bus_space_handle_t gtt_bsh; /* GTT bus_space handle */ 80 struct pci_attach_args vga_pa; 81 82 u_int32_t pgtblctl; 83 }; 84 85 /* XXX hack, see below */ 86 static bus_addr_t agp_i810_vga_regbase; 87 static bus_space_handle_t agp_i810_vga_bsh; 88 89 static u_int32_t agp_i810_get_aperture(struct agp_softc *); 90 static int agp_i810_set_aperture(struct agp_softc *, u_int32_t); 91 static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t); 92 static int agp_i810_unbind_page(struct agp_softc *, off_t); 93 static void agp_i810_flush_tlb(struct agp_softc *); 94 static int agp_i810_enable(struct agp_softc *, u_int32_t mode); 95 static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int, 96 vsize_t); 97 static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *); 98 static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, off_t); 99 static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *); 100 101 static bool agp_i810_resume(device_t, const pmf_qual_t *); 102 static int agp_i810_init(struct agp_softc *); 103 104 static int agp_i810_init(struct agp_softc *); 105 static void agp_i810_write_gtt_entry(struct agp_i810_softc *, off_t, 106 u_int32_t); 107 108 static struct agp_methods agp_i810_methods = { 109 agp_i810_get_aperture, 110 agp_i810_set_aperture, 111 agp_i810_bind_page, 112 agp_i810_unbind_page, 113 agp_i810_flush_tlb, 114 agp_i810_enable, 115 agp_i810_alloc_memory, 116 agp_i810_free_memory, 117 agp_i810_bind_memory, 118 agp_i810_unbind_memory, 119 }; 120 121 static void 122 agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, u_int32_t v) 123 { 124 u_int32_t base_off; 125 126 base_off = 0; 127 128 switch (isc->chiptype) { 129 case CHIP_I810: 130 case CHIP_I830: 131 case CHIP_I855: 132 base_off = AGP_I810_GTT; 133 break; 134 case CHIP_I965: 135 base_off = AGP_I965_GTT; 136 break; 137 case CHIP_G4X: 138 base_off = AGP_G4X_GTT; 139 break; 140 case CHIP_I915: 141 case CHIP_G33: 142 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, 143 (u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4, (v)); 144 return; 145 } 146 147 WRITE4(base_off + (u_int32_t)(off >> AGP_PAGE_SHIFT) * 4, v); 148 } 149 150 /* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */ 151 static int 152 agp_i810_vgamatch(struct pci_attach_args *pa) 153 { 154 155 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 156 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 157 return (0); 158 159 switch (PCI_PRODUCT(pa->pa_id)) { 160 case PCI_PRODUCT_INTEL_82810_GC: 161 case PCI_PRODUCT_INTEL_82810_DC100_GC: 162 case PCI_PRODUCT_INTEL_82810E_GC: 163 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 164 case PCI_PRODUCT_INTEL_82830MP_IV: 165 case PCI_PRODUCT_INTEL_82845G_IGD: 166 case PCI_PRODUCT_INTEL_82855GM_IGD: 167 case PCI_PRODUCT_INTEL_82865_IGD: 168 case PCI_PRODUCT_INTEL_82915G_IGD: 169 case PCI_PRODUCT_INTEL_82915GM_IGD: 170 case PCI_PRODUCT_INTEL_82945P_IGD: 171 case PCI_PRODUCT_INTEL_82945GM_IGD: 172 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 173 case PCI_PRODUCT_INTEL_82945GME_IGD: 174 case PCI_PRODUCT_INTEL_E7221_IGD: 175 case PCI_PRODUCT_INTEL_82965Q_IGD: 176 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 177 case PCI_PRODUCT_INTEL_82965PM_IGD: 178 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 179 case PCI_PRODUCT_INTEL_82G33_IGD: 180 case PCI_PRODUCT_INTEL_82G33_IGD_1: 181 case PCI_PRODUCT_INTEL_82965G_IGD: 182 case PCI_PRODUCT_INTEL_82965G_IGD_1: 183 case PCI_PRODUCT_INTEL_82965GME_IGD: 184 case PCI_PRODUCT_INTEL_82Q35_IGD: 185 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 186 case PCI_PRODUCT_INTEL_82Q33_IGD: 187 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 188 case PCI_PRODUCT_INTEL_82G35_IGD: 189 case PCI_PRODUCT_INTEL_82G35_IGD_1: 190 case PCI_PRODUCT_INTEL_82946GZ_IGD: 191 case PCI_PRODUCT_INTEL_82GM45_IGD: 192 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 193 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 194 case PCI_PRODUCT_INTEL_82Q45_IGD: 195 case PCI_PRODUCT_INTEL_82G45_IGD: 196 case PCI_PRODUCT_INTEL_82G41_IGD: 197 case PCI_PRODUCT_INTEL_82B43_IGD: 198 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 199 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 200 return (1); 201 } 202 203 return (0); 204 } 205 206 static int 207 agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg) 208 { 209 /* 210 * Find the aperture. Don't map it (yet), this would 211 * eat KVA. 212 */ 213 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 214 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize, 215 &sc->as_apflags) != 0) 216 return ENXIO; 217 218 sc->as_apt = pa->pa_memt; 219 220 return 0; 221 } 222 223 int 224 agp_i810_attach(device_t parent, device_t self, void *aux) 225 { 226 struct agp_softc *sc = device_private(self); 227 struct agp_i810_softc *isc; 228 struct agp_gatt *gatt; 229 int error, apbase; 230 bus_addr_t mmadr; 231 bus_size_t mmadrsize; 232 233 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 234 if (isc == NULL) { 235 aprint_error(": can't allocate chipset-specific softc\n"); 236 return ENOMEM; 237 } 238 sc->as_chipc = isc; 239 sc->as_methods = &agp_i810_methods; 240 241 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) { 242 #if NAGP_INTEL > 0 243 const struct pci_attach_args *pa = aux; 244 245 switch (PCI_PRODUCT(pa->pa_id)) { 246 case PCI_PRODUCT_INTEL_82840_HB: 247 case PCI_PRODUCT_INTEL_82865_HB: 248 case PCI_PRODUCT_INTEL_82845G_DRAM: 249 case PCI_PRODUCT_INTEL_82815_FULL_HUB: 250 case PCI_PRODUCT_INTEL_82855GM_MCH: 251 return agp_intel_attach(parent, self, aux); 252 } 253 #endif 254 aprint_error(": can't find internal VGA device config space\n"); 255 free(isc, M_AGP); 256 return ENOENT; 257 } 258 259 /* XXXfvdl */ 260 sc->as_dmat = isc->vga_pa.pa_dmat; 261 262 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 263 case PCI_PRODUCT_INTEL_82810_GC: 264 case PCI_PRODUCT_INTEL_82810_DC100_GC: 265 case PCI_PRODUCT_INTEL_82810E_GC: 266 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 267 isc->chiptype = CHIP_I810; 268 break; 269 case PCI_PRODUCT_INTEL_82830MP_IV: 270 case PCI_PRODUCT_INTEL_82845G_IGD: 271 isc->chiptype = CHIP_I830; 272 break; 273 case PCI_PRODUCT_INTEL_82855GM_IGD: 274 case PCI_PRODUCT_INTEL_82865_IGD: 275 isc->chiptype = CHIP_I855; 276 break; 277 case PCI_PRODUCT_INTEL_82915G_IGD: 278 case PCI_PRODUCT_INTEL_82915GM_IGD: 279 case PCI_PRODUCT_INTEL_82945P_IGD: 280 case PCI_PRODUCT_INTEL_82945GM_IGD: 281 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 282 case PCI_PRODUCT_INTEL_82945GME_IGD: 283 case PCI_PRODUCT_INTEL_E7221_IGD: 284 isc->chiptype = CHIP_I915; 285 break; 286 case PCI_PRODUCT_INTEL_82965Q_IGD: 287 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 288 case PCI_PRODUCT_INTEL_82965PM_IGD: 289 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 290 case PCI_PRODUCT_INTEL_82965G_IGD: 291 case PCI_PRODUCT_INTEL_82965G_IGD_1: 292 case PCI_PRODUCT_INTEL_82965GME_IGD: 293 case PCI_PRODUCT_INTEL_82946GZ_IGD: 294 case PCI_PRODUCT_INTEL_82G35_IGD: 295 case PCI_PRODUCT_INTEL_82G35_IGD_1: 296 isc->chiptype = CHIP_I965; 297 break; 298 case PCI_PRODUCT_INTEL_82Q35_IGD: 299 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 300 case PCI_PRODUCT_INTEL_82G33_IGD: 301 case PCI_PRODUCT_INTEL_82G33_IGD_1: 302 case PCI_PRODUCT_INTEL_82Q33_IGD: 303 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 304 isc->chiptype = CHIP_G33; 305 break; 306 case PCI_PRODUCT_INTEL_82GM45_IGD: 307 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 308 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 309 case PCI_PRODUCT_INTEL_82Q45_IGD: 310 case PCI_PRODUCT_INTEL_82G45_IGD: 311 case PCI_PRODUCT_INTEL_82G41_IGD: 312 case PCI_PRODUCT_INTEL_82B43_IGD: 313 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 314 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 315 isc->chiptype = CHIP_G4X; 316 break; 317 } 318 319 switch (isc->chiptype) { 320 case CHIP_I915: 321 case CHIP_G33: 322 apbase = AGP_I915_GMADR; 323 break; 324 case CHIP_I965: 325 case CHIP_G4X: 326 apbase = AGP_I965_GMADR; 327 break; 328 default: 329 apbase = AGP_I810_GMADR; 330 break; 331 } 332 333 if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) { 334 error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase); 335 } else { 336 error = agp_map_aperture(&isc->vga_pa, sc, apbase); 337 } 338 if (error != 0) { 339 aprint_error(": can't map aperture\n"); 340 free(isc, M_AGP); 341 return error; 342 } 343 344 if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33) { 345 error = pci_mapreg_map(&isc->vga_pa, AGP_I915_MMADR, 346 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 347 &mmadr, &mmadrsize); 348 if (error != 0) { 349 aprint_error(": can't map mmadr registers\n"); 350 agp_generic_detach(sc); 351 return error; 352 } 353 error = pci_mapreg_map(&isc->vga_pa, AGP_I915_GTTADR, 354 PCI_MAPREG_TYPE_MEM, 0, &isc->gtt_bst, &isc->gtt_bsh, 355 NULL, NULL); 356 if (error != 0) { 357 aprint_error(": can't map gttadr registers\n"); 358 /* XXX we should release mmadr here */ 359 agp_generic_detach(sc); 360 return error; 361 } 362 } else if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) { 363 error = pci_mapreg_map(&isc->vga_pa, AGP_I965_MMADR, 364 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 365 &mmadr, &mmadrsize); 366 if (error != 0) { 367 aprint_error(": can't map mmadr registers\n"); 368 agp_generic_detach(sc); 369 return error; 370 } 371 } else { 372 error = pci_mapreg_map(&isc->vga_pa, AGP_I810_MMADR, 373 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 374 &mmadr, &mmadrsize); 375 if (error != 0) { 376 aprint_error(": can't map mmadr registers\n"); 377 agp_generic_detach(sc); 378 return error; 379 } 380 } 381 382 isc->initial_aperture = AGP_GET_APERTURE(sc); 383 384 gatt = malloc(sizeof(struct agp_gatt), M_AGP, M_NOWAIT); 385 if (!gatt) { 386 agp_generic_detach(sc); 387 return ENOMEM; 388 } 389 isc->gatt = gatt; 390 391 gatt->ag_entries = AGP_GET_APERTURE(sc) >> AGP_PAGE_SHIFT; 392 393 if (!pmf_device_register(self, NULL, agp_i810_resume)) 394 aprint_error_dev(self, "couldn't establish power handler\n"); 395 396 /* 397 * XXX horrible hack to allow drm code to use our mapping 398 * of VGA chip registers 399 */ 400 agp_i810_vga_regbase = mmadr; 401 agp_i810_vga_bsh = isc->bsh; 402 403 return agp_i810_init(sc); 404 } 405 406 /* 407 * XXX horrible hack to allow drm code to use our mapping 408 * of VGA chip registers 409 */ 410 int 411 agp_i810_borrow(bus_addr_t base, bus_space_handle_t *hdlp) 412 { 413 414 if (!agp_i810_vga_regbase || base != agp_i810_vga_regbase) 415 return 0; 416 *hdlp = agp_i810_vga_bsh; 417 return 1; 418 } 419 420 static int agp_i810_init(struct agp_softc *sc) 421 { 422 struct agp_i810_softc *isc; 423 struct agp_gatt *gatt; 424 425 isc = sc->as_chipc; 426 gatt = isc->gatt; 427 428 if (isc->chiptype == CHIP_I810) { 429 void *virtual; 430 int dummyseg; 431 432 /* Some i810s have on-chip memory called dcache */ 433 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 434 isc->dcache_size = 4 * 1024 * 1024; 435 else 436 isc->dcache_size = 0; 437 438 /* According to the specs the gatt on the i810 must be 64k */ 439 if (agp_alloc_dmamem(sc->as_dmat, 64 * 1024, 440 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical, 441 &gatt->ag_dmaseg, 1, &dummyseg) != 0) { 442 free(gatt, M_AGP); 443 agp_generic_detach(sc); 444 return ENOMEM; 445 } 446 gatt->ag_virtual = (uint32_t *)virtual; 447 gatt->ag_size = gatt->ag_entries * sizeof(u_int32_t); 448 memset(gatt->ag_virtual, 0, gatt->ag_size); 449 450 agp_flush_cache(); 451 /* Install the GATT. */ 452 WRITE4(AGP_I810_PGTBL_CTL, gatt->ag_physical | 1); 453 } else if (isc->chiptype == CHIP_I830) { 454 /* The i830 automatically initializes the 128k gatt on boot. */ 455 pcireg_t reg; 456 u_int32_t pgtblctl; 457 u_int16_t gcc1; 458 459 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 460 gcc1 = (u_int16_t)(reg >> 16); 461 switch (gcc1 & AGP_I830_GCC1_GMS) { 462 case AGP_I830_GCC1_GMS_STOLEN_512: 463 isc->stolen = (512 - 132) * 1024 / 4096; 464 break; 465 case AGP_I830_GCC1_GMS_STOLEN_1024: 466 isc->stolen = (1024 - 132) * 1024 / 4096; 467 break; 468 case AGP_I830_GCC1_GMS_STOLEN_8192: 469 isc->stolen = (8192 - 132) * 1024 / 4096; 470 break; 471 default: 472 isc->stolen = 0; 473 aprint_error( 474 ": unknown memory configuration, disabling\n"); 475 agp_generic_detach(sc); 476 return EINVAL; 477 } 478 479 if (isc->stolen > 0) { 480 aprint_normal(": detected %dk stolen memory\n%s", 481 isc->stolen * 4, device_xname(sc->as_dev)); 482 } 483 484 /* GATT address is already in there, make sure it's enabled */ 485 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 486 pgtblctl |= 1; 487 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 488 489 gatt->ag_physical = pgtblctl & ~1; 490 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 491 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 || 492 isc->chiptype == CHIP_G4X) { 493 pcireg_t reg; 494 u_int32_t pgtblctl, gtt_size, stolen; 495 u_int16_t gcc1; 496 497 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1); 498 gcc1 = (u_int16_t)(reg >> 16); 499 500 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 501 502 /* Stolen memory is set up at the beginning of the aperture by 503 * the BIOS, consisting of the GATT followed by 4kb for the 504 * BIOS display. 505 */ 506 switch (isc->chiptype) { 507 case CHIP_I855: 508 gtt_size = 128; 509 break; 510 case CHIP_I915: 511 gtt_size = 256; 512 break; 513 case CHIP_I965: 514 switch (pgtblctl & AGP_I810_PGTBL_SIZE_MASK) { 515 case AGP_I810_PGTBL_SIZE_128KB: 516 case AGP_I810_PGTBL_SIZE_512KB: 517 gtt_size = 512; 518 break; 519 case AGP_I965_PGTBL_SIZE_1MB: 520 gtt_size = 1024; 521 break; 522 case AGP_I965_PGTBL_SIZE_2MB: 523 gtt_size = 2048; 524 break; 525 case AGP_I965_PGTBL_SIZE_1_5MB: 526 gtt_size = 1024 + 512; 527 break; 528 default: 529 aprint_error("Bad PGTBL size\n"); 530 agp_generic_detach(sc); 531 return EINVAL; 532 } 533 break; 534 case CHIP_G33: 535 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 536 case AGP_G33_PGTBL_SIZE_1M: 537 gtt_size = 1024; 538 break; 539 case AGP_G33_PGTBL_SIZE_2M: 540 gtt_size = 2048; 541 break; 542 default: 543 aprint_error(": Bad PGTBL size\n"); 544 agp_generic_detach(sc); 545 return EINVAL; 546 } 547 break; 548 case CHIP_G4X: 549 gtt_size = 0; 550 break; 551 default: 552 aprint_error(": bad chiptype\n"); 553 agp_generic_detach(sc); 554 return EINVAL; 555 } 556 557 switch (gcc1 & AGP_I855_GCC1_GMS) { 558 case AGP_I855_GCC1_GMS_STOLEN_1M: 559 stolen = 1024; 560 break; 561 case AGP_I855_GCC1_GMS_STOLEN_4M: 562 stolen = 4 * 1024; 563 break; 564 case AGP_I855_GCC1_GMS_STOLEN_8M: 565 stolen = 8 * 1024; 566 break; 567 case AGP_I855_GCC1_GMS_STOLEN_16M: 568 stolen = 16 * 1024; 569 break; 570 case AGP_I855_GCC1_GMS_STOLEN_32M: 571 stolen = 32 * 1024; 572 break; 573 case AGP_I915_GCC1_GMS_STOLEN_48M: 574 stolen = 48 * 1024; 575 break; 576 case AGP_I915_GCC1_GMS_STOLEN_64M: 577 stolen = 64 * 1024; 578 break; 579 case AGP_G33_GCC1_GMS_STOLEN_128M: 580 stolen = 128 * 1024; 581 break; 582 case AGP_G33_GCC1_GMS_STOLEN_256M: 583 stolen = 256 * 1024; 584 break; 585 case AGP_G4X_GCC1_GMS_STOLEN_96M: 586 stolen = 96 * 1024; 587 break; 588 case AGP_G4X_GCC1_GMS_STOLEN_160M: 589 stolen = 160 * 1024; 590 break; 591 case AGP_G4X_GCC1_GMS_STOLEN_224M: 592 stolen = 224 * 1024; 593 break; 594 case AGP_G4X_GCC1_GMS_STOLEN_352M: 595 stolen = 352 * 1024; 596 break; 597 default: 598 aprint_error( 599 ": unknown memory configuration, disabling\n"); 600 agp_generic_detach(sc); 601 return EINVAL; 602 } 603 604 switch (gcc1 & AGP_I855_GCC1_GMS) { 605 case AGP_I915_GCC1_GMS_STOLEN_48M: 606 case AGP_I915_GCC1_GMS_STOLEN_64M: 607 if (isc->chiptype != CHIP_I915 && 608 isc->chiptype != CHIP_I965 && 609 isc->chiptype != CHIP_G33 && 610 isc->chiptype != CHIP_G4X) 611 stolen = 0; 612 break; 613 case AGP_G33_GCC1_GMS_STOLEN_128M: 614 case AGP_G33_GCC1_GMS_STOLEN_256M: 615 if (isc->chiptype != CHIP_I965 && 616 isc->chiptype != CHIP_G33 && 617 isc->chiptype != CHIP_G4X) 618 stolen = 0; 619 break; 620 case AGP_G4X_GCC1_GMS_STOLEN_96M: 621 case AGP_G4X_GCC1_GMS_STOLEN_160M: 622 case AGP_G4X_GCC1_GMS_STOLEN_224M: 623 case AGP_G4X_GCC1_GMS_STOLEN_352M: 624 if (isc->chiptype != CHIP_I965 && 625 isc->chiptype != CHIP_G4X) 626 stolen = 0; 627 break; 628 } 629 630 /* BIOS space */ 631 gtt_size += 4; 632 633 isc->stolen = (stolen - gtt_size) * 1024 / 4096; 634 635 if (isc->stolen > 0) { 636 aprint_normal(": detected %dk stolen memory\n%s", 637 isc->stolen * 4, device_xname(sc->as_dev)); 638 } 639 640 /* GATT address is already in there, make sure it's enabled */ 641 pgtblctl |= 1; 642 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 643 644 gatt->ag_physical = pgtblctl & ~1; 645 } 646 647 /* 648 * Make sure the chipset can see everything. 649 */ 650 agp_flush_cache(); 651 652 return 0; 653 } 654 655 #if 0 656 static int 657 agp_i810_detach(struct agp_softc *sc) 658 { 659 int error; 660 struct agp_i810_softc *isc = sc->as_chipc; 661 662 error = agp_generic_detach(sc); 663 if (error) 664 return error; 665 666 /* Clear the GATT base. */ 667 if (sc->chiptype == CHIP_I810) { 668 WRITE4(AGP_I810_PGTBL_CTL, 0); 669 } else { 670 unsigned int pgtblctl; 671 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 672 pgtblctl &= ~1; 673 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 674 } 675 676 /* Put the aperture back the way it started. */ 677 AGP_SET_APERTURE(sc, isc->initial_aperture); 678 679 if (sc->chiptype == CHIP_I810) { 680 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap, 681 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 682 } 683 free(sc->gatt, M_AGP); 684 685 return 0; 686 } 687 #endif 688 689 static u_int32_t 690 agp_i810_get_aperture(struct agp_softc *sc) 691 { 692 struct agp_i810_softc *isc = sc->as_chipc; 693 pcireg_t reg; 694 u_int32_t size; 695 u_int16_t miscc, gcc1, msac; 696 697 size = 0; 698 699 switch (isc->chiptype) { 700 case CHIP_I810: 701 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 702 miscc = (u_int16_t)(reg >> 16); 703 if ((miscc & AGP_I810_MISCC_WINSIZE) == 704 AGP_I810_MISCC_WINSIZE_32) 705 size = 32 * 1024 * 1024; 706 else 707 size = 64 * 1024 * 1024; 708 break; 709 case CHIP_I830: 710 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 711 gcc1 = (u_int16_t)(reg >> 16); 712 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 713 size = 64 * 1024 * 1024; 714 else 715 size = 128 * 1024 * 1024; 716 break; 717 case CHIP_I855: 718 size = 128 * 1024 * 1024; 719 break; 720 case CHIP_I915: 721 case CHIP_G33: 722 case CHIP_G4X: 723 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I915_MSAC); 724 msac = (u_int16_t)(reg >> 16); 725 if (msac & AGP_I915_MSAC_APER_128M) 726 size = 128 * 1024 * 1024; 727 else 728 size = 256 * 1024 * 1024; 729 break; 730 case CHIP_I965: 731 size = 512 * 1024 * 1024; 732 break; 733 default: 734 aprint_error(": Unknown chipset\n"); 735 } 736 737 return size; 738 } 739 740 static int 741 agp_i810_set_aperture(struct agp_softc *sc, u_int32_t aperture) 742 { 743 struct agp_i810_softc *isc = sc->as_chipc; 744 pcireg_t reg; 745 u_int16_t miscc, gcc1; 746 747 switch (isc->chiptype) { 748 case CHIP_I810: 749 /* 750 * Double check for sanity. 751 */ 752 if (aperture != (32 * 1024 * 1024) && 753 aperture != (64 * 1024 * 1024)) { 754 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 755 aperture); 756 return EINVAL; 757 } 758 759 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 760 miscc = (u_int16_t)(reg >> 16); 761 miscc &= ~AGP_I810_MISCC_WINSIZE; 762 if (aperture == 32 * 1024 * 1024) 763 miscc |= AGP_I810_MISCC_WINSIZE_32; 764 else 765 miscc |= AGP_I810_MISCC_WINSIZE_64; 766 767 reg &= 0x0000ffff; 768 reg |= ((pcireg_t)miscc) << 16; 769 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I810_SMRAM, reg); 770 break; 771 case CHIP_I830: 772 if (aperture != (64 * 1024 * 1024) && 773 aperture != (128 * 1024 * 1024)) { 774 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 775 aperture); 776 return EINVAL; 777 } 778 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 779 gcc1 = (u_int16_t)(reg >> 16); 780 gcc1 &= ~AGP_I830_GCC1_GMASIZE; 781 if (aperture == 64 * 1024 * 1024) 782 gcc1 |= AGP_I830_GCC1_GMASIZE_64; 783 else 784 gcc1 |= AGP_I830_GCC1_GMASIZE_128; 785 786 reg &= 0x0000ffff; 787 reg |= ((pcireg_t)gcc1) << 16; 788 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I830_GCC0, reg); 789 break; 790 case CHIP_I855: 791 case CHIP_I915: 792 if (aperture != agp_i810_get_aperture(sc)) { 793 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 794 aperture); 795 return EINVAL; 796 } 797 break; 798 case CHIP_I965: 799 if (aperture != 512 * 1024 * 1024) { 800 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 801 aperture); 802 return EINVAL; 803 } 804 break; 805 } 806 807 return 0; 808 } 809 810 static int 811 agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 812 { 813 struct agp_i810_softc *isc = sc->as_chipc; 814 815 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) { 816 #ifdef AGP_DEBUG 817 printf("%s: failed: offset 0x%08x, shift %d, entries %d\n", 818 device_xname(sc->as_dev), (int)offset, AGP_PAGE_SHIFT, 819 isc->gatt->ag_entries); 820 #endif 821 return EINVAL; 822 } 823 824 if (isc->chiptype != CHIP_I830) { 825 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 826 #ifdef AGP_DEBUG 827 printf("%s: trying to bind into stolen memory", 828 device_xname(sc->as_dev)); 829 #endif 830 return EINVAL; 831 } 832 } 833 834 agp_i810_write_gtt_entry(isc, offset, physical | 1); 835 return 0; 836 } 837 838 static int 839 agp_i810_unbind_page(struct agp_softc *sc, off_t offset) 840 { 841 struct agp_i810_softc *isc = sc->as_chipc; 842 843 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 844 return EINVAL; 845 846 if (isc->chiptype != CHIP_I810 ) { 847 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 848 #ifdef AGP_DEBUG 849 printf("%s: trying to unbind from stolen memory", 850 device_xname(sc->as_dev)); 851 #endif 852 return EINVAL; 853 } 854 } 855 856 agp_i810_write_gtt_entry(isc, offset, 0); 857 return 0; 858 } 859 860 /* 861 * Writing via memory mapped registers already flushes all TLBs. 862 */ 863 static void 864 agp_i810_flush_tlb(struct agp_softc *sc) 865 { 866 } 867 868 static int 869 agp_i810_enable(struct agp_softc *sc, u_int32_t mode) 870 { 871 872 return 0; 873 } 874 875 static struct agp_memory * 876 agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size) 877 { 878 struct agp_i810_softc *isc = sc->as_chipc; 879 struct agp_memory *mem; 880 881 #ifdef AGP_DEBUG 882 printf("AGP: alloc(%d, 0x%x)\n", type, (int) size); 883 #endif 884 885 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 886 return 0; 887 888 if (sc->as_allocated + size > sc->as_maxmem) 889 return 0; 890 891 if (type == 1) { 892 /* 893 * Mapping local DRAM into GATT. 894 */ 895 if (isc->chiptype != CHIP_I810 ) 896 return 0; 897 if (size != isc->dcache_size) 898 return 0; 899 } else if (type == 2) { 900 /* 901 * Bogus mapping for the hardware cursor. 902 */ 903 if (size != AGP_PAGE_SIZE && size != 4 * AGP_PAGE_SIZE) 904 return 0; 905 } 906 907 mem = malloc(sizeof *mem, M_AGP, M_WAITOK|M_ZERO); 908 if (mem == NULL) 909 return NULL; 910 mem->am_id = sc->as_nextid++; 911 mem->am_size = size; 912 mem->am_type = type; 913 914 if (type == 2) { 915 /* 916 * Allocate and wire down the memory now so that we can 917 * get its physical address. 918 */ 919 mem->am_dmaseg = malloc(sizeof *mem->am_dmaseg, M_AGP, 920 M_WAITOK); 921 if (mem->am_dmaseg == NULL) { 922 free(mem, M_AGP); 923 return NULL; 924 } 925 if (agp_alloc_dmamem(sc->as_dmat, size, 0, 926 &mem->am_dmamap, &mem->am_virtual, &mem->am_physical, 927 mem->am_dmaseg, 1, &mem->am_nseg) != 0) { 928 free(mem->am_dmaseg, M_AGP); 929 free(mem, M_AGP); 930 return NULL; 931 } 932 memset(mem->am_virtual, 0, size); 933 } else if (type != 1) { 934 if (bus_dmamap_create(sc->as_dmat, size, size / PAGE_SIZE + 1, 935 size, 0, BUS_DMA_NOWAIT, 936 &mem->am_dmamap) != 0) { 937 free(mem, M_AGP); 938 return NULL; 939 } 940 } 941 942 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link); 943 sc->as_allocated += size; 944 945 return mem; 946 } 947 948 static int 949 agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem) 950 { 951 if (mem->am_is_bound) 952 return EBUSY; 953 954 if (mem->am_type == 2) { 955 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap, 956 mem->am_virtual, mem->am_dmaseg, mem->am_nseg); 957 free(mem->am_dmaseg, M_AGP); 958 } 959 960 sc->as_allocated -= mem->am_size; 961 TAILQ_REMOVE(&sc->as_memory, mem, am_link); 962 free(mem, M_AGP); 963 return 0; 964 } 965 966 static int 967 agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem, 968 off_t offset) 969 { 970 struct agp_i810_softc *isc = sc->as_chipc; 971 u_int32_t regval, i; 972 973 /* 974 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 975 * X server for mysterious reasons which leads to crashes if we write 976 * to the GTT through the MMIO window. 977 * Until the issue is solved, simply restore it. 978 */ 979 regval = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL); 980 if (regval != (isc->gatt->ag_physical | 1)) { 981 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%x - fixing\n", 982 regval); 983 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 984 isc->gatt->ag_physical | 1); 985 } 986 987 if (mem->am_type == 2) { 988 agp_i810_write_gtt_entry(isc, offset, mem->am_physical | 1); 989 mem->am_offset = offset; 990 mem->am_is_bound = 1; 991 return 0; 992 } 993 994 if (mem->am_type != 1) 995 return agp_generic_bind_memory(sc, mem, offset); 996 997 if (isc->chiptype != CHIP_I810) 998 return EINVAL; 999 1000 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1001 agp_i810_write_gtt_entry(isc, offset, i | 3); 1002 mem->am_is_bound = 1; 1003 return 0; 1004 } 1005 1006 static int 1007 agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem) 1008 { 1009 struct agp_i810_softc *isc = sc->as_chipc; 1010 u_int32_t i; 1011 1012 if (mem->am_type == 2) { 1013 agp_i810_write_gtt_entry(isc, mem->am_offset, 0); 1014 mem->am_offset = 0; 1015 mem->am_is_bound = 0; 1016 return 0; 1017 } 1018 1019 if (mem->am_type != 1) 1020 return agp_generic_unbind_memory(sc, mem); 1021 1022 if (isc->chiptype != CHIP_I810) 1023 return EINVAL; 1024 1025 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1026 agp_i810_write_gtt_entry(isc, i, 0); 1027 mem->am_is_bound = 0; 1028 return 0; 1029 } 1030 1031 static bool 1032 agp_i810_resume(device_t dv, const pmf_qual_t *qual) 1033 { 1034 struct agp_softc *sc = device_private(dv); 1035 struct agp_i810_softc *isc = sc->as_chipc; 1036 1037 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 1038 agp_flush_cache(); 1039 1040 return true; 1041 } 1042
Indexes created Tue Oct 07 21:09:53 GMT 2025