agp_i810.c revision 1.55
1 /* $NetBSD: agp_i810.c,v 1.55 2008/08/19 09:59:54 matthias Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/pci/agp_i810.c,v 1.4 2001/07/05 21:28:47 jhb Exp $ 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.55 2008/08/19 09:59:54 matthias Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/proc.h> 40 #include <sys/device.h> 41 #include <sys/conf.h> 42 43 #include <uvm/uvm_extern.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/agpvar.h> 49 #include <dev/pci/agpreg.h> 50 51 #include <sys/agpio.h> 52 53 #include <sys/bus.h> 54 55 #include "agp_intel.h" 56 57 #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off) 58 #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off) 59 #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v) 60 #define WRITEGTT(off, v) \ 61 do { \ 62 if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33) { \ 63 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, \ 64 (u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4, \ 65 (v)); \ 66 } else if (isc->chiptype == CHIP_I965) { \ 67 WRITE4(AGP_I965_GTT + \ 68 (u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4, \ 69 (v)); \ 70 } else { \ 71 WRITE4(AGP_I810_GTT + \ 72 (u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4, \ 73 (v)); \ 74 } \ 75 } while (0) 76 77 #define CHIP_I810 0 /* i810/i815 */ 78 #define CHIP_I830 1 /* 830M/845G */ 79 #define CHIP_I855 2 /* 852GM/855GM/865G */ 80 #define CHIP_I915 3 /* 915G/915GM/945G/945GM */ 81 #define CHIP_I965 4 /* 965Q/965PM */ 82 #define CHIP_G33 5 /* G33/Q33/Q35 */ 83 84 struct agp_i810_softc { 85 u_int32_t initial_aperture; /* aperture size at startup */ 86 struct agp_gatt *gatt; 87 int chiptype; /* i810-like or i830 */ 88 u_int32_t dcache_size; /* i810 only */ 89 u_int32_t stolen; /* number of i830/845 gtt entries 90 for stolen memory */ 91 bus_space_tag_t bst; /* register bus_space tag */ 92 bus_space_handle_t bsh; /* register bus_space handle */ 93 bus_space_tag_t gtt_bst; /* GTT bus_space tag */ 94 bus_space_handle_t gtt_bsh; /* GTT bus_space handle */ 95 struct pci_attach_args vga_pa; 96 97 u_int32_t pgtblctl; 98 }; 99 100 /* XXX hack, see below */ 101 static bus_addr_t agp_i810_vga_regbase; 102 static bus_space_handle_t agp_i810_vga_bsh; 103 104 static u_int32_t agp_i810_get_aperture(struct agp_softc *); 105 static int agp_i810_set_aperture(struct agp_softc *, u_int32_t); 106 static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t); 107 static int agp_i810_unbind_page(struct agp_softc *, off_t); 108 static void agp_i810_flush_tlb(struct agp_softc *); 109 static int agp_i810_enable(struct agp_softc *, u_int32_t mode); 110 static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int, 111 vsize_t); 112 static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *); 113 static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, off_t); 114 static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *); 115 116 static bool agp_i810_resume(device_t PMF_FN_PROTO); 117 static int agp_i810_init(struct agp_softc *); 118 119 static int agp_i810_init(struct agp_softc *); 120 121 static struct agp_methods agp_i810_methods = { 122 agp_i810_get_aperture, 123 agp_i810_set_aperture, 124 agp_i810_bind_page, 125 agp_i810_unbind_page, 126 agp_i810_flush_tlb, 127 agp_i810_enable, 128 agp_i810_alloc_memory, 129 agp_i810_free_memory, 130 agp_i810_bind_memory, 131 agp_i810_unbind_memory, 132 }; 133 134 /* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */ 135 static int 136 agp_i810_vgamatch(struct pci_attach_args *pa) 137 { 138 139 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 140 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 141 return (0); 142 143 switch (PCI_PRODUCT(pa->pa_id)) { 144 case PCI_PRODUCT_INTEL_82810_GC: 145 case PCI_PRODUCT_INTEL_82810_DC100_GC: 146 case PCI_PRODUCT_INTEL_82810E_GC: 147 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 148 case PCI_PRODUCT_INTEL_82830MP_IV: 149 case PCI_PRODUCT_INTEL_82845G_IGD: 150 case PCI_PRODUCT_INTEL_82855GM_IGD: 151 case PCI_PRODUCT_INTEL_82865_IGD: 152 case PCI_PRODUCT_INTEL_82915G_IGD: 153 case PCI_PRODUCT_INTEL_82915GM_IGD: 154 case PCI_PRODUCT_INTEL_82945P_IGD: 155 case PCI_PRODUCT_INTEL_82945GM_IGD: 156 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 157 case PCI_PRODUCT_INTEL_82965Q_IGD: 158 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 159 case PCI_PRODUCT_INTEL_82965PM_IGD: 160 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 161 case PCI_PRODUCT_INTEL_82G33_IGD: 162 case PCI_PRODUCT_INTEL_82G33_IGD_1: 163 case PCI_PRODUCT_INTEL_82965G_IGD: 164 case PCI_PRODUCT_INTEL_82965G_IGD_1: 165 case PCI_PRODUCT_INTEL_82Q35_IGD: 166 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 167 case PCI_PRODUCT_INTEL_82Q33_IGD: 168 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 169 case PCI_PRODUCT_INTEL_82946GZ_IGD: 170 return (1); 171 } 172 173 return (0); 174 } 175 176 static int 177 agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg) 178 { 179 /* 180 * Find the aperture. Don't map it (yet), this would 181 * eat KVA. 182 */ 183 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 184 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize, 185 &sc->as_apflags) != 0) 186 return ENXIO; 187 188 sc->as_apt = pa->pa_memt; 189 190 return 0; 191 } 192 193 int 194 agp_i810_attach(device_t parent, device_t self, void *aux) 195 { 196 struct agp_softc *sc = device_private(self); 197 struct agp_i810_softc *isc; 198 struct agp_gatt *gatt; 199 int error, apbase; 200 bus_addr_t mmadr; 201 bus_size_t mmadrsize; 202 203 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 204 if (isc == NULL) { 205 aprint_error(": can't allocate chipset-specific softc\n"); 206 return ENOMEM; 207 } 208 sc->as_chipc = isc; 209 sc->as_methods = &agp_i810_methods; 210 211 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) { 212 #if NAGP_INTEL > 0 213 const struct pci_attach_args *pa = aux; 214 215 switch (PCI_PRODUCT(pa->pa_id)) { 216 case PCI_PRODUCT_INTEL_82840_HB: 217 case PCI_PRODUCT_INTEL_82865_HB: 218 case PCI_PRODUCT_INTEL_82845G_DRAM: 219 case PCI_PRODUCT_INTEL_82815_FULL_HUB: 220 return agp_intel_attach(parent, self, aux); 221 } 222 #endif 223 aprint_error(": can't find internal VGA device config space\n"); 224 free(isc, M_AGP); 225 return ENOENT; 226 } 227 228 /* XXXfvdl */ 229 sc->as_dmat = isc->vga_pa.pa_dmat; 230 231 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 232 case PCI_PRODUCT_INTEL_82810_GC: 233 case PCI_PRODUCT_INTEL_82810_DC100_GC: 234 case PCI_PRODUCT_INTEL_82810E_GC: 235 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 236 isc->chiptype = CHIP_I810; 237 break; 238 case PCI_PRODUCT_INTEL_82830MP_IV: 239 case PCI_PRODUCT_INTEL_82845G_IGD: 240 isc->chiptype = CHIP_I830; 241 break; 242 case PCI_PRODUCT_INTEL_82855GM_IGD: 243 case PCI_PRODUCT_INTEL_82865_IGD: 244 isc->chiptype = CHIP_I855; 245 break; 246 case PCI_PRODUCT_INTEL_82915G_IGD: 247 case PCI_PRODUCT_INTEL_82915GM_IGD: 248 case PCI_PRODUCT_INTEL_82945P_IGD: 249 case PCI_PRODUCT_INTEL_82945GM_IGD: 250 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 251 isc->chiptype = CHIP_I915; 252 break; 253 case PCI_PRODUCT_INTEL_82965Q_IGD: 254 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 255 case PCI_PRODUCT_INTEL_82965PM_IGD: 256 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 257 case PCI_PRODUCT_INTEL_82965G_IGD: 258 case PCI_PRODUCT_INTEL_82965G_IGD_1: 259 case PCI_PRODUCT_INTEL_82946GZ_IGD: 260 isc->chiptype = CHIP_I965; 261 break; 262 case PCI_PRODUCT_INTEL_82Q35_IGD: 263 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 264 case PCI_PRODUCT_INTEL_82G33_IGD: 265 case PCI_PRODUCT_INTEL_82G33_IGD_1: 266 case PCI_PRODUCT_INTEL_82Q33_IGD: 267 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 268 isc->chiptype = CHIP_G33; 269 break; 270 } 271 272 switch (isc->chiptype) { 273 case CHIP_I915: 274 case CHIP_G33: 275 apbase = AGP_I915_GMADR; 276 break; 277 default: 278 apbase = AGP_I810_GMADR; 279 break; 280 } 281 if (isc->chiptype == CHIP_I965) { 282 error = agp_i965_map_aperture(&isc->vga_pa, sc, AGP_I965_GMADR); 283 } else { 284 error = agp_map_aperture(&isc->vga_pa, sc, apbase); 285 } 286 if (error != 0) { 287 aprint_error(": can't map aperture\n"); 288 free(isc, M_AGP); 289 return error; 290 } 291 292 if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33) { 293 error = pci_mapreg_map(&isc->vga_pa, AGP_I915_MMADR, 294 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 295 &mmadr, &mmadrsize); 296 if (error != 0) { 297 aprint_error(": can't map mmadr registers\n"); 298 agp_generic_detach(sc); 299 return error; 300 } 301 error = pci_mapreg_map(&isc->vga_pa, AGP_I915_GTTADR, 302 PCI_MAPREG_TYPE_MEM, 0, &isc->gtt_bst, &isc->gtt_bsh, 303 NULL, NULL); 304 if (error != 0) { 305 aprint_error(": can't map gttadr registers\n"); 306 /* XXX we should release mmadr here */ 307 agp_generic_detach(sc); 308 return error; 309 } 310 } else if (isc->chiptype == CHIP_I965) { 311 error = pci_mapreg_map(&isc->vga_pa, AGP_I965_MMADR, 312 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 313 &mmadr, &mmadrsize); 314 if (error != 0) { 315 aprint_error(": can't map mmadr registers\n"); 316 agp_generic_detach(sc); 317 return error; 318 } 319 } else { 320 error = pci_mapreg_map(&isc->vga_pa, AGP_I810_MMADR, 321 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 322 &mmadr, &mmadrsize); 323 if (error != 0) { 324 aprint_error(": can't map mmadr registers\n"); 325 agp_generic_detach(sc); 326 return error; 327 } 328 } 329 330 isc->initial_aperture = AGP_GET_APERTURE(sc); 331 332 gatt = malloc(sizeof(struct agp_gatt), M_AGP, M_NOWAIT); 333 if (!gatt) { 334 agp_generic_detach(sc); 335 return ENOMEM; 336 } 337 isc->gatt = gatt; 338 339 gatt->ag_entries = AGP_GET_APERTURE(sc) >> AGP_PAGE_SHIFT; 340 341 if (!pmf_device_register(self, NULL, agp_i810_resume)) 342 aprint_error_dev(self, "couldn't establish power handler\n"); 343 344 /* 345 * XXX horrible hack to allow drm code to use our mapping 346 * of VGA chip registers 347 */ 348 agp_i810_vga_regbase = mmadr; 349 agp_i810_vga_bsh = isc->bsh; 350 351 return agp_i810_init(sc); 352 } 353 354 /* 355 * XXX horrible hack to allow drm code to use our mapping 356 * of VGA chip registers 357 */ 358 int 359 agp_i810_borrow(bus_addr_t base, bus_space_handle_t *hdlp) 360 { 361 362 if (!agp_i810_vga_regbase || base != agp_i810_vga_regbase) 363 return 0; 364 *hdlp = agp_i810_vga_bsh; 365 return 1; 366 } 367 368 static int agp_i810_init(struct agp_softc *sc) 369 { 370 struct agp_i810_softc *isc; 371 struct agp_gatt *gatt; 372 373 isc = sc->as_chipc; 374 gatt = isc->gatt; 375 376 if (isc->chiptype == CHIP_I810) { 377 void *virtual; 378 int dummyseg; 379 380 /* Some i810s have on-chip memory called dcache */ 381 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 382 isc->dcache_size = 4 * 1024 * 1024; 383 else 384 isc->dcache_size = 0; 385 386 /* According to the specs the gatt on the i810 must be 64k */ 387 if (agp_alloc_dmamem(sc->as_dmat, 64 * 1024, 388 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical, 389 &gatt->ag_dmaseg, 1, &dummyseg) != 0) { 390 free(gatt, M_AGP); 391 agp_generic_detach(sc); 392 return ENOMEM; 393 } 394 gatt->ag_virtual = (uint32_t *)virtual; 395 gatt->ag_size = gatt->ag_entries * sizeof(u_int32_t); 396 memset(gatt->ag_virtual, 0, gatt->ag_size); 397 398 agp_flush_cache(); 399 /* Install the GATT. */ 400 WRITE4(AGP_I810_PGTBL_CTL, gatt->ag_physical | 1); 401 } else if (isc->chiptype == CHIP_I830) { 402 /* The i830 automatically initializes the 128k gatt on boot. */ 403 pcireg_t reg; 404 u_int32_t pgtblctl; 405 u_int16_t gcc1; 406 407 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 408 gcc1 = (u_int16_t)(reg >> 16); 409 switch (gcc1 & AGP_I830_GCC1_GMS) { 410 case AGP_I830_GCC1_GMS_STOLEN_512: 411 isc->stolen = (512 - 132) * 1024 / 4096; 412 break; 413 case AGP_I830_GCC1_GMS_STOLEN_1024: 414 isc->stolen = (1024 - 132) * 1024 / 4096; 415 break; 416 case AGP_I830_GCC1_GMS_STOLEN_8192: 417 isc->stolen = (8192 - 132) * 1024 / 4096; 418 break; 419 default: 420 isc->stolen = 0; 421 aprint_error( 422 ": unknown memory configuration, disabling\n"); 423 agp_generic_detach(sc); 424 return EINVAL; 425 } 426 427 if (isc->stolen > 0) { 428 aprint_normal(": detected %dk stolen memory\n%s", 429 isc->stolen * 4, device_xname(sc->as_dev)); 430 } 431 432 /* GATT address is already in there, make sure it's enabled */ 433 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 434 pgtblctl |= 1; 435 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 436 437 gatt->ag_physical = pgtblctl & ~1; 438 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 439 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33) { 440 pcireg_t reg; 441 u_int32_t pgtblctl, stolen; 442 u_int16_t gcc1; 443 444 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1); 445 gcc1 = (u_int16_t)(reg >> 16); 446 447 /* Stolen memory is set up at the beginning of the aperture by 448 * the BIOS, consisting of the GATT followed by 4kb for the 449 * BIOS display. 450 */ 451 switch (isc->chiptype) { 452 case CHIP_I855: 453 stolen = 128 + 4; 454 break; 455 case CHIP_I915: 456 stolen = 256 + 4; 457 break; 458 case CHIP_I965: 459 stolen = 512 + 4; 460 break; 461 case CHIP_G33: 462 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 463 case AGP_G33_PGTBL_SIZE_1M: 464 stolen = 1024 + 4; 465 break; 466 case AGP_G33_PGTBL_SIZE_2M: 467 stolen = 2048 + 4; 468 break; 469 default: 470 aprint_error(": bad gtt size\n"); 471 agp_generic_detach(sc); 472 return EINVAL; 473 } 474 break; 475 default: 476 aprint_error(": bad chiptype\n"); 477 agp_generic_detach(sc); 478 return EINVAL; 479 } 480 481 switch (gcc1 & AGP_I855_GCC1_GMS) { 482 case AGP_I855_GCC1_GMS_STOLEN_1M: 483 isc->stolen = (1024 - stolen) * 1024 / 4096; 484 break; 485 case AGP_I855_GCC1_GMS_STOLEN_4M: 486 isc->stolen = (4096 - stolen) * 1024 / 4096; 487 break; 488 case AGP_I855_GCC1_GMS_STOLEN_8M: 489 isc->stolen = (8192 - stolen) * 1024 / 4096; 490 break; 491 case AGP_I855_GCC1_GMS_STOLEN_16M: 492 isc->stolen = (16384 - stolen) * 1024 / 4096; 493 break; 494 case AGP_I855_GCC1_GMS_STOLEN_32M: 495 isc->stolen = (32768 - stolen) * 1024 / 4096; 496 break; 497 case AGP_I915_GCC1_GMS_STOLEN_48M: 498 isc->stolen = (49152 - stolen) * 1024 / 4096; 499 break; 500 case AGP_I915_GCC1_GMS_STOLEN_64M: 501 isc->stolen = (65536 - stolen) * 1024 / 4096; 502 break; 503 case AGP_G33_GCC1_GMS_STOLEN_128M: 504 isc->stolen = ((128 * 1024) - stolen) * 1024 / 4096; 505 break; 506 case AGP_G33_GCC1_GMS_STOLEN_256M: 507 isc->stolen = ((256 * 1024) - stolen) * 1024 / 4096; 508 break; 509 default: 510 isc->stolen = 0; 511 aprint_error( 512 ": unknown memory configuration, disabling\n"); 513 agp_generic_detach(sc); 514 return EINVAL; 515 } 516 if (isc->stolen > 0) { 517 aprint_normal(": detected %dk stolen memory\n%s", 518 isc->stolen * 4, device_xname(sc->as_dev)); 519 } 520 521 /* GATT address is already in there, make sure it's enabled */ 522 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 523 pgtblctl |= 1; 524 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 525 526 gatt->ag_physical = pgtblctl & ~1; 527 } 528 529 /* 530 * Make sure the chipset can see everything. 531 */ 532 agp_flush_cache(); 533 534 return 0; 535 } 536 537 #if 0 538 static int 539 agp_i810_detach(struct agp_softc *sc) 540 { 541 int error; 542 struct agp_i810_softc *isc = sc->as_chipc; 543 544 error = agp_generic_detach(sc); 545 if (error) 546 return error; 547 548 /* Clear the GATT base. */ 549 if (sc->chiptype == CHIP_I810) { 550 WRITE4(AGP_I810_PGTBL_CTL, 0); 551 } else { 552 unsigned int pgtblctl; 553 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 554 pgtblctl &= ~1; 555 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 556 } 557 558 /* Put the aperture back the way it started. */ 559 AGP_SET_APERTURE(sc, isc->initial_aperture); 560 561 if (sc->chiptype == CHIP_I810) { 562 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap, 563 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 564 } 565 free(sc->gatt, M_AGP); 566 567 return 0; 568 } 569 #endif 570 571 static u_int32_t 572 agp_i810_get_aperture(struct agp_softc *sc) 573 { 574 struct agp_i810_softc *isc = sc->as_chipc; 575 pcireg_t reg; 576 u_int16_t miscc, gcc1, msac; 577 578 switch (isc->chiptype) { 579 case CHIP_I810: 580 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 581 miscc = (u_int16_t)(reg >> 16); 582 if ((miscc & AGP_I810_MISCC_WINSIZE) == 583 AGP_I810_MISCC_WINSIZE_32) 584 return 32 * 1024 * 1024; 585 else 586 return 64 * 1024 * 1024; 587 case CHIP_I830: 588 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 589 gcc1 = (u_int16_t)(reg >> 16); 590 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 591 return 64 * 1024 * 1024; 592 else 593 return 128 * 1024 * 1024; 594 case CHIP_I855: 595 return 128 * 1024 * 1024; 596 case CHIP_I915: 597 case CHIP_G33: 598 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I915_MSAC); 599 msac = (u_int16_t)(reg >> 16); 600 if (msac & AGP_I915_MSAC_APER_128M) 601 return 128 * 1024 * 1024; 602 else 603 return 256 * 1024 * 1024; 604 case CHIP_I965: 605 return 512 * 1024 * 1024; 606 default: 607 aprint_error(": Unknown chipset\n"); 608 } 609 610 return 0; 611 } 612 613 static int 614 agp_i810_set_aperture(struct agp_softc *sc, u_int32_t aperture) 615 { 616 struct agp_i810_softc *isc = sc->as_chipc; 617 pcireg_t reg; 618 u_int16_t miscc, gcc1; 619 620 switch (isc->chiptype) { 621 case CHIP_I810: 622 /* 623 * Double check for sanity. 624 */ 625 if (aperture != (32 * 1024 * 1024) && 626 aperture != (64 * 1024 * 1024)) { 627 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 628 aperture); 629 return EINVAL; 630 } 631 632 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 633 miscc = (u_int16_t)(reg >> 16); 634 miscc &= ~AGP_I810_MISCC_WINSIZE; 635 if (aperture == 32 * 1024 * 1024) 636 miscc |= AGP_I810_MISCC_WINSIZE_32; 637 else 638 miscc |= AGP_I810_MISCC_WINSIZE_64; 639 640 reg &= 0x0000ffff; 641 reg |= ((pcireg_t)miscc) << 16; 642 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I810_SMRAM, reg); 643 break; 644 case CHIP_I830: 645 if (aperture != (64 * 1024 * 1024) && 646 aperture != (128 * 1024 * 1024)) { 647 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 648 aperture); 649 return EINVAL; 650 } 651 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 652 gcc1 = (u_int16_t)(reg >> 16); 653 gcc1 &= ~AGP_I830_GCC1_GMASIZE; 654 if (aperture == 64 * 1024 * 1024) 655 gcc1 |= AGP_I830_GCC1_GMASIZE_64; 656 else 657 gcc1 |= AGP_I830_GCC1_GMASIZE_128; 658 659 reg &= 0x0000ffff; 660 reg |= ((pcireg_t)gcc1) << 16; 661 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I830_GCC0, reg); 662 break; 663 case CHIP_I855: 664 case CHIP_I915: 665 if (aperture != agp_i810_get_aperture(sc)) { 666 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 667 aperture); 668 return EINVAL; 669 } 670 break; 671 case CHIP_I965: 672 if (aperture != 512 * 1024 * 1024) { 673 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 674 aperture); 675 return EINVAL; 676 } 677 break; 678 } 679 680 return 0; 681 } 682 683 static int 684 agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 685 { 686 struct agp_i810_softc *isc = sc->as_chipc; 687 688 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) { 689 #ifdef AGP_DEBUG 690 printf("%s: failed: offset 0x%08x, shift %d, entries %d\n", 691 device_xname(sc->as_dev), (int)offset, AGP_PAGE_SHIFT, 692 isc->gatt->ag_entries); 693 #endif 694 return EINVAL; 695 } 696 697 if (isc->chiptype != CHIP_I830) { 698 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 699 #ifdef AGP_DEBUG 700 printf("%s: trying to bind into stolen memory", 701 device_xname(sc->as_dev)); 702 #endif 703 return EINVAL; 704 } 705 } 706 707 WRITEGTT(offset, physical | 1); 708 return 0; 709 } 710 711 static int 712 agp_i810_unbind_page(struct agp_softc *sc, off_t offset) 713 { 714 struct agp_i810_softc *isc = sc->as_chipc; 715 716 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 717 return EINVAL; 718 719 if (isc->chiptype != CHIP_I810 ) { 720 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 721 #ifdef AGP_DEBUG 722 printf("%s: trying to unbind from stolen memory", 723 device_xname(sc->as_dev)); 724 #endif 725 return EINVAL; 726 } 727 } 728 729 WRITEGTT(offset, 0); 730 return 0; 731 } 732 733 /* 734 * Writing via memory mapped registers already flushes all TLBs. 735 */ 736 static void 737 agp_i810_flush_tlb(struct agp_softc *sc) 738 { 739 } 740 741 static int 742 agp_i810_enable(struct agp_softc *sc, u_int32_t mode) 743 { 744 745 return 0; 746 } 747 748 static struct agp_memory * 749 agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size) 750 { 751 struct agp_i810_softc *isc = sc->as_chipc; 752 struct agp_memory *mem; 753 754 #ifdef AGP_DEBUG 755 printf("AGP: alloc(%d, 0x%x)\n", type, (int) size); 756 #endif 757 758 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 759 return 0; 760 761 if (sc->as_allocated + size > sc->as_maxmem) 762 return 0; 763 764 if (type == 1) { 765 /* 766 * Mapping local DRAM into GATT. 767 */ 768 if (isc->chiptype != CHIP_I810 ) 769 return 0; 770 if (size != isc->dcache_size) 771 return 0; 772 } else if (type == 2) { 773 /* 774 * Bogus mapping for the hardware cursor. 775 */ 776 if (size != AGP_PAGE_SIZE && size != 4 * AGP_PAGE_SIZE) 777 return 0; 778 } 779 780 mem = malloc(sizeof *mem, M_AGP, M_WAITOK|M_ZERO); 781 if (mem == NULL) 782 return NULL; 783 mem->am_id = sc->as_nextid++; 784 mem->am_size = size; 785 mem->am_type = type; 786 787 if (type == 2) { 788 /* 789 * Allocate and wire down the memory now so that we can 790 * get its physical address. 791 */ 792 mem->am_dmaseg = malloc(sizeof *mem->am_dmaseg, M_AGP, 793 M_WAITOK); 794 if (mem->am_dmaseg == NULL) { 795 free(mem, M_AGP); 796 return NULL; 797 } 798 if (agp_alloc_dmamem(sc->as_dmat, size, 0, 799 &mem->am_dmamap, &mem->am_virtual, &mem->am_physical, 800 mem->am_dmaseg, 1, &mem->am_nseg) != 0) { 801 free(mem->am_dmaseg, M_AGP); 802 free(mem, M_AGP); 803 return NULL; 804 } 805 memset(mem->am_virtual, 0, size); 806 } else if (type != 1) { 807 if (bus_dmamap_create(sc->as_dmat, size, size / PAGE_SIZE + 1, 808 size, 0, BUS_DMA_NOWAIT, 809 &mem->am_dmamap) != 0) { 810 free(mem, M_AGP); 811 return NULL; 812 } 813 } 814 815 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link); 816 sc->as_allocated += size; 817 818 return mem; 819 } 820 821 static int 822 agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem) 823 { 824 if (mem->am_is_bound) 825 return EBUSY; 826 827 if (mem->am_type == 2) { 828 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap, 829 mem->am_virtual, mem->am_dmaseg, mem->am_nseg); 830 free(mem->am_dmaseg, M_AGP); 831 } 832 833 sc->as_allocated -= mem->am_size; 834 TAILQ_REMOVE(&sc->as_memory, mem, am_link); 835 free(mem, M_AGP); 836 return 0; 837 } 838 839 static int 840 agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem, 841 off_t offset) 842 { 843 struct agp_i810_softc *isc = sc->as_chipc; 844 u_int32_t regval, i; 845 846 /* 847 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 848 * X server for mysterious reasons which leads to crashes if we write 849 * to the GTT through the MMIO window. 850 * Until the issue is solved, simply restore it. 851 */ 852 regval = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL); 853 if (regval != (isc->gatt->ag_physical | 1)) { 854 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%x - fixing\n", 855 regval); 856 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 857 isc->gatt->ag_physical | 1); 858 } 859 860 if (mem->am_type == 2) { 861 WRITEGTT(offset, mem->am_physical | 1); 862 mem->am_offset = offset; 863 mem->am_is_bound = 1; 864 return 0; 865 } 866 867 if (mem->am_type != 1) 868 return agp_generic_bind_memory(sc, mem, offset); 869 870 if (isc->chiptype != CHIP_I810) 871 return EINVAL; 872 873 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 874 WRITEGTT(offset, i | 3); 875 mem->am_is_bound = 1; 876 return 0; 877 } 878 879 static int 880 agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem) 881 { 882 struct agp_i810_softc *isc = sc->as_chipc; 883 u_int32_t i; 884 885 if (mem->am_type == 2) { 886 WRITEGTT(mem->am_offset, 0); 887 mem->am_offset = 0; 888 mem->am_is_bound = 0; 889 return 0; 890 } 891 892 if (mem->am_type != 1) 893 return agp_generic_unbind_memory(sc, mem); 894 895 if (isc->chiptype != CHIP_I810) 896 return EINVAL; 897 898 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 899 WRITEGTT(i, 0); 900 mem->am_is_bound = 0; 901 return 0; 902 } 903 904 static bool 905 agp_i810_resume(device_t dv PMF_FN_ARGS) 906 { 907 struct agp_softc *sc = device_private(dv); 908 struct agp_i810_softc *isc = sc->as_chipc; 909 910 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 911 agp_flush_cache(); 912 913 return true; 914 } 915
Indexes created Tue Sep 23 07:09:52 GMT 2025