agp_i810.c revision 1.56
1 /* $NetBSD: agp_i810.c,v 1.56 2008/08/22 18:05:44 tnn Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/pci/agp_i810.c,v 1.4 2001/07/05 21:28:47 jhb Exp $ 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.56 2008/08/22 18:05:44 tnn Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/proc.h> 40 #include <sys/device.h> 41 #include <sys/conf.h> 42 43 #include <uvm/uvm_extern.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/agpvar.h> 49 #include <dev/pci/agpreg.h> 50 51 #include <sys/agpio.h> 52 53 #include <sys/bus.h> 54 55 #include "agp_intel.h" 56 57 #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off) 58 #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off) 59 #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v) 60 #define WRITEGTT(off, v) \ 61 do { \ 62 if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33) { \ 63 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, \ 64 (u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4, \ 65 (v)); \ 66 } else if (isc->chiptype == CHIP_I965) { \ 67 WRITE4(AGP_I965_GTT + \ 68 (u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4, \ 69 (v)); \ 70 } else { \ 71 WRITE4(AGP_I810_GTT + \ 72 (u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4, \ 73 (v)); \ 74 } \ 75 } while (0) 76 77 #define CHIP_I810 0 /* i810/i815 */ 78 #define CHIP_I830 1 /* 830M/845G */ 79 #define CHIP_I855 2 /* 852GM/855GM/865G */ 80 #define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */ 81 #define CHIP_I965 4 /* 965Q/965PM */ 82 #define CHIP_G33 5 /* G33/Q33/Q35 */ 83 84 struct agp_i810_softc { 85 u_int32_t initial_aperture; /* aperture size at startup */ 86 struct agp_gatt *gatt; 87 int chiptype; /* i810-like or i830 */ 88 u_int32_t dcache_size; /* i810 only */ 89 u_int32_t stolen; /* number of i830/845 gtt entries 90 for stolen memory */ 91 bus_space_tag_t bst; /* register bus_space tag */ 92 bus_space_handle_t bsh; /* register bus_space handle */ 93 bus_space_tag_t gtt_bst; /* GTT bus_space tag */ 94 bus_space_handle_t gtt_bsh; /* GTT bus_space handle */ 95 struct pci_attach_args vga_pa; 96 97 u_int32_t pgtblctl; 98 }; 99 100 /* XXX hack, see below */ 101 static bus_addr_t agp_i810_vga_regbase; 102 static bus_space_handle_t agp_i810_vga_bsh; 103 104 static u_int32_t agp_i810_get_aperture(struct agp_softc *); 105 static int agp_i810_set_aperture(struct agp_softc *, u_int32_t); 106 static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t); 107 static int agp_i810_unbind_page(struct agp_softc *, off_t); 108 static void agp_i810_flush_tlb(struct agp_softc *); 109 static int agp_i810_enable(struct agp_softc *, u_int32_t mode); 110 static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int, 111 vsize_t); 112 static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *); 113 static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, off_t); 114 static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *); 115 116 static bool agp_i810_resume(device_t PMF_FN_PROTO); 117 static int agp_i810_init(struct agp_softc *); 118 119 static int agp_i810_init(struct agp_softc *); 120 121 static struct agp_methods agp_i810_methods = { 122 agp_i810_get_aperture, 123 agp_i810_set_aperture, 124 agp_i810_bind_page, 125 agp_i810_unbind_page, 126 agp_i810_flush_tlb, 127 agp_i810_enable, 128 agp_i810_alloc_memory, 129 agp_i810_free_memory, 130 agp_i810_bind_memory, 131 agp_i810_unbind_memory, 132 }; 133 134 /* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */ 135 static int 136 agp_i810_vgamatch(struct pci_attach_args *pa) 137 { 138 139 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 140 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 141 return (0); 142 143 switch (PCI_PRODUCT(pa->pa_id)) { 144 case PCI_PRODUCT_INTEL_82810_GC: 145 case PCI_PRODUCT_INTEL_82810_DC100_GC: 146 case PCI_PRODUCT_INTEL_82810E_GC: 147 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 148 case PCI_PRODUCT_INTEL_82830MP_IV: 149 case PCI_PRODUCT_INTEL_82845G_IGD: 150 case PCI_PRODUCT_INTEL_82855GM_IGD: 151 case PCI_PRODUCT_INTEL_82865_IGD: 152 case PCI_PRODUCT_INTEL_82915G_IGD: 153 case PCI_PRODUCT_INTEL_82915GM_IGD: 154 case PCI_PRODUCT_INTEL_82945P_IGD: 155 case PCI_PRODUCT_INTEL_82945GM_IGD: 156 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 157 case PCI_PRODUCT_INTEL_82945GME_IGD: 158 case PCI_PRODUCT_INTEL_82965Q_IGD: 159 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 160 case PCI_PRODUCT_INTEL_82965PM_IGD: 161 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 162 case PCI_PRODUCT_INTEL_82G33_IGD: 163 case PCI_PRODUCT_INTEL_82G33_IGD_1: 164 case PCI_PRODUCT_INTEL_82965G_IGD: 165 case PCI_PRODUCT_INTEL_82965G_IGD_1: 166 case PCI_PRODUCT_INTEL_82Q35_IGD: 167 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 168 case PCI_PRODUCT_INTEL_82Q33_IGD: 169 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 170 case PCI_PRODUCT_INTEL_82946GZ_IGD: 171 return (1); 172 } 173 174 return (0); 175 } 176 177 static int 178 agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg) 179 { 180 /* 181 * Find the aperture. Don't map it (yet), this would 182 * eat KVA. 183 */ 184 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 185 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize, 186 &sc->as_apflags) != 0) 187 return ENXIO; 188 189 sc->as_apt = pa->pa_memt; 190 191 return 0; 192 } 193 194 int 195 agp_i810_attach(device_t parent, device_t self, void *aux) 196 { 197 struct agp_softc *sc = device_private(self); 198 struct agp_i810_softc *isc; 199 struct agp_gatt *gatt; 200 int error, apbase; 201 bus_addr_t mmadr; 202 bus_size_t mmadrsize; 203 204 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 205 if (isc == NULL) { 206 aprint_error(": can't allocate chipset-specific softc\n"); 207 return ENOMEM; 208 } 209 sc->as_chipc = isc; 210 sc->as_methods = &agp_i810_methods; 211 212 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) { 213 #if NAGP_INTEL > 0 214 const struct pci_attach_args *pa = aux; 215 216 switch (PCI_PRODUCT(pa->pa_id)) { 217 case PCI_PRODUCT_INTEL_82840_HB: 218 case PCI_PRODUCT_INTEL_82865_HB: 219 case PCI_PRODUCT_INTEL_82845G_DRAM: 220 case PCI_PRODUCT_INTEL_82815_FULL_HUB: 221 return agp_intel_attach(parent, self, aux); 222 } 223 #endif 224 aprint_error(": can't find internal VGA device config space\n"); 225 free(isc, M_AGP); 226 return ENOENT; 227 } 228 229 /* XXXfvdl */ 230 sc->as_dmat = isc->vga_pa.pa_dmat; 231 232 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 233 case PCI_PRODUCT_INTEL_82810_GC: 234 case PCI_PRODUCT_INTEL_82810_DC100_GC: 235 case PCI_PRODUCT_INTEL_82810E_GC: 236 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 237 isc->chiptype = CHIP_I810; 238 break; 239 case PCI_PRODUCT_INTEL_82830MP_IV: 240 case PCI_PRODUCT_INTEL_82845G_IGD: 241 isc->chiptype = CHIP_I830; 242 break; 243 case PCI_PRODUCT_INTEL_82855GM_IGD: 244 case PCI_PRODUCT_INTEL_82865_IGD: 245 isc->chiptype = CHIP_I855; 246 break; 247 case PCI_PRODUCT_INTEL_82915G_IGD: 248 case PCI_PRODUCT_INTEL_82915GM_IGD: 249 case PCI_PRODUCT_INTEL_82945P_IGD: 250 case PCI_PRODUCT_INTEL_82945GM_IGD: 251 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 252 case PCI_PRODUCT_INTEL_82945GME_IGD: 253 isc->chiptype = CHIP_I915; 254 break; 255 case PCI_PRODUCT_INTEL_82965Q_IGD: 256 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 257 case PCI_PRODUCT_INTEL_82965PM_IGD: 258 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 259 case PCI_PRODUCT_INTEL_82965G_IGD: 260 case PCI_PRODUCT_INTEL_82965G_IGD_1: 261 case PCI_PRODUCT_INTEL_82946GZ_IGD: 262 isc->chiptype = CHIP_I965; 263 break; 264 case PCI_PRODUCT_INTEL_82Q35_IGD: 265 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 266 case PCI_PRODUCT_INTEL_82G33_IGD: 267 case PCI_PRODUCT_INTEL_82G33_IGD_1: 268 case PCI_PRODUCT_INTEL_82Q33_IGD: 269 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 270 isc->chiptype = CHIP_G33; 271 break; 272 } 273 274 switch (isc->chiptype) { 275 case CHIP_I915: 276 case CHIP_G33: 277 apbase = AGP_I915_GMADR; 278 break; 279 default: 280 apbase = AGP_I810_GMADR; 281 break; 282 } 283 if (isc->chiptype == CHIP_I965) { 284 error = agp_i965_map_aperture(&isc->vga_pa, sc, AGP_I965_GMADR); 285 } else { 286 error = agp_map_aperture(&isc->vga_pa, sc, apbase); 287 } 288 if (error != 0) { 289 aprint_error(": can't map aperture\n"); 290 free(isc, M_AGP); 291 return error; 292 } 293 294 if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33) { 295 error = pci_mapreg_map(&isc->vga_pa, AGP_I915_MMADR, 296 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 297 &mmadr, &mmadrsize); 298 if (error != 0) { 299 aprint_error(": can't map mmadr registers\n"); 300 agp_generic_detach(sc); 301 return error; 302 } 303 error = pci_mapreg_map(&isc->vga_pa, AGP_I915_GTTADR, 304 PCI_MAPREG_TYPE_MEM, 0, &isc->gtt_bst, &isc->gtt_bsh, 305 NULL, NULL); 306 if (error != 0) { 307 aprint_error(": can't map gttadr registers\n"); 308 /* XXX we should release mmadr here */ 309 agp_generic_detach(sc); 310 return error; 311 } 312 } else if (isc->chiptype == CHIP_I965) { 313 error = pci_mapreg_map(&isc->vga_pa, AGP_I965_MMADR, 314 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 315 &mmadr, &mmadrsize); 316 if (error != 0) { 317 aprint_error(": can't map mmadr registers\n"); 318 agp_generic_detach(sc); 319 return error; 320 } 321 } else { 322 error = pci_mapreg_map(&isc->vga_pa, AGP_I810_MMADR, 323 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 324 &mmadr, &mmadrsize); 325 if (error != 0) { 326 aprint_error(": can't map mmadr registers\n"); 327 agp_generic_detach(sc); 328 return error; 329 } 330 } 331 332 isc->initial_aperture = AGP_GET_APERTURE(sc); 333 334 gatt = malloc(sizeof(struct agp_gatt), M_AGP, M_NOWAIT); 335 if (!gatt) { 336 agp_generic_detach(sc); 337 return ENOMEM; 338 } 339 isc->gatt = gatt; 340 341 gatt->ag_entries = AGP_GET_APERTURE(sc) >> AGP_PAGE_SHIFT; 342 343 if (!pmf_device_register(self, NULL, agp_i810_resume)) 344 aprint_error_dev(self, "couldn't establish power handler\n"); 345 346 /* 347 * XXX horrible hack to allow drm code to use our mapping 348 * of VGA chip registers 349 */ 350 agp_i810_vga_regbase = mmadr; 351 agp_i810_vga_bsh = isc->bsh; 352 353 return agp_i810_init(sc); 354 } 355 356 /* 357 * XXX horrible hack to allow drm code to use our mapping 358 * of VGA chip registers 359 */ 360 int 361 agp_i810_borrow(bus_addr_t base, bus_space_handle_t *hdlp) 362 { 363 364 if (!agp_i810_vga_regbase || base != agp_i810_vga_regbase) 365 return 0; 366 *hdlp = agp_i810_vga_bsh; 367 return 1; 368 } 369 370 static int agp_i810_init(struct agp_softc *sc) 371 { 372 struct agp_i810_softc *isc; 373 struct agp_gatt *gatt; 374 375 isc = sc->as_chipc; 376 gatt = isc->gatt; 377 378 if (isc->chiptype == CHIP_I810) { 379 void *virtual; 380 int dummyseg; 381 382 /* Some i810s have on-chip memory called dcache */ 383 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 384 isc->dcache_size = 4 * 1024 * 1024; 385 else 386 isc->dcache_size = 0; 387 388 /* According to the specs the gatt on the i810 must be 64k */ 389 if (agp_alloc_dmamem(sc->as_dmat, 64 * 1024, 390 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical, 391 &gatt->ag_dmaseg, 1, &dummyseg) != 0) { 392 free(gatt, M_AGP); 393 agp_generic_detach(sc); 394 return ENOMEM; 395 } 396 gatt->ag_virtual = (uint32_t *)virtual; 397 gatt->ag_size = gatt->ag_entries * sizeof(u_int32_t); 398 memset(gatt->ag_virtual, 0, gatt->ag_size); 399 400 agp_flush_cache(); 401 /* Install the GATT. */ 402 WRITE4(AGP_I810_PGTBL_CTL, gatt->ag_physical | 1); 403 } else if (isc->chiptype == CHIP_I830) { 404 /* The i830 automatically initializes the 128k gatt on boot. */ 405 pcireg_t reg; 406 u_int32_t pgtblctl; 407 u_int16_t gcc1; 408 409 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 410 gcc1 = (u_int16_t)(reg >> 16); 411 switch (gcc1 & AGP_I830_GCC1_GMS) { 412 case AGP_I830_GCC1_GMS_STOLEN_512: 413 isc->stolen = (512 - 132) * 1024 / 4096; 414 break; 415 case AGP_I830_GCC1_GMS_STOLEN_1024: 416 isc->stolen = (1024 - 132) * 1024 / 4096; 417 break; 418 case AGP_I830_GCC1_GMS_STOLEN_8192: 419 isc->stolen = (8192 - 132) * 1024 / 4096; 420 break; 421 default: 422 isc->stolen = 0; 423 aprint_error( 424 ": unknown memory configuration, disabling\n"); 425 agp_generic_detach(sc); 426 return EINVAL; 427 } 428 429 if (isc->stolen > 0) { 430 aprint_normal(": detected %dk stolen memory\n%s", 431 isc->stolen * 4, device_xname(sc->as_dev)); 432 } 433 434 /* GATT address is already in there, make sure it's enabled */ 435 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 436 pgtblctl |= 1; 437 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 438 439 gatt->ag_physical = pgtblctl & ~1; 440 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 441 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33) { 442 pcireg_t reg; 443 u_int32_t pgtblctl, stolen; 444 u_int16_t gcc1; 445 446 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1); 447 gcc1 = (u_int16_t)(reg >> 16); 448 449 /* Stolen memory is set up at the beginning of the aperture by 450 * the BIOS, consisting of the GATT followed by 4kb for the 451 * BIOS display. 452 */ 453 switch (isc->chiptype) { 454 case CHIP_I855: 455 stolen = 128 + 4; 456 break; 457 case CHIP_I915: 458 stolen = 256 + 4; 459 break; 460 case CHIP_I965: 461 stolen = 512 + 4; 462 break; 463 case CHIP_G33: 464 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 465 case AGP_G33_PGTBL_SIZE_1M: 466 stolen = 1024 + 4; 467 break; 468 case AGP_G33_PGTBL_SIZE_2M: 469 stolen = 2048 + 4; 470 break; 471 default: 472 aprint_error(": bad gtt size\n"); 473 agp_generic_detach(sc); 474 return EINVAL; 475 } 476 break; 477 default: 478 aprint_error(": bad chiptype\n"); 479 agp_generic_detach(sc); 480 return EINVAL; 481 } 482 483 switch (gcc1 & AGP_I855_GCC1_GMS) { 484 case AGP_I855_GCC1_GMS_STOLEN_1M: 485 isc->stolen = (1024 - stolen) * 1024 / 4096; 486 break; 487 case AGP_I855_GCC1_GMS_STOLEN_4M: 488 isc->stolen = (4096 - stolen) * 1024 / 4096; 489 break; 490 case AGP_I855_GCC1_GMS_STOLEN_8M: 491 isc->stolen = (8192 - stolen) * 1024 / 4096; 492 break; 493 case AGP_I855_GCC1_GMS_STOLEN_16M: 494 isc->stolen = (16384 - stolen) * 1024 / 4096; 495 break; 496 case AGP_I855_GCC1_GMS_STOLEN_32M: 497 isc->stolen = (32768 - stolen) * 1024 / 4096; 498 break; 499 case AGP_I915_GCC1_GMS_STOLEN_48M: 500 isc->stolen = (49152 - stolen) * 1024 / 4096; 501 break; 502 case AGP_I915_GCC1_GMS_STOLEN_64M: 503 isc->stolen = (65536 - stolen) * 1024 / 4096; 504 break; 505 case AGP_G33_GCC1_GMS_STOLEN_128M: 506 isc->stolen = ((128 * 1024) - stolen) * 1024 / 4096; 507 break; 508 case AGP_G33_GCC1_GMS_STOLEN_256M: 509 isc->stolen = ((256 * 1024) - stolen) * 1024 / 4096; 510 break; 511 default: 512 isc->stolen = 0; 513 aprint_error( 514 ": unknown memory configuration, disabling\n"); 515 agp_generic_detach(sc); 516 return EINVAL; 517 } 518 if (isc->stolen > 0) { 519 aprint_normal(": detected %dk stolen memory\n%s", 520 isc->stolen * 4, device_xname(sc->as_dev)); 521 } 522 523 /* GATT address is already in there, make sure it's enabled */ 524 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 525 pgtblctl |= 1; 526 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 527 528 gatt->ag_physical = pgtblctl & ~1; 529 } 530 531 /* 532 * Make sure the chipset can see everything. 533 */ 534 agp_flush_cache(); 535 536 return 0; 537 } 538 539 #if 0 540 static int 541 agp_i810_detach(struct agp_softc *sc) 542 { 543 int error; 544 struct agp_i810_softc *isc = sc->as_chipc; 545 546 error = agp_generic_detach(sc); 547 if (error) 548 return error; 549 550 /* Clear the GATT base. */ 551 if (sc->chiptype == CHIP_I810) { 552 WRITE4(AGP_I810_PGTBL_CTL, 0); 553 } else { 554 unsigned int pgtblctl; 555 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 556 pgtblctl &= ~1; 557 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 558 } 559 560 /* Put the aperture back the way it started. */ 561 AGP_SET_APERTURE(sc, isc->initial_aperture); 562 563 if (sc->chiptype == CHIP_I810) { 564 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap, 565 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 566 } 567 free(sc->gatt, M_AGP); 568 569 return 0; 570 } 571 #endif 572 573 static u_int32_t 574 agp_i810_get_aperture(struct agp_softc *sc) 575 { 576 struct agp_i810_softc *isc = sc->as_chipc; 577 pcireg_t reg; 578 u_int16_t miscc, gcc1, msac; 579 580 switch (isc->chiptype) { 581 case CHIP_I810: 582 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 583 miscc = (u_int16_t)(reg >> 16); 584 if ((miscc & AGP_I810_MISCC_WINSIZE) == 585 AGP_I810_MISCC_WINSIZE_32) 586 return 32 * 1024 * 1024; 587 else 588 return 64 * 1024 * 1024; 589 case CHIP_I830: 590 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 591 gcc1 = (u_int16_t)(reg >> 16); 592 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 593 return 64 * 1024 * 1024; 594 else 595 return 128 * 1024 * 1024; 596 case CHIP_I855: 597 return 128 * 1024 * 1024; 598 case CHIP_I915: 599 case CHIP_G33: 600 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I915_MSAC); 601 msac = (u_int16_t)(reg >> 16); 602 if (msac & AGP_I915_MSAC_APER_128M) 603 return 128 * 1024 * 1024; 604 else 605 return 256 * 1024 * 1024; 606 case CHIP_I965: 607 return 512 * 1024 * 1024; 608 default: 609 aprint_error(": Unknown chipset\n"); 610 } 611 612 return 0; 613 } 614 615 static int 616 agp_i810_set_aperture(struct agp_softc *sc, u_int32_t aperture) 617 { 618 struct agp_i810_softc *isc = sc->as_chipc; 619 pcireg_t reg; 620 u_int16_t miscc, gcc1; 621 622 switch (isc->chiptype) { 623 case CHIP_I810: 624 /* 625 * Double check for sanity. 626 */ 627 if (aperture != (32 * 1024 * 1024) && 628 aperture != (64 * 1024 * 1024)) { 629 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 630 aperture); 631 return EINVAL; 632 } 633 634 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 635 miscc = (u_int16_t)(reg >> 16); 636 miscc &= ~AGP_I810_MISCC_WINSIZE; 637 if (aperture == 32 * 1024 * 1024) 638 miscc |= AGP_I810_MISCC_WINSIZE_32; 639 else 640 miscc |= AGP_I810_MISCC_WINSIZE_64; 641 642 reg &= 0x0000ffff; 643 reg |= ((pcireg_t)miscc) << 16; 644 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I810_SMRAM, reg); 645 break; 646 case CHIP_I830: 647 if (aperture != (64 * 1024 * 1024) && 648 aperture != (128 * 1024 * 1024)) { 649 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 650 aperture); 651 return EINVAL; 652 } 653 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 654 gcc1 = (u_int16_t)(reg >> 16); 655 gcc1 &= ~AGP_I830_GCC1_GMASIZE; 656 if (aperture == 64 * 1024 * 1024) 657 gcc1 |= AGP_I830_GCC1_GMASIZE_64; 658 else 659 gcc1 |= AGP_I830_GCC1_GMASIZE_128; 660 661 reg &= 0x0000ffff; 662 reg |= ((pcireg_t)gcc1) << 16; 663 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I830_GCC0, reg); 664 break; 665 case CHIP_I855: 666 case CHIP_I915: 667 if (aperture != agp_i810_get_aperture(sc)) { 668 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 669 aperture); 670 return EINVAL; 671 } 672 break; 673 case CHIP_I965: 674 if (aperture != 512 * 1024 * 1024) { 675 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 676 aperture); 677 return EINVAL; 678 } 679 break; 680 } 681 682 return 0; 683 } 684 685 static int 686 agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 687 { 688 struct agp_i810_softc *isc = sc->as_chipc; 689 690 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) { 691 #ifdef AGP_DEBUG 692 printf("%s: failed: offset 0x%08x, shift %d, entries %d\n", 693 device_xname(sc->as_dev), (int)offset, AGP_PAGE_SHIFT, 694 isc->gatt->ag_entries); 695 #endif 696 return EINVAL; 697 } 698 699 if (isc->chiptype != CHIP_I830) { 700 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 701 #ifdef AGP_DEBUG 702 printf("%s: trying to bind into stolen memory", 703 device_xname(sc->as_dev)); 704 #endif 705 return EINVAL; 706 } 707 } 708 709 WRITEGTT(offset, physical | 1); 710 return 0; 711 } 712 713 static int 714 agp_i810_unbind_page(struct agp_softc *sc, off_t offset) 715 { 716 struct agp_i810_softc *isc = sc->as_chipc; 717 718 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 719 return EINVAL; 720 721 if (isc->chiptype != CHIP_I810 ) { 722 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 723 #ifdef AGP_DEBUG 724 printf("%s: trying to unbind from stolen memory", 725 device_xname(sc->as_dev)); 726 #endif 727 return EINVAL; 728 } 729 } 730 731 WRITEGTT(offset, 0); 732 return 0; 733 } 734 735 /* 736 * Writing via memory mapped registers already flushes all TLBs. 737 */ 738 static void 739 agp_i810_flush_tlb(struct agp_softc *sc) 740 { 741 } 742 743 static int 744 agp_i810_enable(struct agp_softc *sc, u_int32_t mode) 745 { 746 747 return 0; 748 } 749 750 static struct agp_memory * 751 agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size) 752 { 753 struct agp_i810_softc *isc = sc->as_chipc; 754 struct agp_memory *mem; 755 756 #ifdef AGP_DEBUG 757 printf("AGP: alloc(%d, 0x%x)\n", type, (int) size); 758 #endif 759 760 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 761 return 0; 762 763 if (sc->as_allocated + size > sc->as_maxmem) 764 return 0; 765 766 if (type == 1) { 767 /* 768 * Mapping local DRAM into GATT. 769 */ 770 if (isc->chiptype != CHIP_I810 ) 771 return 0; 772 if (size != isc->dcache_size) 773 return 0; 774 } else if (type == 2) { 775 /* 776 * Bogus mapping for the hardware cursor. 777 */ 778 if (size != AGP_PAGE_SIZE && size != 4 * AGP_PAGE_SIZE) 779 return 0; 780 } 781 782 mem = malloc(sizeof *mem, M_AGP, M_WAITOK|M_ZERO); 783 if (mem == NULL) 784 return NULL; 785 mem->am_id = sc->as_nextid++; 786 mem->am_size = size; 787 mem->am_type = type; 788 789 if (type == 2) { 790 /* 791 * Allocate and wire down the memory now so that we can 792 * get its physical address. 793 */ 794 mem->am_dmaseg = malloc(sizeof *mem->am_dmaseg, M_AGP, 795 M_WAITOK); 796 if (mem->am_dmaseg == NULL) { 797 free(mem, M_AGP); 798 return NULL; 799 } 800 if (agp_alloc_dmamem(sc->as_dmat, size, 0, 801 &mem->am_dmamap, &mem->am_virtual, &mem->am_physical, 802 mem->am_dmaseg, 1, &mem->am_nseg) != 0) { 803 free(mem->am_dmaseg, M_AGP); 804 free(mem, M_AGP); 805 return NULL; 806 } 807 memset(mem->am_virtual, 0, size); 808 } else if (type != 1) { 809 if (bus_dmamap_create(sc->as_dmat, size, size / PAGE_SIZE + 1, 810 size, 0, BUS_DMA_NOWAIT, 811 &mem->am_dmamap) != 0) { 812 free(mem, M_AGP); 813 return NULL; 814 } 815 } 816 817 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link); 818 sc->as_allocated += size; 819 820 return mem; 821 } 822 823 static int 824 agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem) 825 { 826 if (mem->am_is_bound) 827 return EBUSY; 828 829 if (mem->am_type == 2) { 830 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap, 831 mem->am_virtual, mem->am_dmaseg, mem->am_nseg); 832 free(mem->am_dmaseg, M_AGP); 833 } 834 835 sc->as_allocated -= mem->am_size; 836 TAILQ_REMOVE(&sc->as_memory, mem, am_link); 837 free(mem, M_AGP); 838 return 0; 839 } 840 841 static int 842 agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem, 843 off_t offset) 844 { 845 struct agp_i810_softc *isc = sc->as_chipc; 846 u_int32_t regval, i; 847 848 /* 849 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 850 * X server for mysterious reasons which leads to crashes if we write 851 * to the GTT through the MMIO window. 852 * Until the issue is solved, simply restore it. 853 */ 854 regval = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL); 855 if (regval != (isc->gatt->ag_physical | 1)) { 856 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%x - fixing\n", 857 regval); 858 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 859 isc->gatt->ag_physical | 1); 860 } 861 862 if (mem->am_type == 2) { 863 WRITEGTT(offset, mem->am_physical | 1); 864 mem->am_offset = offset; 865 mem->am_is_bound = 1; 866 return 0; 867 } 868 869 if (mem->am_type != 1) 870 return agp_generic_bind_memory(sc, mem, offset); 871 872 if (isc->chiptype != CHIP_I810) 873 return EINVAL; 874 875 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 876 WRITEGTT(offset, i | 3); 877 mem->am_is_bound = 1; 878 return 0; 879 } 880 881 static int 882 agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem) 883 { 884 struct agp_i810_softc *isc = sc->as_chipc; 885 u_int32_t i; 886 887 if (mem->am_type == 2) { 888 WRITEGTT(mem->am_offset, 0); 889 mem->am_offset = 0; 890 mem->am_is_bound = 0; 891 return 0; 892 } 893 894 if (mem->am_type != 1) 895 return agp_generic_unbind_memory(sc, mem); 896 897 if (isc->chiptype != CHIP_I810) 898 return EINVAL; 899 900 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 901 WRITEGTT(i, 0); 902 mem->am_is_bound = 0; 903 return 0; 904 } 905 906 static bool 907 agp_i810_resume(device_t dv PMF_FN_ARGS) 908 { 909 struct agp_softc *sc = device_private(dv); 910 struct agp_i810_softc *isc = sc->as_chipc; 911 912 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 913 agp_flush_cache(); 914 915 return true; 916 } 917
Indexes created Thu Sep 25 16:09:42 GMT 2025