agp_i810.c revision 1.58
1 /* $NetBSD: agp_i810.c,v 1.58 2008/11/29 23:48:12 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/pci/agp_i810.c,v 1.4 2001/07/05 21:28:47 jhb Exp $ 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.58 2008/11/29 23:48:12 christos Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/proc.h> 40 #include <sys/device.h> 41 #include <sys/conf.h> 42 43 #include <uvm/uvm_extern.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/agpvar.h> 49 #include <dev/pci/agpreg.h> 50 51 #include <sys/agpio.h> 52 53 #include <sys/bus.h> 54 55 #include "agp_intel.h" 56 57 #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off) 58 #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off) 59 #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v) 60 61 #define CHIP_I810 0 /* i810/i815 */ 62 #define CHIP_I830 1 /* 830M/845G */ 63 #define CHIP_I855 2 /* 852GM/855GM/865G */ 64 #define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */ 65 #define CHIP_I965 4 /* 965Q/965PM */ 66 #define CHIP_G33 5 /* G33/Q33/Q35 */ 67 #define CHIP_G4X 6 /* G45/Q45 */ 68 69 struct agp_i810_softc { 70 u_int32_t initial_aperture; /* aperture size at startup */ 71 struct agp_gatt *gatt; 72 int chiptype; /* i810-like or i830 */ 73 u_int32_t dcache_size; /* i810 only */ 74 u_int32_t stolen; /* number of i830/845 gtt entries 75 for stolen memory */ 76 bus_space_tag_t bst; /* register bus_space tag */ 77 bus_space_handle_t bsh; /* register bus_space handle */ 78 bus_space_tag_t gtt_bst; /* GTT bus_space tag */ 79 bus_space_handle_t gtt_bsh; /* GTT bus_space handle */ 80 struct pci_attach_args vga_pa; 81 82 u_int32_t pgtblctl; 83 }; 84 85 /* XXX hack, see below */ 86 static bus_addr_t agp_i810_vga_regbase; 87 static bus_space_handle_t agp_i810_vga_bsh; 88 89 static u_int32_t agp_i810_get_aperture(struct agp_softc *); 90 static int agp_i810_set_aperture(struct agp_softc *, u_int32_t); 91 static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t); 92 static int agp_i810_unbind_page(struct agp_softc *, off_t); 93 static void agp_i810_flush_tlb(struct agp_softc *); 94 static int agp_i810_enable(struct agp_softc *, u_int32_t mode); 95 static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int, 96 vsize_t); 97 static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *); 98 static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, off_t); 99 static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *); 100 101 static bool agp_i810_resume(device_t PMF_FN_PROTO); 102 static int agp_i810_init(struct agp_softc *); 103 104 static int agp_i810_init(struct agp_softc *); 105 static void agp_i810_write_gtt_entry(struct agp_i810_softc *, off_t, 106 u_int32_t); 107 108 static struct agp_methods agp_i810_methods = { 109 agp_i810_get_aperture, 110 agp_i810_set_aperture, 111 agp_i810_bind_page, 112 agp_i810_unbind_page, 113 agp_i810_flush_tlb, 114 agp_i810_enable, 115 agp_i810_alloc_memory, 116 agp_i810_free_memory, 117 agp_i810_bind_memory, 118 agp_i810_unbind_memory, 119 }; 120 121 static void 122 agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, u_int32_t v) 123 { 124 u_int32_t base_off; 125 126 base_off = 0; 127 128 switch (isc->chiptype) { 129 case CHIP_I810: 130 case CHIP_I830: 131 case CHIP_I855: 132 base_off = AGP_I810_GTT; 133 break; 134 case CHIP_I965: 135 base_off = AGP_I965_GTT; 136 break; 137 case CHIP_G4X: 138 base_off = AGP_G4X_GTT; 139 break; 140 case CHIP_I915: 141 case CHIP_G33: 142 break; 143 } 144 145 WRITE4(base_off + (u_int32_t)(off >> AGP_PAGE_SHIFT) * 4, v); 146 } 147 148 /* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */ 149 static int 150 agp_i810_vgamatch(struct pci_attach_args *pa) 151 { 152 153 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 154 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 155 return (0); 156 157 switch (PCI_PRODUCT(pa->pa_id)) { 158 case PCI_PRODUCT_INTEL_82810_GC: 159 case PCI_PRODUCT_INTEL_82810_DC100_GC: 160 case PCI_PRODUCT_INTEL_82810E_GC: 161 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 162 case PCI_PRODUCT_INTEL_82830MP_IV: 163 case PCI_PRODUCT_INTEL_82845G_IGD: 164 case PCI_PRODUCT_INTEL_82855GM_IGD: 165 case PCI_PRODUCT_INTEL_82865_IGD: 166 case PCI_PRODUCT_INTEL_82915G_IGD: 167 case PCI_PRODUCT_INTEL_82915GM_IGD: 168 case PCI_PRODUCT_INTEL_82945P_IGD: 169 case PCI_PRODUCT_INTEL_82945GM_IGD: 170 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 171 case PCI_PRODUCT_INTEL_82945GME_IGD: 172 case PCI_PRODUCT_INTEL_82965Q_IGD: 173 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 174 case PCI_PRODUCT_INTEL_82965PM_IGD: 175 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 176 case PCI_PRODUCT_INTEL_82G33_IGD: 177 case PCI_PRODUCT_INTEL_82G33_IGD_1: 178 case PCI_PRODUCT_INTEL_82965G_IGD: 179 case PCI_PRODUCT_INTEL_82965G_IGD_1: 180 case PCI_PRODUCT_INTEL_82Q35_IGD: 181 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 182 case PCI_PRODUCT_INTEL_82Q33_IGD: 183 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 184 case PCI_PRODUCT_INTEL_82G35_IGD: 185 case PCI_PRODUCT_INTEL_82G35_IGD_1: 186 case PCI_PRODUCT_INTEL_82946GZ_IGD: 187 case PCI_PRODUCT_INTEL_82GM45_IGD: 188 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 189 return (1); 190 } 191 192 return (0); 193 } 194 195 static int 196 agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg) 197 { 198 /* 199 * Find the aperture. Don't map it (yet), this would 200 * eat KVA. 201 */ 202 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 203 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize, 204 &sc->as_apflags) != 0) 205 return ENXIO; 206 207 sc->as_apt = pa->pa_memt; 208 209 return 0; 210 } 211 212 int 213 agp_i810_attach(device_t parent, device_t self, void *aux) 214 { 215 struct agp_softc *sc = device_private(self); 216 struct agp_i810_softc *isc; 217 struct agp_gatt *gatt; 218 int error, apbase; 219 bus_addr_t mmadr; 220 bus_size_t mmadrsize; 221 222 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 223 if (isc == NULL) { 224 aprint_error(": can't allocate chipset-specific softc\n"); 225 return ENOMEM; 226 } 227 sc->as_chipc = isc; 228 sc->as_methods = &agp_i810_methods; 229 230 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) { 231 #if NAGP_INTEL > 0 232 const struct pci_attach_args *pa = aux; 233 234 switch (PCI_PRODUCT(pa->pa_id)) { 235 case PCI_PRODUCT_INTEL_82840_HB: 236 case PCI_PRODUCT_INTEL_82865_HB: 237 case PCI_PRODUCT_INTEL_82845G_DRAM: 238 case PCI_PRODUCT_INTEL_82815_FULL_HUB: 239 return agp_intel_attach(parent, self, aux); 240 } 241 #endif 242 aprint_error(": can't find internal VGA device config space\n"); 243 free(isc, M_AGP); 244 return ENOENT; 245 } 246 247 /* XXXfvdl */ 248 sc->as_dmat = isc->vga_pa.pa_dmat; 249 250 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 251 case PCI_PRODUCT_INTEL_82810_GC: 252 case PCI_PRODUCT_INTEL_82810_DC100_GC: 253 case PCI_PRODUCT_INTEL_82810E_GC: 254 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 255 isc->chiptype = CHIP_I810; 256 break; 257 case PCI_PRODUCT_INTEL_82830MP_IV: 258 case PCI_PRODUCT_INTEL_82845G_IGD: 259 isc->chiptype = CHIP_I830; 260 break; 261 case PCI_PRODUCT_INTEL_82855GM_IGD: 262 case PCI_PRODUCT_INTEL_82865_IGD: 263 isc->chiptype = CHIP_I855; 264 break; 265 case PCI_PRODUCT_INTEL_82915G_IGD: 266 case PCI_PRODUCT_INTEL_82915GM_IGD: 267 case PCI_PRODUCT_INTEL_82945P_IGD: 268 case PCI_PRODUCT_INTEL_82945GM_IGD: 269 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 270 case PCI_PRODUCT_INTEL_82945GME_IGD: 271 isc->chiptype = CHIP_I915; 272 break; 273 case PCI_PRODUCT_INTEL_82965Q_IGD: 274 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 275 case PCI_PRODUCT_INTEL_82965PM_IGD: 276 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 277 case PCI_PRODUCT_INTEL_82965G_IGD: 278 case PCI_PRODUCT_INTEL_82965G_IGD_1: 279 case PCI_PRODUCT_INTEL_82946GZ_IGD: 280 case PCI_PRODUCT_INTEL_82G35_IGD: 281 case PCI_PRODUCT_INTEL_82G35_IGD_1: 282 isc->chiptype = CHIP_I965; 283 break; 284 case PCI_PRODUCT_INTEL_82Q35_IGD: 285 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 286 case PCI_PRODUCT_INTEL_82G33_IGD: 287 case PCI_PRODUCT_INTEL_82G33_IGD_1: 288 case PCI_PRODUCT_INTEL_82Q33_IGD: 289 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 290 isc->chiptype = CHIP_G33; 291 case PCI_PRODUCT_INTEL_82GM45_IGD: 292 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 293 isc->chiptype = CHIP_G4X; 294 break; 295 } 296 297 switch (isc->chiptype) { 298 case CHIP_I915: 299 case CHIP_G33: 300 apbase = AGP_I915_GMADR; 301 break; 302 case CHIP_I965: 303 case CHIP_G4X: 304 apbase = AGP_I965_GMADR; 305 break; 306 default: 307 apbase = AGP_I810_GMADR; 308 break; 309 } 310 311 if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) { 312 error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase); 313 } else { 314 error = agp_map_aperture(&isc->vga_pa, sc, apbase); 315 } 316 if (error != 0) { 317 aprint_error(": can't map aperture\n"); 318 free(isc, M_AGP); 319 return error; 320 } 321 322 if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33) { 323 error = pci_mapreg_map(&isc->vga_pa, AGP_I915_MMADR, 324 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 325 &mmadr, &mmadrsize); 326 if (error != 0) { 327 aprint_error(": can't map mmadr registers\n"); 328 agp_generic_detach(sc); 329 return error; 330 } 331 error = pci_mapreg_map(&isc->vga_pa, AGP_I915_GTTADR, 332 PCI_MAPREG_TYPE_MEM, 0, &isc->gtt_bst, &isc->gtt_bsh, 333 NULL, NULL); 334 if (error != 0) { 335 aprint_error(": can't map gttadr registers\n"); 336 /* XXX we should release mmadr here */ 337 agp_generic_detach(sc); 338 return error; 339 } 340 } else if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) { 341 error = pci_mapreg_map(&isc->vga_pa, AGP_I965_MMADR, 342 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 343 &mmadr, &mmadrsize); 344 if (error != 0) { 345 aprint_error(": can't map mmadr registers\n"); 346 agp_generic_detach(sc); 347 return error; 348 } 349 } else { 350 error = pci_mapreg_map(&isc->vga_pa, AGP_I810_MMADR, 351 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 352 &mmadr, &mmadrsize); 353 if (error != 0) { 354 aprint_error(": can't map mmadr registers\n"); 355 agp_generic_detach(sc); 356 return error; 357 } 358 } 359 360 isc->initial_aperture = AGP_GET_APERTURE(sc); 361 362 gatt = malloc(sizeof(struct agp_gatt), M_AGP, M_NOWAIT); 363 if (!gatt) { 364 agp_generic_detach(sc); 365 return ENOMEM; 366 } 367 isc->gatt = gatt; 368 369 gatt->ag_entries = AGP_GET_APERTURE(sc) >> AGP_PAGE_SHIFT; 370 371 if (!pmf_device_register(self, NULL, agp_i810_resume)) 372 aprint_error_dev(self, "couldn't establish power handler\n"); 373 374 /* 375 * XXX horrible hack to allow drm code to use our mapping 376 * of VGA chip registers 377 */ 378 agp_i810_vga_regbase = mmadr; 379 agp_i810_vga_bsh = isc->bsh; 380 381 return agp_i810_init(sc); 382 } 383 384 /* 385 * XXX horrible hack to allow drm code to use our mapping 386 * of VGA chip registers 387 */ 388 int 389 agp_i810_borrow(bus_addr_t base, bus_space_handle_t *hdlp) 390 { 391 392 if (!agp_i810_vga_regbase || base != agp_i810_vga_regbase) 393 return 0; 394 *hdlp = agp_i810_vga_bsh; 395 return 1; 396 } 397 398 static int agp_i810_init(struct agp_softc *sc) 399 { 400 struct agp_i810_softc *isc; 401 struct agp_gatt *gatt; 402 403 isc = sc->as_chipc; 404 gatt = isc->gatt; 405 406 if (isc->chiptype == CHIP_I810) { 407 void *virtual; 408 int dummyseg; 409 410 /* Some i810s have on-chip memory called dcache */ 411 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 412 isc->dcache_size = 4 * 1024 * 1024; 413 else 414 isc->dcache_size = 0; 415 416 /* According to the specs the gatt on the i810 must be 64k */ 417 if (agp_alloc_dmamem(sc->as_dmat, 64 * 1024, 418 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical, 419 &gatt->ag_dmaseg, 1, &dummyseg) != 0) { 420 free(gatt, M_AGP); 421 agp_generic_detach(sc); 422 return ENOMEM; 423 } 424 gatt->ag_virtual = (uint32_t *)virtual; 425 gatt->ag_size = gatt->ag_entries * sizeof(u_int32_t); 426 memset(gatt->ag_virtual, 0, gatt->ag_size); 427 428 agp_flush_cache(); 429 /* Install the GATT. */ 430 WRITE4(AGP_I810_PGTBL_CTL, gatt->ag_physical | 1); 431 } else if (isc->chiptype == CHIP_I830) { 432 /* The i830 automatically initializes the 128k gatt on boot. */ 433 pcireg_t reg; 434 u_int32_t pgtblctl; 435 u_int16_t gcc1; 436 437 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 438 gcc1 = (u_int16_t)(reg >> 16); 439 switch (gcc1 & AGP_I830_GCC1_GMS) { 440 case AGP_I830_GCC1_GMS_STOLEN_512: 441 isc->stolen = (512 - 132) * 1024 / 4096; 442 break; 443 case AGP_I830_GCC1_GMS_STOLEN_1024: 444 isc->stolen = (1024 - 132) * 1024 / 4096; 445 break; 446 case AGP_I830_GCC1_GMS_STOLEN_8192: 447 isc->stolen = (8192 - 132) * 1024 / 4096; 448 break; 449 default: 450 isc->stolen = 0; 451 aprint_error( 452 ": unknown memory configuration, disabling\n"); 453 agp_generic_detach(sc); 454 return EINVAL; 455 } 456 457 if (isc->stolen > 0) { 458 aprint_normal(": detected %dk stolen memory\n%s", 459 isc->stolen * 4, device_xname(sc->as_dev)); 460 } 461 462 /* GATT address is already in there, make sure it's enabled */ 463 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 464 pgtblctl |= 1; 465 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 466 467 gatt->ag_physical = pgtblctl & ~1; 468 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 469 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 || 470 isc->chiptype == CHIP_G4X) { 471 pcireg_t reg; 472 u_int32_t pgtblctl, gtt_size, stolen; 473 u_int16_t gcc1; 474 475 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1); 476 gcc1 = (u_int16_t)(reg >> 16); 477 478 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 479 480 /* Stolen memory is set up at the beginning of the aperture by 481 * the BIOS, consisting of the GATT followed by 4kb for the 482 * BIOS display. 483 */ 484 switch (isc->chiptype) { 485 case CHIP_I855: 486 gtt_size = 128; 487 break; 488 case CHIP_I915: 489 gtt_size = 256; 490 break; 491 case CHIP_I965: 492 switch (pgtblctl) { 493 case AGP_I810_PGTBL_SIZE_128KB: 494 case AGP_I810_PGTBL_SIZE_512KB: 495 gtt_size = 512; 496 break; 497 case AGP_I965_PGTBL_SIZE_1MB: 498 gtt_size = 1024; 499 break; 500 case AGP_I965_PGTBL_SIZE_2MB: 501 gtt_size = 1024; 502 break; 503 case AGP_I965_PGTBL_SIZE_1_5MB: 504 gtt_size = 1024; 505 break; 506 default: 507 aprint_error("Bad PGTBL size\n"); 508 agp_generic_detach(sc); 509 return EINVAL; 510 } 511 break; 512 case CHIP_G33: 513 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 514 case AGP_G33_PGTBL_SIZE_1M: 515 gtt_size = 1024; 516 break; 517 case AGP_G33_PGTBL_SIZE_2M: 518 gtt_size = 2048; 519 break; 520 default: 521 aprint_error(": Bad PGTBL size\n"); 522 agp_generic_detach(sc); 523 return EINVAL; 524 } 525 break; 526 case CHIP_G4X: 527 gtt_size = 0; 528 break; 529 default: 530 aprint_error(": bad chiptype\n"); 531 agp_generic_detach(sc); 532 return EINVAL; 533 } 534 535 switch (gcc1 & AGP_I855_GCC1_GMS) { 536 case AGP_I855_GCC1_GMS_STOLEN_1M: 537 stolen = 1024; 538 break; 539 case AGP_I855_GCC1_GMS_STOLEN_4M: 540 stolen = 4 * 1024; 541 break; 542 case AGP_I855_GCC1_GMS_STOLEN_8M: 543 stolen = 8 * 1024; 544 break; 545 case AGP_I855_GCC1_GMS_STOLEN_16M: 546 stolen = 16 * 1024; 547 break; 548 case AGP_I855_GCC1_GMS_STOLEN_32M: 549 stolen = 32 * 1024; 550 break; 551 case AGP_I915_GCC1_GMS_STOLEN_48M: 552 stolen = 48 * 1024; 553 break; 554 case AGP_I915_GCC1_GMS_STOLEN_64M: 555 stolen = 64 * 1024; 556 break; 557 case AGP_G33_GCC1_GMS_STOLEN_128M: 558 stolen = 128 * 1024; 559 break; 560 case AGP_G33_GCC1_GMS_STOLEN_256M: 561 stolen = 256 * 1024; 562 break; 563 case AGP_G4X_GCC1_GMS_STOLEN_96M: 564 stolen = 96 * 1024; 565 break; 566 case AGP_G4X_GCC1_GMS_STOLEN_160M: 567 stolen = 160 * 1024; 568 break; 569 case AGP_G4X_GCC1_GMS_STOLEN_224M: 570 stolen = 224 * 1024; 571 break; 572 case AGP_G4X_GCC1_GMS_STOLEN_352M: 573 stolen = 352 * 1024; 574 break; 575 default: 576 aprint_error( 577 ": unknown memory configuration, disabling\n"); 578 agp_generic_detach(sc); 579 return EINVAL; 580 } 581 582 switch (gcc1 & AGP_I855_GCC1_GMS) { 583 case AGP_I915_GCC1_GMS_STOLEN_48M: 584 case AGP_I915_GCC1_GMS_STOLEN_64M: 585 if (isc->chiptype != CHIP_I915 && 586 isc->chiptype != CHIP_I965 && 587 isc->chiptype != CHIP_G33 && 588 isc->chiptype != CHIP_G4X) 589 stolen = 0; 590 break; 591 case AGP_G33_GCC1_GMS_STOLEN_128M: 592 case AGP_G33_GCC1_GMS_STOLEN_256M: 593 if (isc->chiptype != CHIP_I965 && 594 isc->chiptype != CHIP_G33 && 595 isc->chiptype != CHIP_G4X) 596 stolen = 0; 597 break; 598 case AGP_G4X_GCC1_GMS_STOLEN_96M: 599 case AGP_G4X_GCC1_GMS_STOLEN_160M: 600 case AGP_G4X_GCC1_GMS_STOLEN_224M: 601 case AGP_G4X_GCC1_GMS_STOLEN_352M: 602 if (isc->chiptype != CHIP_I965 && 603 isc->chiptype != CHIP_G4X) 604 stolen = 0; 605 break; 606 } 607 608 /* BIOS space */ 609 if (isc->chiptype != CHIP_G4X) 610 gtt_size += 4; 611 612 isc->stolen = (stolen - gtt_size) * 1024 / 4096; 613 614 if (isc->stolen > 0) { 615 aprint_normal(": detected %dk stolen memory\n%s", 616 isc->stolen * 4, device_xname(sc->as_dev)); 617 } 618 619 /* GATT address is already in there, make sure it's enabled */ 620 pgtblctl |= 1; 621 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 622 623 gatt->ag_physical = pgtblctl & ~1; 624 } 625 626 /* 627 * Make sure the chipset can see everything. 628 */ 629 agp_flush_cache(); 630 631 return 0; 632 } 633 634 #if 0 635 static int 636 agp_i810_detach(struct agp_softc *sc) 637 { 638 int error; 639 struct agp_i810_softc *isc = sc->as_chipc; 640 641 error = agp_generic_detach(sc); 642 if (error) 643 return error; 644 645 /* Clear the GATT base. */ 646 if (sc->chiptype == CHIP_I810) { 647 WRITE4(AGP_I810_PGTBL_CTL, 0); 648 } else { 649 unsigned int pgtblctl; 650 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 651 pgtblctl &= ~1; 652 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 653 } 654 655 /* Put the aperture back the way it started. */ 656 AGP_SET_APERTURE(sc, isc->initial_aperture); 657 658 if (sc->chiptype == CHIP_I810) { 659 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap, 660 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 661 } 662 free(sc->gatt, M_AGP); 663 664 return 0; 665 } 666 #endif 667 668 static u_int32_t 669 agp_i810_get_aperture(struct agp_softc *sc) 670 { 671 struct agp_i810_softc *isc = sc->as_chipc; 672 pcireg_t reg; 673 u_int32_t size; 674 u_int16_t miscc, gcc1, msac; 675 676 size = 0; 677 678 switch (isc->chiptype) { 679 case CHIP_I810: 680 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 681 miscc = (u_int16_t)(reg >> 16); 682 if ((miscc & AGP_I810_MISCC_WINSIZE) == 683 AGP_I810_MISCC_WINSIZE_32) 684 size = 32 * 1024 * 1024; 685 else 686 size = 64 * 1024 * 1024; 687 break; 688 case CHIP_I830: 689 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 690 gcc1 = (u_int16_t)(reg >> 16); 691 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 692 size = 64 * 1024 * 1024; 693 else 694 size = 128 * 1024 * 1024; 695 break; 696 case CHIP_I855: 697 size = 128 * 1024 * 1024; 698 break; 699 case CHIP_I915: 700 case CHIP_G33: 701 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I915_MSAC); 702 msac = (u_int16_t)(reg >> 16); 703 if (msac & AGP_I915_MSAC_APER_128M) 704 size = 128 * 1024 * 1024; 705 else 706 size = 256 * 1024 * 1024; 707 break; 708 case CHIP_I965: 709 size = 512 * 1024 * 1024; 710 break; 711 case CHIP_G4X: 712 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_G4X_MSAC); 713 msac = (u_int16_t)(reg >> 16); 714 switch (msac & AGP_G4X_MSAC_MASK) { 715 case AGP_G4X_MSAC_APER_256M: 716 size = 256 * 1024 * 1024; 717 case AGP_G4X_MSAC_APER_512M: 718 size = 512 * 1024 * 1024; 719 } 720 break; 721 default: 722 aprint_error(": Unknown chipset\n"); 723 } 724 725 return size; 726 } 727 728 static int 729 agp_i810_set_aperture(struct agp_softc *sc, u_int32_t aperture) 730 { 731 struct agp_i810_softc *isc = sc->as_chipc; 732 pcireg_t reg; 733 u_int16_t miscc, gcc1; 734 735 switch (isc->chiptype) { 736 case CHIP_I810: 737 /* 738 * Double check for sanity. 739 */ 740 if (aperture != (32 * 1024 * 1024) && 741 aperture != (64 * 1024 * 1024)) { 742 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 743 aperture); 744 return EINVAL; 745 } 746 747 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 748 miscc = (u_int16_t)(reg >> 16); 749 miscc &= ~AGP_I810_MISCC_WINSIZE; 750 if (aperture == 32 * 1024 * 1024) 751 miscc |= AGP_I810_MISCC_WINSIZE_32; 752 else 753 miscc |= AGP_I810_MISCC_WINSIZE_64; 754 755 reg &= 0x0000ffff; 756 reg |= ((pcireg_t)miscc) << 16; 757 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I810_SMRAM, reg); 758 break; 759 case CHIP_I830: 760 if (aperture != (64 * 1024 * 1024) && 761 aperture != (128 * 1024 * 1024)) { 762 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 763 aperture); 764 return EINVAL; 765 } 766 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 767 gcc1 = (u_int16_t)(reg >> 16); 768 gcc1 &= ~AGP_I830_GCC1_GMASIZE; 769 if (aperture == 64 * 1024 * 1024) 770 gcc1 |= AGP_I830_GCC1_GMASIZE_64; 771 else 772 gcc1 |= AGP_I830_GCC1_GMASIZE_128; 773 774 reg &= 0x0000ffff; 775 reg |= ((pcireg_t)gcc1) << 16; 776 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I830_GCC0, reg); 777 break; 778 case CHIP_I855: 779 case CHIP_I915: 780 if (aperture != agp_i810_get_aperture(sc)) { 781 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 782 aperture); 783 return EINVAL; 784 } 785 break; 786 case CHIP_I965: 787 if (aperture != 512 * 1024 * 1024) { 788 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 789 aperture); 790 return EINVAL; 791 } 792 break; 793 } 794 795 return 0; 796 } 797 798 static int 799 agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 800 { 801 struct agp_i810_softc *isc = sc->as_chipc; 802 803 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) { 804 #ifdef AGP_DEBUG 805 printf("%s: failed: offset 0x%08x, shift %d, entries %d\n", 806 device_xname(sc->as_dev), (int)offset, AGP_PAGE_SHIFT, 807 isc->gatt->ag_entries); 808 #endif 809 return EINVAL; 810 } 811 812 if (isc->chiptype != CHIP_I830) { 813 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 814 #ifdef AGP_DEBUG 815 printf("%s: trying to bind into stolen memory", 816 device_xname(sc->as_dev)); 817 #endif 818 return EINVAL; 819 } 820 } 821 822 agp_i810_write_gtt_entry(isc, offset, physical | 1); 823 return 0; 824 } 825 826 static int 827 agp_i810_unbind_page(struct agp_softc *sc, off_t offset) 828 { 829 struct agp_i810_softc *isc = sc->as_chipc; 830 831 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 832 return EINVAL; 833 834 if (isc->chiptype != CHIP_I810 ) { 835 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 836 #ifdef AGP_DEBUG 837 printf("%s: trying to unbind from stolen memory", 838 device_xname(sc->as_dev)); 839 #endif 840 return EINVAL; 841 } 842 } 843 844 agp_i810_write_gtt_entry(isc, offset, 0); 845 return 0; 846 } 847 848 /* 849 * Writing via memory mapped registers already flushes all TLBs. 850 */ 851 static void 852 agp_i810_flush_tlb(struct agp_softc *sc) 853 { 854 } 855 856 static int 857 agp_i810_enable(struct agp_softc *sc, u_int32_t mode) 858 { 859 860 return 0; 861 } 862 863 static struct agp_memory * 864 agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size) 865 { 866 struct agp_i810_softc *isc = sc->as_chipc; 867 struct agp_memory *mem; 868 869 #ifdef AGP_DEBUG 870 printf("AGP: alloc(%d, 0x%x)\n", type, (int) size); 871 #endif 872 873 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 874 return 0; 875 876 if (sc->as_allocated + size > sc->as_maxmem) 877 return 0; 878 879 if (type == 1) { 880 /* 881 * Mapping local DRAM into GATT. 882 */ 883 if (isc->chiptype != CHIP_I810 ) 884 return 0; 885 if (size != isc->dcache_size) 886 return 0; 887 } else if (type == 2) { 888 /* 889 * Bogus mapping for the hardware cursor. 890 */ 891 if (size != AGP_PAGE_SIZE && size != 4 * AGP_PAGE_SIZE) 892 return 0; 893 } 894 895 mem = malloc(sizeof *mem, M_AGP, M_WAITOK|M_ZERO); 896 if (mem == NULL) 897 return NULL; 898 mem->am_id = sc->as_nextid++; 899 mem->am_size = size; 900 mem->am_type = type; 901 902 if (type == 2) { 903 /* 904 * Allocate and wire down the memory now so that we can 905 * get its physical address. 906 */ 907 mem->am_dmaseg = malloc(sizeof *mem->am_dmaseg, M_AGP, 908 M_WAITOK); 909 if (mem->am_dmaseg == NULL) { 910 free(mem, M_AGP); 911 return NULL; 912 } 913 if (agp_alloc_dmamem(sc->as_dmat, size, 0, 914 &mem->am_dmamap, &mem->am_virtual, &mem->am_physical, 915 mem->am_dmaseg, 1, &mem->am_nseg) != 0) { 916 free(mem->am_dmaseg, M_AGP); 917 free(mem, M_AGP); 918 return NULL; 919 } 920 memset(mem->am_virtual, 0, size); 921 } else if (type != 1) { 922 if (bus_dmamap_create(sc->as_dmat, size, size / PAGE_SIZE + 1, 923 size, 0, BUS_DMA_NOWAIT, 924 &mem->am_dmamap) != 0) { 925 free(mem, M_AGP); 926 return NULL; 927 } 928 } 929 930 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link); 931 sc->as_allocated += size; 932 933 return mem; 934 } 935 936 static int 937 agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem) 938 { 939 if (mem->am_is_bound) 940 return EBUSY; 941 942 if (mem->am_type == 2) { 943 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap, 944 mem->am_virtual, mem->am_dmaseg, mem->am_nseg); 945 free(mem->am_dmaseg, M_AGP); 946 } 947 948 sc->as_allocated -= mem->am_size; 949 TAILQ_REMOVE(&sc->as_memory, mem, am_link); 950 free(mem, M_AGP); 951 return 0; 952 } 953 954 static int 955 agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem, 956 off_t offset) 957 { 958 struct agp_i810_softc *isc = sc->as_chipc; 959 u_int32_t regval, i; 960 961 /* 962 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 963 * X server for mysterious reasons which leads to crashes if we write 964 * to the GTT through the MMIO window. 965 * Until the issue is solved, simply restore it. 966 */ 967 regval = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL); 968 if (regval != (isc->gatt->ag_physical | 1)) { 969 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%x - fixing\n", 970 regval); 971 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 972 isc->gatt->ag_physical | 1); 973 } 974 975 if (mem->am_type == 2) { 976 agp_i810_write_gtt_entry(isc, offset, mem->am_physical | 1); 977 mem->am_offset = offset; 978 mem->am_is_bound = 1; 979 return 0; 980 } 981 982 if (mem->am_type != 1) 983 return agp_generic_bind_memory(sc, mem, offset); 984 985 if (isc->chiptype != CHIP_I810) 986 return EINVAL; 987 988 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 989 agp_i810_write_gtt_entry(isc, offset, i | 3); 990 mem->am_is_bound = 1; 991 return 0; 992 } 993 994 static int 995 agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem) 996 { 997 struct agp_i810_softc *isc = sc->as_chipc; 998 u_int32_t i; 999 1000 if (mem->am_type == 2) { 1001 agp_i810_write_gtt_entry(isc, mem->am_offset, 0); 1002 mem->am_offset = 0; 1003 mem->am_is_bound = 0; 1004 return 0; 1005 } 1006 1007 if (mem->am_type != 1) 1008 return agp_generic_unbind_memory(sc, mem); 1009 1010 if (isc->chiptype != CHIP_I810) 1011 return EINVAL; 1012 1013 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1014 agp_i810_write_gtt_entry(isc, i, 0); 1015 mem->am_is_bound = 0; 1016 return 0; 1017 } 1018 1019 static bool 1020 agp_i810_resume(device_t dv PMF_FN_ARGS) 1021 { 1022 struct agp_softc *sc = device_private(dv); 1023 struct agp_i810_softc *isc = sc->as_chipc; 1024 1025 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 1026 agp_flush_cache(); 1027 1028 return true; 1029 } 1030
Indexes created Fri Sep 26 20:09:58 GMT 2025