agp_i810.c revision 1.61
1 /* $NetBSD: agp_i810.c,v 1.61 2008/12/13 20:12:13 sketch Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/pci/agp_i810.c,v 1.4 2001/07/05 21:28:47 jhb Exp $ 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.61 2008/12/13 20:12:13 sketch Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/proc.h> 40 #include <sys/device.h> 41 #include <sys/conf.h> 42 43 #include <uvm/uvm_extern.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/agpvar.h> 49 #include <dev/pci/agpreg.h> 50 51 #include <sys/agpio.h> 52 53 #include <sys/bus.h> 54 55 #include "agp_intel.h" 56 57 #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off) 58 #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off) 59 #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v) 60 61 #define CHIP_I810 0 /* i810/i815 */ 62 #define CHIP_I830 1 /* 830M/845G */ 63 #define CHIP_I855 2 /* 852GM/855GM/865G */ 64 #define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */ 65 #define CHIP_I965 4 /* 965Q/965PM */ 66 #define CHIP_G33 5 /* G33/Q33/Q35 */ 67 #define CHIP_G4X 6 /* G45/Q45 */ 68 69 struct agp_i810_softc { 70 u_int32_t initial_aperture; /* aperture size at startup */ 71 struct agp_gatt *gatt; 72 int chiptype; /* i810-like or i830 */ 73 u_int32_t dcache_size; /* i810 only */ 74 u_int32_t stolen; /* number of i830/845 gtt entries 75 for stolen memory */ 76 bus_space_tag_t bst; /* register bus_space tag */ 77 bus_space_handle_t bsh; /* register bus_space handle */ 78 bus_space_tag_t gtt_bst; /* GTT bus_space tag */ 79 bus_space_handle_t gtt_bsh; /* GTT bus_space handle */ 80 struct pci_attach_args vga_pa; 81 82 u_int32_t pgtblctl; 83 }; 84 85 /* XXX hack, see below */ 86 static bus_addr_t agp_i810_vga_regbase; 87 static bus_space_handle_t agp_i810_vga_bsh; 88 89 static u_int32_t agp_i810_get_aperture(struct agp_softc *); 90 static int agp_i810_set_aperture(struct agp_softc *, u_int32_t); 91 static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t); 92 static int agp_i810_unbind_page(struct agp_softc *, off_t); 93 static void agp_i810_flush_tlb(struct agp_softc *); 94 static int agp_i810_enable(struct agp_softc *, u_int32_t mode); 95 static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int, 96 vsize_t); 97 static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *); 98 static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, off_t); 99 static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *); 100 101 static bool agp_i810_resume(device_t PMF_FN_PROTO); 102 static int agp_i810_init(struct agp_softc *); 103 104 static int agp_i810_init(struct agp_softc *); 105 static void agp_i810_write_gtt_entry(struct agp_i810_softc *, off_t, 106 u_int32_t); 107 108 static struct agp_methods agp_i810_methods = { 109 agp_i810_get_aperture, 110 agp_i810_set_aperture, 111 agp_i810_bind_page, 112 agp_i810_unbind_page, 113 agp_i810_flush_tlb, 114 agp_i810_enable, 115 agp_i810_alloc_memory, 116 agp_i810_free_memory, 117 agp_i810_bind_memory, 118 agp_i810_unbind_memory, 119 }; 120 121 static void 122 agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, u_int32_t v) 123 { 124 u_int32_t base_off; 125 126 base_off = 0; 127 128 switch (isc->chiptype) { 129 case CHIP_I810: 130 case CHIP_I830: 131 case CHIP_I855: 132 base_off = AGP_I810_GTT; 133 break; 134 case CHIP_I965: 135 base_off = AGP_I965_GTT; 136 break; 137 case CHIP_G4X: 138 base_off = AGP_G4X_GTT; 139 break; 140 case CHIP_I915: 141 case CHIP_G33: 142 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, 143 (u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4, (v)); 144 return; 145 } 146 147 WRITE4(base_off + (u_int32_t)(off >> AGP_PAGE_SHIFT) * 4, v); 148 } 149 150 /* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */ 151 static int 152 agp_i810_vgamatch(struct pci_attach_args *pa) 153 { 154 155 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 156 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 157 return (0); 158 159 switch (PCI_PRODUCT(pa->pa_id)) { 160 case PCI_PRODUCT_INTEL_82810_GC: 161 case PCI_PRODUCT_INTEL_82810_DC100_GC: 162 case PCI_PRODUCT_INTEL_82810E_GC: 163 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 164 case PCI_PRODUCT_INTEL_82830MP_IV: 165 case PCI_PRODUCT_INTEL_82845G_IGD: 166 case PCI_PRODUCT_INTEL_82855GM_IGD: 167 case PCI_PRODUCT_INTEL_82865_IGD: 168 case PCI_PRODUCT_INTEL_82915G_IGD: 169 case PCI_PRODUCT_INTEL_82915GM_IGD: 170 case PCI_PRODUCT_INTEL_82945P_IGD: 171 case PCI_PRODUCT_INTEL_82945GM_IGD: 172 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 173 case PCI_PRODUCT_INTEL_82945GME_IGD: 174 case PCI_PRODUCT_INTEL_82965Q_IGD: 175 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 176 case PCI_PRODUCT_INTEL_82965PM_IGD: 177 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 178 case PCI_PRODUCT_INTEL_82G33_IGD: 179 case PCI_PRODUCT_INTEL_82G33_IGD_1: 180 case PCI_PRODUCT_INTEL_82965G_IGD: 181 case PCI_PRODUCT_INTEL_82965G_IGD_1: 182 case PCI_PRODUCT_INTEL_82Q35_IGD: 183 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 184 case PCI_PRODUCT_INTEL_82Q33_IGD: 185 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 186 case PCI_PRODUCT_INTEL_82G35_IGD: 187 case PCI_PRODUCT_INTEL_82G35_IGD_1: 188 case PCI_PRODUCT_INTEL_82946GZ_IGD: 189 case PCI_PRODUCT_INTEL_82GM45_IGD: 190 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 191 return (1); 192 } 193 194 return (0); 195 } 196 197 static int 198 agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg) 199 { 200 /* 201 * Find the aperture. Don't map it (yet), this would 202 * eat KVA. 203 */ 204 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 205 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize, 206 &sc->as_apflags) != 0) 207 return ENXIO; 208 209 sc->as_apt = pa->pa_memt; 210 211 return 0; 212 } 213 214 int 215 agp_i810_attach(device_t parent, device_t self, void *aux) 216 { 217 struct agp_softc *sc = device_private(self); 218 struct agp_i810_softc *isc; 219 struct agp_gatt *gatt; 220 int error, apbase; 221 bus_addr_t mmadr; 222 bus_size_t mmadrsize; 223 224 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 225 if (isc == NULL) { 226 aprint_error(": can't allocate chipset-specific softc\n"); 227 return ENOMEM; 228 } 229 sc->as_chipc = isc; 230 sc->as_methods = &agp_i810_methods; 231 232 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) { 233 #if NAGP_INTEL > 0 234 const struct pci_attach_args *pa = aux; 235 236 switch (PCI_PRODUCT(pa->pa_id)) { 237 case PCI_PRODUCT_INTEL_82840_HB: 238 case PCI_PRODUCT_INTEL_82865_HB: 239 case PCI_PRODUCT_INTEL_82845G_DRAM: 240 case PCI_PRODUCT_INTEL_82815_FULL_HUB: 241 return agp_intel_attach(parent, self, aux); 242 } 243 #endif 244 aprint_error(": can't find internal VGA device config space\n"); 245 free(isc, M_AGP); 246 return ENOENT; 247 } 248 249 /* XXXfvdl */ 250 sc->as_dmat = isc->vga_pa.pa_dmat; 251 252 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 253 case PCI_PRODUCT_INTEL_82810_GC: 254 case PCI_PRODUCT_INTEL_82810_DC100_GC: 255 case PCI_PRODUCT_INTEL_82810E_GC: 256 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 257 isc->chiptype = CHIP_I810; 258 break; 259 case PCI_PRODUCT_INTEL_82830MP_IV: 260 case PCI_PRODUCT_INTEL_82845G_IGD: 261 isc->chiptype = CHIP_I830; 262 break; 263 case PCI_PRODUCT_INTEL_82855GM_IGD: 264 case PCI_PRODUCT_INTEL_82865_IGD: 265 isc->chiptype = CHIP_I855; 266 break; 267 case PCI_PRODUCT_INTEL_82915G_IGD: 268 case PCI_PRODUCT_INTEL_82915GM_IGD: 269 case PCI_PRODUCT_INTEL_82945P_IGD: 270 case PCI_PRODUCT_INTEL_82945GM_IGD: 271 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 272 case PCI_PRODUCT_INTEL_82945GME_IGD: 273 isc->chiptype = CHIP_I915; 274 break; 275 case PCI_PRODUCT_INTEL_82965Q_IGD: 276 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 277 case PCI_PRODUCT_INTEL_82965PM_IGD: 278 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 279 case PCI_PRODUCT_INTEL_82965G_IGD: 280 case PCI_PRODUCT_INTEL_82965G_IGD_1: 281 case PCI_PRODUCT_INTEL_82946GZ_IGD: 282 case PCI_PRODUCT_INTEL_82G35_IGD: 283 case PCI_PRODUCT_INTEL_82G35_IGD_1: 284 isc->chiptype = CHIP_I965; 285 break; 286 case PCI_PRODUCT_INTEL_82Q35_IGD: 287 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 288 case PCI_PRODUCT_INTEL_82G33_IGD: 289 case PCI_PRODUCT_INTEL_82G33_IGD_1: 290 case PCI_PRODUCT_INTEL_82Q33_IGD: 291 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 292 isc->chiptype = CHIP_G33; 293 case PCI_PRODUCT_INTEL_82GM45_IGD: 294 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 295 isc->chiptype = CHIP_G4X; 296 break; 297 } 298 299 switch (isc->chiptype) { 300 case CHIP_I915: 301 case CHIP_G33: 302 apbase = AGP_I915_GMADR; 303 break; 304 case CHIP_I965: 305 case CHIP_G4X: 306 apbase = AGP_I965_GMADR; 307 break; 308 default: 309 apbase = AGP_I810_GMADR; 310 break; 311 } 312 313 if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) { 314 error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase); 315 } else { 316 error = agp_map_aperture(&isc->vga_pa, sc, apbase); 317 } 318 if (error != 0) { 319 aprint_error(": can't map aperture\n"); 320 free(isc, M_AGP); 321 return error; 322 } 323 324 if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33) { 325 error = pci_mapreg_map(&isc->vga_pa, AGP_I915_MMADR, 326 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 327 &mmadr, &mmadrsize); 328 if (error != 0) { 329 aprint_error(": can't map mmadr registers\n"); 330 agp_generic_detach(sc); 331 return error; 332 } 333 error = pci_mapreg_map(&isc->vga_pa, AGP_I915_GTTADR, 334 PCI_MAPREG_TYPE_MEM, 0, &isc->gtt_bst, &isc->gtt_bsh, 335 NULL, NULL); 336 if (error != 0) { 337 aprint_error(": can't map gttadr registers\n"); 338 /* XXX we should release mmadr here */ 339 agp_generic_detach(sc); 340 return error; 341 } 342 } else if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) { 343 error = pci_mapreg_map(&isc->vga_pa, AGP_I965_MMADR, 344 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 345 &mmadr, &mmadrsize); 346 if (error != 0) { 347 aprint_error(": can't map mmadr registers\n"); 348 agp_generic_detach(sc); 349 return error; 350 } 351 } else { 352 error = pci_mapreg_map(&isc->vga_pa, AGP_I810_MMADR, 353 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 354 &mmadr, &mmadrsize); 355 if (error != 0) { 356 aprint_error(": can't map mmadr registers\n"); 357 agp_generic_detach(sc); 358 return error; 359 } 360 } 361 362 isc->initial_aperture = AGP_GET_APERTURE(sc); 363 364 gatt = malloc(sizeof(struct agp_gatt), M_AGP, M_NOWAIT); 365 if (!gatt) { 366 agp_generic_detach(sc); 367 return ENOMEM; 368 } 369 isc->gatt = gatt; 370 371 gatt->ag_entries = AGP_GET_APERTURE(sc) >> AGP_PAGE_SHIFT; 372 373 if (!pmf_device_register(self, NULL, agp_i810_resume)) 374 aprint_error_dev(self, "couldn't establish power handler\n"); 375 376 /* 377 * XXX horrible hack to allow drm code to use our mapping 378 * of VGA chip registers 379 */ 380 agp_i810_vga_regbase = mmadr; 381 agp_i810_vga_bsh = isc->bsh; 382 383 return agp_i810_init(sc); 384 } 385 386 /* 387 * XXX horrible hack to allow drm code to use our mapping 388 * of VGA chip registers 389 */ 390 int 391 agp_i810_borrow(bus_addr_t base, bus_space_handle_t *hdlp) 392 { 393 394 if (!agp_i810_vga_regbase || base != agp_i810_vga_regbase) 395 return 0; 396 *hdlp = agp_i810_vga_bsh; 397 return 1; 398 } 399 400 static int agp_i810_init(struct agp_softc *sc) 401 { 402 struct agp_i810_softc *isc; 403 struct agp_gatt *gatt; 404 405 isc = sc->as_chipc; 406 gatt = isc->gatt; 407 408 if (isc->chiptype == CHIP_I810) { 409 void *virtual; 410 int dummyseg; 411 412 /* Some i810s have on-chip memory called dcache */ 413 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 414 isc->dcache_size = 4 * 1024 * 1024; 415 else 416 isc->dcache_size = 0; 417 418 /* According to the specs the gatt on the i810 must be 64k */ 419 if (agp_alloc_dmamem(sc->as_dmat, 64 * 1024, 420 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical, 421 &gatt->ag_dmaseg, 1, &dummyseg) != 0) { 422 free(gatt, M_AGP); 423 agp_generic_detach(sc); 424 return ENOMEM; 425 } 426 gatt->ag_virtual = (uint32_t *)virtual; 427 gatt->ag_size = gatt->ag_entries * sizeof(u_int32_t); 428 memset(gatt->ag_virtual, 0, gatt->ag_size); 429 430 agp_flush_cache(); 431 /* Install the GATT. */ 432 WRITE4(AGP_I810_PGTBL_CTL, gatt->ag_physical | 1); 433 } else if (isc->chiptype == CHIP_I830) { 434 /* The i830 automatically initializes the 128k gatt on boot. */ 435 pcireg_t reg; 436 u_int32_t pgtblctl; 437 u_int16_t gcc1; 438 439 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 440 gcc1 = (u_int16_t)(reg >> 16); 441 switch (gcc1 & AGP_I830_GCC1_GMS) { 442 case AGP_I830_GCC1_GMS_STOLEN_512: 443 isc->stolen = (512 - 132) * 1024 / 4096; 444 break; 445 case AGP_I830_GCC1_GMS_STOLEN_1024: 446 isc->stolen = (1024 - 132) * 1024 / 4096; 447 break; 448 case AGP_I830_GCC1_GMS_STOLEN_8192: 449 isc->stolen = (8192 - 132) * 1024 / 4096; 450 break; 451 default: 452 isc->stolen = 0; 453 aprint_error( 454 ": unknown memory configuration, disabling\n"); 455 agp_generic_detach(sc); 456 return EINVAL; 457 } 458 459 if (isc->stolen > 0) { 460 aprint_normal(": detected %dk stolen memory\n%s", 461 isc->stolen * 4, device_xname(sc->as_dev)); 462 } 463 464 /* GATT address is already in there, make sure it's enabled */ 465 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 466 pgtblctl |= 1; 467 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 468 469 gatt->ag_physical = pgtblctl & ~1; 470 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 471 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 || 472 isc->chiptype == CHIP_G4X) { 473 pcireg_t reg; 474 u_int32_t pgtblctl, gtt_size, stolen; 475 u_int16_t gcc1; 476 477 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1); 478 gcc1 = (u_int16_t)(reg >> 16); 479 480 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 481 482 /* Stolen memory is set up at the beginning of the aperture by 483 * the BIOS, consisting of the GATT followed by 4kb for the 484 * BIOS display. 485 */ 486 switch (isc->chiptype) { 487 case CHIP_I855: 488 gtt_size = 128; 489 break; 490 case CHIP_I915: 491 gtt_size = 256; 492 break; 493 case CHIP_I965: 494 switch (pgtblctl & AGP_I810_PGTBL_SIZE_MASK) { 495 case AGP_I810_PGTBL_SIZE_128KB: 496 case AGP_I810_PGTBL_SIZE_512KB: 497 gtt_size = 512; 498 break; 499 case AGP_I965_PGTBL_SIZE_1MB: 500 gtt_size = 1024; 501 break; 502 case AGP_I965_PGTBL_SIZE_2MB: 503 gtt_size = 2048; 504 break; 505 case AGP_I965_PGTBL_SIZE_1_5MB: 506 gtt_size = 1024 + 512; 507 break; 508 default: 509 aprint_error("Bad PGTBL size\n"); 510 agp_generic_detach(sc); 511 return EINVAL; 512 } 513 break; 514 case CHIP_G33: 515 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 516 case AGP_G33_PGTBL_SIZE_1M: 517 gtt_size = 1024; 518 break; 519 case AGP_G33_PGTBL_SIZE_2M: 520 gtt_size = 2048; 521 break; 522 default: 523 aprint_error(": Bad PGTBL size\n"); 524 agp_generic_detach(sc); 525 return EINVAL; 526 } 527 break; 528 case CHIP_G4X: 529 gtt_size = 0; 530 break; 531 default: 532 aprint_error(": bad chiptype\n"); 533 agp_generic_detach(sc); 534 return EINVAL; 535 } 536 537 switch (gcc1 & AGP_I855_GCC1_GMS) { 538 case AGP_I855_GCC1_GMS_STOLEN_1M: 539 stolen = 1024; 540 break; 541 case AGP_I855_GCC1_GMS_STOLEN_4M: 542 stolen = 4 * 1024; 543 break; 544 case AGP_I855_GCC1_GMS_STOLEN_8M: 545 stolen = 8 * 1024; 546 break; 547 case AGP_I855_GCC1_GMS_STOLEN_16M: 548 stolen = 16 * 1024; 549 break; 550 case AGP_I855_GCC1_GMS_STOLEN_32M: 551 stolen = 32 * 1024; 552 break; 553 case AGP_I915_GCC1_GMS_STOLEN_48M: 554 stolen = 48 * 1024; 555 break; 556 case AGP_I915_GCC1_GMS_STOLEN_64M: 557 stolen = 64 * 1024; 558 break; 559 case AGP_G33_GCC1_GMS_STOLEN_128M: 560 stolen = 128 * 1024; 561 break; 562 case AGP_G33_GCC1_GMS_STOLEN_256M: 563 stolen = 256 * 1024; 564 break; 565 case AGP_G4X_GCC1_GMS_STOLEN_96M: 566 stolen = 96 * 1024; 567 break; 568 case AGP_G4X_GCC1_GMS_STOLEN_160M: 569 stolen = 160 * 1024; 570 break; 571 case AGP_G4X_GCC1_GMS_STOLEN_224M: 572 stolen = 224 * 1024; 573 break; 574 case AGP_G4X_GCC1_GMS_STOLEN_352M: 575 stolen = 352 * 1024; 576 break; 577 default: 578 aprint_error( 579 ": unknown memory configuration, disabling\n"); 580 agp_generic_detach(sc); 581 return EINVAL; 582 } 583 584 switch (gcc1 & AGP_I855_GCC1_GMS) { 585 case AGP_I915_GCC1_GMS_STOLEN_48M: 586 case AGP_I915_GCC1_GMS_STOLEN_64M: 587 if (isc->chiptype != CHIP_I915 && 588 isc->chiptype != CHIP_I965 && 589 isc->chiptype != CHIP_G33 && 590 isc->chiptype != CHIP_G4X) 591 stolen = 0; 592 break; 593 case AGP_G33_GCC1_GMS_STOLEN_128M: 594 case AGP_G33_GCC1_GMS_STOLEN_256M: 595 if (isc->chiptype != CHIP_I965 && 596 isc->chiptype != CHIP_G33 && 597 isc->chiptype != CHIP_G4X) 598 stolen = 0; 599 break; 600 case AGP_G4X_GCC1_GMS_STOLEN_96M: 601 case AGP_G4X_GCC1_GMS_STOLEN_160M: 602 case AGP_G4X_GCC1_GMS_STOLEN_224M: 603 case AGP_G4X_GCC1_GMS_STOLEN_352M: 604 if (isc->chiptype != CHIP_I965 && 605 isc->chiptype != CHIP_G4X) 606 stolen = 0; 607 break; 608 } 609 610 /* BIOS space */ 611 if (isc->chiptype != CHIP_G4X) 612 gtt_size += 4; 613 614 isc->stolen = (stolen - gtt_size) * 1024 / 4096; 615 616 if (isc->stolen > 0) { 617 aprint_normal(": detected %dk stolen memory\n%s", 618 isc->stolen * 4, device_xname(sc->as_dev)); 619 } 620 621 /* GATT address is already in there, make sure it's enabled */ 622 pgtblctl |= 1; 623 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 624 625 gatt->ag_physical = pgtblctl & ~1; 626 } 627 628 /* 629 * Make sure the chipset can see everything. 630 */ 631 agp_flush_cache(); 632 633 return 0; 634 } 635 636 #if 0 637 static int 638 agp_i810_detach(struct agp_softc *sc) 639 { 640 int error; 641 struct agp_i810_softc *isc = sc->as_chipc; 642 643 error = agp_generic_detach(sc); 644 if (error) 645 return error; 646 647 /* Clear the GATT base. */ 648 if (sc->chiptype == CHIP_I810) { 649 WRITE4(AGP_I810_PGTBL_CTL, 0); 650 } else { 651 unsigned int pgtblctl; 652 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 653 pgtblctl &= ~1; 654 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 655 } 656 657 /* Put the aperture back the way it started. */ 658 AGP_SET_APERTURE(sc, isc->initial_aperture); 659 660 if (sc->chiptype == CHIP_I810) { 661 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap, 662 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 663 } 664 free(sc->gatt, M_AGP); 665 666 return 0; 667 } 668 #endif 669 670 static u_int32_t 671 agp_i810_get_aperture(struct agp_softc *sc) 672 { 673 struct agp_i810_softc *isc = sc->as_chipc; 674 pcireg_t reg; 675 u_int32_t size; 676 u_int16_t miscc, gcc1, msac; 677 678 size = 0; 679 680 switch (isc->chiptype) { 681 case CHIP_I810: 682 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 683 miscc = (u_int16_t)(reg >> 16); 684 if ((miscc & AGP_I810_MISCC_WINSIZE) == 685 AGP_I810_MISCC_WINSIZE_32) 686 size = 32 * 1024 * 1024; 687 else 688 size = 64 * 1024 * 1024; 689 break; 690 case CHIP_I830: 691 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 692 gcc1 = (u_int16_t)(reg >> 16); 693 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 694 size = 64 * 1024 * 1024; 695 else 696 size = 128 * 1024 * 1024; 697 break; 698 case CHIP_I855: 699 size = 128 * 1024 * 1024; 700 break; 701 case CHIP_I915: 702 case CHIP_G33: 703 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I915_MSAC); 704 msac = (u_int16_t)(reg >> 16); 705 if (msac & AGP_I915_MSAC_APER_128M) 706 size = 128 * 1024 * 1024; 707 else 708 size = 256 * 1024 * 1024; 709 break; 710 case CHIP_I965: 711 size = 512 * 1024 * 1024; 712 break; 713 case CHIP_G4X: 714 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_G4X_MSAC); 715 msac = (u_int16_t)(reg >> 16); 716 switch (msac & AGP_G4X_MSAC_MASK) { 717 case AGP_G4X_MSAC_APER_256M: 718 size = 256 * 1024 * 1024; 719 case AGP_G4X_MSAC_APER_512M: 720 size = 512 * 1024 * 1024; 721 } 722 break; 723 default: 724 aprint_error(": Unknown chipset\n"); 725 } 726 727 return size; 728 } 729 730 static int 731 agp_i810_set_aperture(struct agp_softc *sc, u_int32_t aperture) 732 { 733 struct agp_i810_softc *isc = sc->as_chipc; 734 pcireg_t reg; 735 u_int16_t miscc, gcc1; 736 737 switch (isc->chiptype) { 738 case CHIP_I810: 739 /* 740 * Double check for sanity. 741 */ 742 if (aperture != (32 * 1024 * 1024) && 743 aperture != (64 * 1024 * 1024)) { 744 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 745 aperture); 746 return EINVAL; 747 } 748 749 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 750 miscc = (u_int16_t)(reg >> 16); 751 miscc &= ~AGP_I810_MISCC_WINSIZE; 752 if (aperture == 32 * 1024 * 1024) 753 miscc |= AGP_I810_MISCC_WINSIZE_32; 754 else 755 miscc |= AGP_I810_MISCC_WINSIZE_64; 756 757 reg &= 0x0000ffff; 758 reg |= ((pcireg_t)miscc) << 16; 759 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I810_SMRAM, reg); 760 break; 761 case CHIP_I830: 762 if (aperture != (64 * 1024 * 1024) && 763 aperture != (128 * 1024 * 1024)) { 764 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 765 aperture); 766 return EINVAL; 767 } 768 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 769 gcc1 = (u_int16_t)(reg >> 16); 770 gcc1 &= ~AGP_I830_GCC1_GMASIZE; 771 if (aperture == 64 * 1024 * 1024) 772 gcc1 |= AGP_I830_GCC1_GMASIZE_64; 773 else 774 gcc1 |= AGP_I830_GCC1_GMASIZE_128; 775 776 reg &= 0x0000ffff; 777 reg |= ((pcireg_t)gcc1) << 16; 778 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I830_GCC0, reg); 779 break; 780 case CHIP_I855: 781 case CHIP_I915: 782 if (aperture != agp_i810_get_aperture(sc)) { 783 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 784 aperture); 785 return EINVAL; 786 } 787 break; 788 case CHIP_I965: 789 if (aperture != 512 * 1024 * 1024) { 790 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 791 aperture); 792 return EINVAL; 793 } 794 break; 795 } 796 797 return 0; 798 } 799 800 static int 801 agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 802 { 803 struct agp_i810_softc *isc = sc->as_chipc; 804 805 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) { 806 #ifdef AGP_DEBUG 807 printf("%s: failed: offset 0x%08x, shift %d, entries %d\n", 808 device_xname(sc->as_dev), (int)offset, AGP_PAGE_SHIFT, 809 isc->gatt->ag_entries); 810 #endif 811 return EINVAL; 812 } 813 814 if (isc->chiptype != CHIP_I830) { 815 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 816 #ifdef AGP_DEBUG 817 printf("%s: trying to bind into stolen memory", 818 device_xname(sc->as_dev)); 819 #endif 820 return EINVAL; 821 } 822 } 823 824 agp_i810_write_gtt_entry(isc, offset, physical | 1); 825 return 0; 826 } 827 828 static int 829 agp_i810_unbind_page(struct agp_softc *sc, off_t offset) 830 { 831 struct agp_i810_softc *isc = sc->as_chipc; 832 833 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 834 return EINVAL; 835 836 if (isc->chiptype != CHIP_I810 ) { 837 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 838 #ifdef AGP_DEBUG 839 printf("%s: trying to unbind from stolen memory", 840 device_xname(sc->as_dev)); 841 #endif 842 return EINVAL; 843 } 844 } 845 846 agp_i810_write_gtt_entry(isc, offset, 0); 847 return 0; 848 } 849 850 /* 851 * Writing via memory mapped registers already flushes all TLBs. 852 */ 853 static void 854 agp_i810_flush_tlb(struct agp_softc *sc) 855 { 856 } 857 858 static int 859 agp_i810_enable(struct agp_softc *sc, u_int32_t mode) 860 { 861 862 return 0; 863 } 864 865 static struct agp_memory * 866 agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size) 867 { 868 struct agp_i810_softc *isc = sc->as_chipc; 869 struct agp_memory *mem; 870 871 #ifdef AGP_DEBUG 872 printf("AGP: alloc(%d, 0x%x)\n", type, (int) size); 873 #endif 874 875 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 876 return 0; 877 878 if (sc->as_allocated + size > sc->as_maxmem) 879 return 0; 880 881 if (type == 1) { 882 /* 883 * Mapping local DRAM into GATT. 884 */ 885 if (isc->chiptype != CHIP_I810 ) 886 return 0; 887 if (size != isc->dcache_size) 888 return 0; 889 } else if (type == 2) { 890 /* 891 * Bogus mapping for the hardware cursor. 892 */ 893 if (size != AGP_PAGE_SIZE && size != 4 * AGP_PAGE_SIZE) 894 return 0; 895 } 896 897 mem = malloc(sizeof *mem, M_AGP, M_WAITOK|M_ZERO); 898 if (mem == NULL) 899 return NULL; 900 mem->am_id = sc->as_nextid++; 901 mem->am_size = size; 902 mem->am_type = type; 903 904 if (type == 2) { 905 /* 906 * Allocate and wire down the memory now so that we can 907 * get its physical address. 908 */ 909 mem->am_dmaseg = malloc(sizeof *mem->am_dmaseg, M_AGP, 910 M_WAITOK); 911 if (mem->am_dmaseg == NULL) { 912 free(mem, M_AGP); 913 return NULL; 914 } 915 if (agp_alloc_dmamem(sc->as_dmat, size, 0, 916 &mem->am_dmamap, &mem->am_virtual, &mem->am_physical, 917 mem->am_dmaseg, 1, &mem->am_nseg) != 0) { 918 free(mem->am_dmaseg, M_AGP); 919 free(mem, M_AGP); 920 return NULL; 921 } 922 memset(mem->am_virtual, 0, size); 923 } else if (type != 1) { 924 if (bus_dmamap_create(sc->as_dmat, size, size / PAGE_SIZE + 1, 925 size, 0, BUS_DMA_NOWAIT, 926 &mem->am_dmamap) != 0) { 927 free(mem, M_AGP); 928 return NULL; 929 } 930 } 931 932 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link); 933 sc->as_allocated += size; 934 935 return mem; 936 } 937 938 static int 939 agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem) 940 { 941 if (mem->am_is_bound) 942 return EBUSY; 943 944 if (mem->am_type == 2) { 945 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap, 946 mem->am_virtual, mem->am_dmaseg, mem->am_nseg); 947 free(mem->am_dmaseg, M_AGP); 948 } 949 950 sc->as_allocated -= mem->am_size; 951 TAILQ_REMOVE(&sc->as_memory, mem, am_link); 952 free(mem, M_AGP); 953 return 0; 954 } 955 956 static int 957 agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem, 958 off_t offset) 959 { 960 struct agp_i810_softc *isc = sc->as_chipc; 961 u_int32_t regval, i; 962 963 /* 964 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 965 * X server for mysterious reasons which leads to crashes if we write 966 * to the GTT through the MMIO window. 967 * Until the issue is solved, simply restore it. 968 */ 969 regval = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL); 970 if (regval != (isc->gatt->ag_physical | 1)) { 971 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%x - fixing\n", 972 regval); 973 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 974 isc->gatt->ag_physical | 1); 975 } 976 977 if (mem->am_type == 2) { 978 agp_i810_write_gtt_entry(isc, offset, mem->am_physical | 1); 979 mem->am_offset = offset; 980 mem->am_is_bound = 1; 981 return 0; 982 } 983 984 if (mem->am_type != 1) 985 return agp_generic_bind_memory(sc, mem, offset); 986 987 if (isc->chiptype != CHIP_I810) 988 return EINVAL; 989 990 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 991 agp_i810_write_gtt_entry(isc, offset, i | 3); 992 mem->am_is_bound = 1; 993 return 0; 994 } 995 996 static int 997 agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem) 998 { 999 struct agp_i810_softc *isc = sc->as_chipc; 1000 u_int32_t i; 1001 1002 if (mem->am_type == 2) { 1003 agp_i810_write_gtt_entry(isc, mem->am_offset, 0); 1004 mem->am_offset = 0; 1005 mem->am_is_bound = 0; 1006 return 0; 1007 } 1008 1009 if (mem->am_type != 1) 1010 return agp_generic_unbind_memory(sc, mem); 1011 1012 if (isc->chiptype != CHIP_I810) 1013 return EINVAL; 1014 1015 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1016 agp_i810_write_gtt_entry(isc, i, 0); 1017 mem->am_is_bound = 0; 1018 return 0; 1019 } 1020 1021 static bool 1022 agp_i810_resume(device_t dv PMF_FN_ARGS) 1023 { 1024 struct agp_softc *sc = device_private(dv); 1025 struct agp_i810_softc *isc = sc->as_chipc; 1026 1027 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 1028 agp_flush_cache(); 1029 1030 return true; 1031 } 1032
Indexes created Fri Sep 26 20:09:58 GMT 2025