agp_i810.c revision 1.67
1 /* $NetBSD: agp_i810.c,v 1.67 2010/04/04 14:40:05 jakllsch Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/pci/agp_i810.c,v 1.4 2001/07/05 21:28:47 jhb Exp $ 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.67 2010/04/04 14:40:05 jakllsch Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/proc.h> 40 #include <sys/device.h> 41 #include <sys/conf.h> 42 43 #include <uvm/uvm_extern.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/agpvar.h> 49 #include <dev/pci/agpreg.h> 50 51 #include <sys/agpio.h> 52 53 #include <sys/bus.h> 54 55 #include "agp_intel.h" 56 57 #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off) 58 #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off) 59 #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v) 60 61 #define CHIP_I810 0 /* i810/i815 */ 62 #define CHIP_I830 1 /* 830M/845G */ 63 #define CHIP_I855 2 /* 852GM/855GM/865G */ 64 #define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */ 65 #define CHIP_I965 4 /* 965Q/965PM */ 66 #define CHIP_G33 5 /* G33/Q33/Q35 */ 67 #define CHIP_G4X 6 /* G45/Q45 */ 68 69 struct agp_i810_softc { 70 u_int32_t initial_aperture; /* aperture size at startup */ 71 struct agp_gatt *gatt; 72 int chiptype; /* i810-like or i830 */ 73 u_int32_t dcache_size; /* i810 only */ 74 u_int32_t stolen; /* number of i830/845 gtt entries 75 for stolen memory */ 76 bus_space_tag_t bst; /* register bus_space tag */ 77 bus_space_handle_t bsh; /* register bus_space handle */ 78 bus_space_tag_t gtt_bst; /* GTT bus_space tag */ 79 bus_space_handle_t gtt_bsh; /* GTT bus_space handle */ 80 struct pci_attach_args vga_pa; 81 82 u_int32_t pgtblctl; 83 }; 84 85 /* XXX hack, see below */ 86 static bus_addr_t agp_i810_vga_regbase; 87 static bus_space_handle_t agp_i810_vga_bsh; 88 89 static u_int32_t agp_i810_get_aperture(struct agp_softc *); 90 static int agp_i810_set_aperture(struct agp_softc *, u_int32_t); 91 static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t); 92 static int agp_i810_unbind_page(struct agp_softc *, off_t); 93 static void agp_i810_flush_tlb(struct agp_softc *); 94 static int agp_i810_enable(struct agp_softc *, u_int32_t mode); 95 static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int, 96 vsize_t); 97 static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *); 98 static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, off_t); 99 static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *); 100 101 static bool agp_i810_resume(device_t, const pmf_qual_t *); 102 static int agp_i810_init(struct agp_softc *); 103 104 static int agp_i810_init(struct agp_softc *); 105 static void agp_i810_write_gtt_entry(struct agp_i810_softc *, off_t, 106 u_int32_t); 107 108 static struct agp_methods agp_i810_methods = { 109 agp_i810_get_aperture, 110 agp_i810_set_aperture, 111 agp_i810_bind_page, 112 agp_i810_unbind_page, 113 agp_i810_flush_tlb, 114 agp_i810_enable, 115 agp_i810_alloc_memory, 116 agp_i810_free_memory, 117 agp_i810_bind_memory, 118 agp_i810_unbind_memory, 119 }; 120 121 static void 122 agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, u_int32_t v) 123 { 124 u_int32_t base_off; 125 126 base_off = 0; 127 128 switch (isc->chiptype) { 129 case CHIP_I810: 130 case CHIP_I830: 131 case CHIP_I855: 132 base_off = AGP_I810_GTT; 133 break; 134 case CHIP_I965: 135 base_off = AGP_I965_GTT; 136 break; 137 case CHIP_G4X: 138 base_off = AGP_G4X_GTT; 139 break; 140 case CHIP_I915: 141 case CHIP_G33: 142 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, 143 (u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4, (v)); 144 return; 145 } 146 147 WRITE4(base_off + (u_int32_t)(off >> AGP_PAGE_SHIFT) * 4, v); 148 } 149 150 /* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */ 151 static int 152 agp_i810_vgamatch(struct pci_attach_args *pa) 153 { 154 155 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 156 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 157 return (0); 158 159 switch (PCI_PRODUCT(pa->pa_id)) { 160 case PCI_PRODUCT_INTEL_82810_GC: 161 case PCI_PRODUCT_INTEL_82810_DC100_GC: 162 case PCI_PRODUCT_INTEL_82810E_GC: 163 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 164 case PCI_PRODUCT_INTEL_82830MP_IV: 165 case PCI_PRODUCT_INTEL_82845G_IGD: 166 case PCI_PRODUCT_INTEL_82855GM_IGD: 167 case PCI_PRODUCT_INTEL_82865_IGD: 168 case PCI_PRODUCT_INTEL_82915G_IGD: 169 case PCI_PRODUCT_INTEL_82915GM_IGD: 170 case PCI_PRODUCT_INTEL_82945P_IGD: 171 case PCI_PRODUCT_INTEL_82945GM_IGD: 172 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 173 case PCI_PRODUCT_INTEL_82945GME_IGD: 174 case PCI_PRODUCT_INTEL_82965Q_IGD: 175 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 176 case PCI_PRODUCT_INTEL_82965PM_IGD: 177 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 178 case PCI_PRODUCT_INTEL_82G33_IGD: 179 case PCI_PRODUCT_INTEL_82G33_IGD_1: 180 case PCI_PRODUCT_INTEL_82965G_IGD: 181 case PCI_PRODUCT_INTEL_82965G_IGD_1: 182 case PCI_PRODUCT_INTEL_82Q35_IGD: 183 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 184 case PCI_PRODUCT_INTEL_82Q33_IGD: 185 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 186 case PCI_PRODUCT_INTEL_82G35_IGD: 187 case PCI_PRODUCT_INTEL_82G35_IGD_1: 188 case PCI_PRODUCT_INTEL_82946GZ_IGD: 189 case PCI_PRODUCT_INTEL_82GM45_IGD: 190 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 191 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 192 case PCI_PRODUCT_INTEL_82Q45_IGD: 193 case PCI_PRODUCT_INTEL_82G45_IGD: 194 return (1); 195 } 196 197 return (0); 198 } 199 200 static int 201 agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg) 202 { 203 /* 204 * Find the aperture. Don't map it (yet), this would 205 * eat KVA. 206 */ 207 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 208 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize, 209 &sc->as_apflags) != 0) 210 return ENXIO; 211 212 sc->as_apt = pa->pa_memt; 213 214 return 0; 215 } 216 217 int 218 agp_i810_attach(device_t parent, device_t self, void *aux) 219 { 220 struct agp_softc *sc = device_private(self); 221 struct agp_i810_softc *isc; 222 struct agp_gatt *gatt; 223 int error, apbase; 224 bus_addr_t mmadr; 225 bus_size_t mmadrsize; 226 227 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 228 if (isc == NULL) { 229 aprint_error(": can't allocate chipset-specific softc\n"); 230 return ENOMEM; 231 } 232 sc->as_chipc = isc; 233 sc->as_methods = &agp_i810_methods; 234 235 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) { 236 #if NAGP_INTEL > 0 237 const struct pci_attach_args *pa = aux; 238 239 switch (PCI_PRODUCT(pa->pa_id)) { 240 case PCI_PRODUCT_INTEL_82840_HB: 241 case PCI_PRODUCT_INTEL_82865_HB: 242 case PCI_PRODUCT_INTEL_82845G_DRAM: 243 case PCI_PRODUCT_INTEL_82815_FULL_HUB: 244 case PCI_PRODUCT_INTEL_82855GM_MCH: 245 return agp_intel_attach(parent, self, aux); 246 } 247 #endif 248 aprint_error(": can't find internal VGA device config space\n"); 249 free(isc, M_AGP); 250 return ENOENT; 251 } 252 253 /* XXXfvdl */ 254 sc->as_dmat = isc->vga_pa.pa_dmat; 255 256 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 257 case PCI_PRODUCT_INTEL_82810_GC: 258 case PCI_PRODUCT_INTEL_82810_DC100_GC: 259 case PCI_PRODUCT_INTEL_82810E_GC: 260 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 261 isc->chiptype = CHIP_I810; 262 break; 263 case PCI_PRODUCT_INTEL_82830MP_IV: 264 case PCI_PRODUCT_INTEL_82845G_IGD: 265 isc->chiptype = CHIP_I830; 266 break; 267 case PCI_PRODUCT_INTEL_82855GM_IGD: 268 case PCI_PRODUCT_INTEL_82865_IGD: 269 isc->chiptype = CHIP_I855; 270 break; 271 case PCI_PRODUCT_INTEL_82915G_IGD: 272 case PCI_PRODUCT_INTEL_82915GM_IGD: 273 case PCI_PRODUCT_INTEL_82945P_IGD: 274 case PCI_PRODUCT_INTEL_82945GM_IGD: 275 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 276 case PCI_PRODUCT_INTEL_82945GME_IGD: 277 isc->chiptype = CHIP_I915; 278 break; 279 case PCI_PRODUCT_INTEL_82965Q_IGD: 280 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 281 case PCI_PRODUCT_INTEL_82965PM_IGD: 282 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 283 case PCI_PRODUCT_INTEL_82965G_IGD: 284 case PCI_PRODUCT_INTEL_82965G_IGD_1: 285 case PCI_PRODUCT_INTEL_82946GZ_IGD: 286 case PCI_PRODUCT_INTEL_82G35_IGD: 287 case PCI_PRODUCT_INTEL_82G35_IGD_1: 288 isc->chiptype = CHIP_I965; 289 break; 290 case PCI_PRODUCT_INTEL_82Q35_IGD: 291 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 292 case PCI_PRODUCT_INTEL_82G33_IGD: 293 case PCI_PRODUCT_INTEL_82G33_IGD_1: 294 case PCI_PRODUCT_INTEL_82Q33_IGD: 295 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 296 isc->chiptype = CHIP_G33; 297 break; 298 case PCI_PRODUCT_INTEL_82GM45_IGD: 299 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 300 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 301 case PCI_PRODUCT_INTEL_82Q45_IGD: 302 case PCI_PRODUCT_INTEL_82G45_IGD: 303 isc->chiptype = CHIP_G4X; 304 break; 305 } 306 307 switch (isc->chiptype) { 308 case CHIP_I915: 309 case CHIP_G33: 310 apbase = AGP_I915_GMADR; 311 break; 312 case CHIP_I965: 313 case CHIP_G4X: 314 apbase = AGP_I965_GMADR; 315 break; 316 default: 317 apbase = AGP_I810_GMADR; 318 break; 319 } 320 321 if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) { 322 error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase); 323 } else { 324 error = agp_map_aperture(&isc->vga_pa, sc, apbase); 325 } 326 if (error != 0) { 327 aprint_error(": can't map aperture\n"); 328 free(isc, M_AGP); 329 return error; 330 } 331 332 if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33) { 333 error = pci_mapreg_map(&isc->vga_pa, AGP_I915_MMADR, 334 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 335 &mmadr, &mmadrsize); 336 if (error != 0) { 337 aprint_error(": can't map mmadr registers\n"); 338 agp_generic_detach(sc); 339 return error; 340 } 341 error = pci_mapreg_map(&isc->vga_pa, AGP_I915_GTTADR, 342 PCI_MAPREG_TYPE_MEM, 0, &isc->gtt_bst, &isc->gtt_bsh, 343 NULL, NULL); 344 if (error != 0) { 345 aprint_error(": can't map gttadr registers\n"); 346 /* XXX we should release mmadr here */ 347 agp_generic_detach(sc); 348 return error; 349 } 350 } else if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) { 351 error = pci_mapreg_map(&isc->vga_pa, AGP_I965_MMADR, 352 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 353 &mmadr, &mmadrsize); 354 if (error != 0) { 355 aprint_error(": can't map mmadr registers\n"); 356 agp_generic_detach(sc); 357 return error; 358 } 359 } else { 360 error = pci_mapreg_map(&isc->vga_pa, AGP_I810_MMADR, 361 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 362 &mmadr, &mmadrsize); 363 if (error != 0) { 364 aprint_error(": can't map mmadr registers\n"); 365 agp_generic_detach(sc); 366 return error; 367 } 368 } 369 370 isc->initial_aperture = AGP_GET_APERTURE(sc); 371 372 gatt = malloc(sizeof(struct agp_gatt), M_AGP, M_NOWAIT); 373 if (!gatt) { 374 agp_generic_detach(sc); 375 return ENOMEM; 376 } 377 isc->gatt = gatt; 378 379 gatt->ag_entries = AGP_GET_APERTURE(sc) >> AGP_PAGE_SHIFT; 380 381 if (!pmf_device_register(self, NULL, agp_i810_resume)) 382 aprint_error_dev(self, "couldn't establish power handler\n"); 383 384 /* 385 * XXX horrible hack to allow drm code to use our mapping 386 * of VGA chip registers 387 */ 388 agp_i810_vga_regbase = mmadr; 389 agp_i810_vga_bsh = isc->bsh; 390 391 return agp_i810_init(sc); 392 } 393 394 /* 395 * XXX horrible hack to allow drm code to use our mapping 396 * of VGA chip registers 397 */ 398 int 399 agp_i810_borrow(bus_addr_t base, bus_space_handle_t *hdlp) 400 { 401 402 if (!agp_i810_vga_regbase || base != agp_i810_vga_regbase) 403 return 0; 404 *hdlp = agp_i810_vga_bsh; 405 return 1; 406 } 407 408 static int agp_i810_init(struct agp_softc *sc) 409 { 410 struct agp_i810_softc *isc; 411 struct agp_gatt *gatt; 412 413 isc = sc->as_chipc; 414 gatt = isc->gatt; 415 416 if (isc->chiptype == CHIP_I810) { 417 void *virtual; 418 int dummyseg; 419 420 /* Some i810s have on-chip memory called dcache */ 421 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 422 isc->dcache_size = 4 * 1024 * 1024; 423 else 424 isc->dcache_size = 0; 425 426 /* According to the specs the gatt on the i810 must be 64k */ 427 if (agp_alloc_dmamem(sc->as_dmat, 64 * 1024, 428 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical, 429 &gatt->ag_dmaseg, 1, &dummyseg) != 0) { 430 free(gatt, M_AGP); 431 agp_generic_detach(sc); 432 return ENOMEM; 433 } 434 gatt->ag_virtual = (uint32_t *)virtual; 435 gatt->ag_size = gatt->ag_entries * sizeof(u_int32_t); 436 memset(gatt->ag_virtual, 0, gatt->ag_size); 437 438 agp_flush_cache(); 439 /* Install the GATT. */ 440 WRITE4(AGP_I810_PGTBL_CTL, gatt->ag_physical | 1); 441 } else if (isc->chiptype == CHIP_I830) { 442 /* The i830 automatically initializes the 128k gatt on boot. */ 443 pcireg_t reg; 444 u_int32_t pgtblctl; 445 u_int16_t gcc1; 446 447 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 448 gcc1 = (u_int16_t)(reg >> 16); 449 switch (gcc1 & AGP_I830_GCC1_GMS) { 450 case AGP_I830_GCC1_GMS_STOLEN_512: 451 isc->stolen = (512 - 132) * 1024 / 4096; 452 break; 453 case AGP_I830_GCC1_GMS_STOLEN_1024: 454 isc->stolen = (1024 - 132) * 1024 / 4096; 455 break; 456 case AGP_I830_GCC1_GMS_STOLEN_8192: 457 isc->stolen = (8192 - 132) * 1024 / 4096; 458 break; 459 default: 460 isc->stolen = 0; 461 aprint_error( 462 ": unknown memory configuration, disabling\n"); 463 agp_generic_detach(sc); 464 return EINVAL; 465 } 466 467 if (isc->stolen > 0) { 468 aprint_normal(": detected %dk stolen memory\n%s", 469 isc->stolen * 4, device_xname(sc->as_dev)); 470 } 471 472 /* GATT address is already in there, make sure it's enabled */ 473 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 474 pgtblctl |= 1; 475 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 476 477 gatt->ag_physical = pgtblctl & ~1; 478 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 479 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 || 480 isc->chiptype == CHIP_G4X) { 481 pcireg_t reg; 482 u_int32_t pgtblctl, gtt_size, stolen; 483 u_int16_t gcc1; 484 485 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1); 486 gcc1 = (u_int16_t)(reg >> 16); 487 488 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 489 490 /* Stolen memory is set up at the beginning of the aperture by 491 * the BIOS, consisting of the GATT followed by 4kb for the 492 * BIOS display. 493 */ 494 switch (isc->chiptype) { 495 case CHIP_I855: 496 gtt_size = 128; 497 break; 498 case CHIP_I915: 499 gtt_size = 256; 500 break; 501 case CHIP_I965: 502 switch (pgtblctl & AGP_I810_PGTBL_SIZE_MASK) { 503 case AGP_I810_PGTBL_SIZE_128KB: 504 case AGP_I810_PGTBL_SIZE_512KB: 505 gtt_size = 512; 506 break; 507 case AGP_I965_PGTBL_SIZE_1MB: 508 gtt_size = 1024; 509 break; 510 case AGP_I965_PGTBL_SIZE_2MB: 511 gtt_size = 2048; 512 break; 513 case AGP_I965_PGTBL_SIZE_1_5MB: 514 gtt_size = 1024 + 512; 515 break; 516 default: 517 aprint_error("Bad PGTBL size\n"); 518 agp_generic_detach(sc); 519 return EINVAL; 520 } 521 break; 522 case CHIP_G33: 523 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 524 case AGP_G33_PGTBL_SIZE_1M: 525 gtt_size = 1024; 526 break; 527 case AGP_G33_PGTBL_SIZE_2M: 528 gtt_size = 2048; 529 break; 530 default: 531 aprint_error(": Bad PGTBL size\n"); 532 agp_generic_detach(sc); 533 return EINVAL; 534 } 535 break; 536 case CHIP_G4X: 537 gtt_size = 0; 538 break; 539 default: 540 aprint_error(": bad chiptype\n"); 541 agp_generic_detach(sc); 542 return EINVAL; 543 } 544 545 switch (gcc1 & AGP_I855_GCC1_GMS) { 546 case AGP_I855_GCC1_GMS_STOLEN_1M: 547 stolen = 1024; 548 break; 549 case AGP_I855_GCC1_GMS_STOLEN_4M: 550 stolen = 4 * 1024; 551 break; 552 case AGP_I855_GCC1_GMS_STOLEN_8M: 553 stolen = 8 * 1024; 554 break; 555 case AGP_I855_GCC1_GMS_STOLEN_16M: 556 stolen = 16 * 1024; 557 break; 558 case AGP_I855_GCC1_GMS_STOLEN_32M: 559 stolen = 32 * 1024; 560 break; 561 case AGP_I915_GCC1_GMS_STOLEN_48M: 562 stolen = 48 * 1024; 563 break; 564 case AGP_I915_GCC1_GMS_STOLEN_64M: 565 stolen = 64 * 1024; 566 break; 567 case AGP_G33_GCC1_GMS_STOLEN_128M: 568 stolen = 128 * 1024; 569 break; 570 case AGP_G33_GCC1_GMS_STOLEN_256M: 571 stolen = 256 * 1024; 572 break; 573 case AGP_G4X_GCC1_GMS_STOLEN_96M: 574 stolen = 96 * 1024; 575 break; 576 case AGP_G4X_GCC1_GMS_STOLEN_160M: 577 stolen = 160 * 1024; 578 break; 579 case AGP_G4X_GCC1_GMS_STOLEN_224M: 580 stolen = 224 * 1024; 581 break; 582 case AGP_G4X_GCC1_GMS_STOLEN_352M: 583 stolen = 352 * 1024; 584 break; 585 default: 586 aprint_error( 587 ": unknown memory configuration, disabling\n"); 588 agp_generic_detach(sc); 589 return EINVAL; 590 } 591 592 switch (gcc1 & AGP_I855_GCC1_GMS) { 593 case AGP_I915_GCC1_GMS_STOLEN_48M: 594 case AGP_I915_GCC1_GMS_STOLEN_64M: 595 if (isc->chiptype != CHIP_I915 && 596 isc->chiptype != CHIP_I965 && 597 isc->chiptype != CHIP_G33 && 598 isc->chiptype != CHIP_G4X) 599 stolen = 0; 600 break; 601 case AGP_G33_GCC1_GMS_STOLEN_128M: 602 case AGP_G33_GCC1_GMS_STOLEN_256M: 603 if (isc->chiptype != CHIP_I965 && 604 isc->chiptype != CHIP_G33 && 605 isc->chiptype != CHIP_G4X) 606 stolen = 0; 607 break; 608 case AGP_G4X_GCC1_GMS_STOLEN_96M: 609 case AGP_G4X_GCC1_GMS_STOLEN_160M: 610 case AGP_G4X_GCC1_GMS_STOLEN_224M: 611 case AGP_G4X_GCC1_GMS_STOLEN_352M: 612 if (isc->chiptype != CHIP_I965 && 613 isc->chiptype != CHIP_G4X) 614 stolen = 0; 615 break; 616 } 617 618 /* BIOS space */ 619 gtt_size += 4; 620 621 isc->stolen = (stolen - gtt_size) * 1024 / 4096; 622 623 if (isc->stolen > 0) { 624 aprint_normal(": detected %dk stolen memory\n%s", 625 isc->stolen * 4, device_xname(sc->as_dev)); 626 } 627 628 /* GATT address is already in there, make sure it's enabled */ 629 pgtblctl |= 1; 630 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 631 632 gatt->ag_physical = pgtblctl & ~1; 633 } 634 635 /* 636 * Make sure the chipset can see everything. 637 */ 638 agp_flush_cache(); 639 640 return 0; 641 } 642 643 #if 0 644 static int 645 agp_i810_detach(struct agp_softc *sc) 646 { 647 int error; 648 struct agp_i810_softc *isc = sc->as_chipc; 649 650 error = agp_generic_detach(sc); 651 if (error) 652 return error; 653 654 /* Clear the GATT base. */ 655 if (sc->chiptype == CHIP_I810) { 656 WRITE4(AGP_I810_PGTBL_CTL, 0); 657 } else { 658 unsigned int pgtblctl; 659 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 660 pgtblctl &= ~1; 661 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 662 } 663 664 /* Put the aperture back the way it started. */ 665 AGP_SET_APERTURE(sc, isc->initial_aperture); 666 667 if (sc->chiptype == CHIP_I810) { 668 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap, 669 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 670 } 671 free(sc->gatt, M_AGP); 672 673 return 0; 674 } 675 #endif 676 677 static u_int32_t 678 agp_i810_get_aperture(struct agp_softc *sc) 679 { 680 struct agp_i810_softc *isc = sc->as_chipc; 681 pcireg_t reg; 682 u_int32_t size; 683 u_int16_t miscc, gcc1, msac; 684 685 size = 0; 686 687 switch (isc->chiptype) { 688 case CHIP_I810: 689 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 690 miscc = (u_int16_t)(reg >> 16); 691 if ((miscc & AGP_I810_MISCC_WINSIZE) == 692 AGP_I810_MISCC_WINSIZE_32) 693 size = 32 * 1024 * 1024; 694 else 695 size = 64 * 1024 * 1024; 696 break; 697 case CHIP_I830: 698 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 699 gcc1 = (u_int16_t)(reg >> 16); 700 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 701 size = 64 * 1024 * 1024; 702 else 703 size = 128 * 1024 * 1024; 704 break; 705 case CHIP_I855: 706 size = 128 * 1024 * 1024; 707 break; 708 case CHIP_I915: 709 case CHIP_G33: 710 case CHIP_G4X: 711 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I915_MSAC); 712 msac = (u_int16_t)(reg >> 16); 713 if (msac & AGP_I915_MSAC_APER_128M) 714 size = 128 * 1024 * 1024; 715 else 716 size = 256 * 1024 * 1024; 717 break; 718 case CHIP_I965: 719 size = 512 * 1024 * 1024; 720 break; 721 default: 722 aprint_error(": Unknown chipset\n"); 723 } 724 725 return size; 726 } 727 728 static int 729 agp_i810_set_aperture(struct agp_softc *sc, u_int32_t aperture) 730 { 731 struct agp_i810_softc *isc = sc->as_chipc; 732 pcireg_t reg; 733 u_int16_t miscc, gcc1; 734 735 switch (isc->chiptype) { 736 case CHIP_I810: 737 /* 738 * Double check for sanity. 739 */ 740 if (aperture != (32 * 1024 * 1024) && 741 aperture != (64 * 1024 * 1024)) { 742 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 743 aperture); 744 return EINVAL; 745 } 746 747 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 748 miscc = (u_int16_t)(reg >> 16); 749 miscc &= ~AGP_I810_MISCC_WINSIZE; 750 if (aperture == 32 * 1024 * 1024) 751 miscc |= AGP_I810_MISCC_WINSIZE_32; 752 else 753 miscc |= AGP_I810_MISCC_WINSIZE_64; 754 755 reg &= 0x0000ffff; 756 reg |= ((pcireg_t)miscc) << 16; 757 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I810_SMRAM, reg); 758 break; 759 case CHIP_I830: 760 if (aperture != (64 * 1024 * 1024) && 761 aperture != (128 * 1024 * 1024)) { 762 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 763 aperture); 764 return EINVAL; 765 } 766 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 767 gcc1 = (u_int16_t)(reg >> 16); 768 gcc1 &= ~AGP_I830_GCC1_GMASIZE; 769 if (aperture == 64 * 1024 * 1024) 770 gcc1 |= AGP_I830_GCC1_GMASIZE_64; 771 else 772 gcc1 |= AGP_I830_GCC1_GMASIZE_128; 773 774 reg &= 0x0000ffff; 775 reg |= ((pcireg_t)gcc1) << 16; 776 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I830_GCC0, reg); 777 break; 778 case CHIP_I855: 779 case CHIP_I915: 780 if (aperture != agp_i810_get_aperture(sc)) { 781 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 782 aperture); 783 return EINVAL; 784 } 785 break; 786 case CHIP_I965: 787 if (aperture != 512 * 1024 * 1024) { 788 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 789 aperture); 790 return EINVAL; 791 } 792 break; 793 } 794 795 return 0; 796 } 797 798 static int 799 agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 800 { 801 struct agp_i810_softc *isc = sc->as_chipc; 802 803 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) { 804 #ifdef AGP_DEBUG 805 printf("%s: failed: offset 0x%08x, shift %d, entries %d\n", 806 device_xname(sc->as_dev), (int)offset, AGP_PAGE_SHIFT, 807 isc->gatt->ag_entries); 808 #endif 809 return EINVAL; 810 } 811 812 if (isc->chiptype != CHIP_I830) { 813 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 814 #ifdef AGP_DEBUG 815 printf("%s: trying to bind into stolen memory", 816 device_xname(sc->as_dev)); 817 #endif 818 return EINVAL; 819 } 820 } 821 822 agp_i810_write_gtt_entry(isc, offset, physical | 1); 823 return 0; 824 } 825 826 static int 827 agp_i810_unbind_page(struct agp_softc *sc, off_t offset) 828 { 829 struct agp_i810_softc *isc = sc->as_chipc; 830 831 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 832 return EINVAL; 833 834 if (isc->chiptype != CHIP_I810 ) { 835 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 836 #ifdef AGP_DEBUG 837 printf("%s: trying to unbind from stolen memory", 838 device_xname(sc->as_dev)); 839 #endif 840 return EINVAL; 841 } 842 } 843 844 agp_i810_write_gtt_entry(isc, offset, 0); 845 return 0; 846 } 847 848 /* 849 * Writing via memory mapped registers already flushes all TLBs. 850 */ 851 static void 852 agp_i810_flush_tlb(struct agp_softc *sc) 853 { 854 } 855 856 static int 857 agp_i810_enable(struct agp_softc *sc, u_int32_t mode) 858 { 859 860 return 0; 861 } 862 863 static struct agp_memory * 864 agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size) 865 { 866 struct agp_i810_softc *isc = sc->as_chipc; 867 struct agp_memory *mem; 868 869 #ifdef AGP_DEBUG 870 printf("AGP: alloc(%d, 0x%x)\n", type, (int) size); 871 #endif 872 873 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 874 return 0; 875 876 if (sc->as_allocated + size > sc->as_maxmem) 877 return 0; 878 879 if (type == 1) { 880 /* 881 * Mapping local DRAM into GATT. 882 */ 883 if (isc->chiptype != CHIP_I810 ) 884 return 0; 885 if (size != isc->dcache_size) 886 return 0; 887 } else if (type == 2) { 888 /* 889 * Bogus mapping for the hardware cursor. 890 */ 891 if (size != AGP_PAGE_SIZE && size != 4 * AGP_PAGE_SIZE) 892 return 0; 893 } 894 895 mem = malloc(sizeof *mem, M_AGP, M_WAITOK|M_ZERO); 896 if (mem == NULL) 897 return NULL; 898 mem->am_id = sc->as_nextid++; 899 mem->am_size = size; 900 mem->am_type = type; 901 902 if (type == 2) { 903 /* 904 * Allocate and wire down the memory now so that we can 905 * get its physical address. 906 */ 907 mem->am_dmaseg = malloc(sizeof *mem->am_dmaseg, M_AGP, 908 M_WAITOK); 909 if (mem->am_dmaseg == NULL) { 910 free(mem, M_AGP); 911 return NULL; 912 } 913 if (agp_alloc_dmamem(sc->as_dmat, size, 0, 914 &mem->am_dmamap, &mem->am_virtual, &mem->am_physical, 915 mem->am_dmaseg, 1, &mem->am_nseg) != 0) { 916 free(mem->am_dmaseg, M_AGP); 917 free(mem, M_AGP); 918 return NULL; 919 } 920 memset(mem->am_virtual, 0, size); 921 } else if (type != 1) { 922 if (bus_dmamap_create(sc->as_dmat, size, size / PAGE_SIZE + 1, 923 size, 0, BUS_DMA_NOWAIT, 924 &mem->am_dmamap) != 0) { 925 free(mem, M_AGP); 926 return NULL; 927 } 928 } 929 930 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link); 931 sc->as_allocated += size; 932 933 return mem; 934 } 935 936 static int 937 agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem) 938 { 939 if (mem->am_is_bound) 940 return EBUSY; 941 942 if (mem->am_type == 2) { 943 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap, 944 mem->am_virtual, mem->am_dmaseg, mem->am_nseg); 945 free(mem->am_dmaseg, M_AGP); 946 } 947 948 sc->as_allocated -= mem->am_size; 949 TAILQ_REMOVE(&sc->as_memory, mem, am_link); 950 free(mem, M_AGP); 951 return 0; 952 } 953 954 static int 955 agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem, 956 off_t offset) 957 { 958 struct agp_i810_softc *isc = sc->as_chipc; 959 u_int32_t regval, i; 960 961 /* 962 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 963 * X server for mysterious reasons which leads to crashes if we write 964 * to the GTT through the MMIO window. 965 * Until the issue is solved, simply restore it. 966 */ 967 regval = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL); 968 if (regval != (isc->gatt->ag_physical | 1)) { 969 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%x - fixing\n", 970 regval); 971 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 972 isc->gatt->ag_physical | 1); 973 } 974 975 if (mem->am_type == 2) { 976 agp_i810_write_gtt_entry(isc, offset, mem->am_physical | 1); 977 mem->am_offset = offset; 978 mem->am_is_bound = 1; 979 return 0; 980 } 981 982 if (mem->am_type != 1) 983 return agp_generic_bind_memory(sc, mem, offset); 984 985 if (isc->chiptype != CHIP_I810) 986 return EINVAL; 987 988 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 989 agp_i810_write_gtt_entry(isc, offset, i | 3); 990 mem->am_is_bound = 1; 991 return 0; 992 } 993 994 static int 995 agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem) 996 { 997 struct agp_i810_softc *isc = sc->as_chipc; 998 u_int32_t i; 999 1000 if (mem->am_type == 2) { 1001 agp_i810_write_gtt_entry(isc, mem->am_offset, 0); 1002 mem->am_offset = 0; 1003 mem->am_is_bound = 0; 1004 return 0; 1005 } 1006 1007 if (mem->am_type != 1) 1008 return agp_generic_unbind_memory(sc, mem); 1009 1010 if (isc->chiptype != CHIP_I810) 1011 return EINVAL; 1012 1013 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1014 agp_i810_write_gtt_entry(isc, i, 0); 1015 mem->am_is_bound = 0; 1016 return 0; 1017 } 1018 1019 static bool 1020 agp_i810_resume(device_t dv, const pmf_qual_t *qual) 1021 { 1022 struct agp_softc *sc = device_private(dv); 1023 struct agp_i810_softc *isc = sc->as_chipc; 1024 1025 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 1026 agp_flush_cache(); 1027 1028 return true; 1029 } 1030
Indexes created Thu Sep 25 06:09:39 GMT 2025