agp_i810.c revision 1.70
1 /* $NetBSD: agp_i810.c,v 1.70 2011/01/25 10:52:11 gsutre Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/pci/agp_i810.c,v 1.4 2001/07/05 21:28:47 jhb Exp $ 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.70 2011/01/25 10:52:11 gsutre Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/proc.h> 40 #include <sys/device.h> 41 #include <sys/conf.h> 42 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcidevs.h> 46 #include <dev/pci/agpvar.h> 47 #include <dev/pci/agpreg.h> 48 49 #include <sys/agpio.h> 50 51 #include <sys/bus.h> 52 53 #include "agp_intel.h" 54 55 #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off) 56 #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off) 57 #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v) 58 59 #define CHIP_I810 0 /* i810/i815 */ 60 #define CHIP_I830 1 /* 830M/845G */ 61 #define CHIP_I855 2 /* 852GM/855GM/865G */ 62 #define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */ 63 #define CHIP_I965 4 /* 965Q/965PM */ 64 #define CHIP_G33 5 /* G33/Q33/Q35 */ 65 #define CHIP_G4X 6 /* G45/Q45 */ 66 67 struct agp_i810_softc { 68 u_int32_t initial_aperture; /* aperture size at startup */ 69 struct agp_gatt *gatt; 70 int chiptype; /* i810-like or i830 */ 71 u_int32_t dcache_size; /* i810 only */ 72 u_int32_t stolen; /* number of i830/845 gtt entries 73 for stolen memory */ 74 bus_space_tag_t bst; /* register bus_space tag */ 75 bus_space_handle_t bsh; /* register bus_space handle */ 76 bus_space_tag_t gtt_bst; /* GTT bus_space tag */ 77 bus_space_handle_t gtt_bsh; /* GTT bus_space handle */ 78 struct pci_attach_args vga_pa; 79 80 u_int32_t pgtblctl; 81 }; 82 83 /* XXX hack, see below */ 84 static bus_addr_t agp_i810_vga_regbase; 85 static bus_space_handle_t agp_i810_vga_bsh; 86 87 static u_int32_t agp_i810_get_aperture(struct agp_softc *); 88 static int agp_i810_set_aperture(struct agp_softc *, u_int32_t); 89 static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t); 90 static int agp_i810_unbind_page(struct agp_softc *, off_t); 91 static void agp_i810_flush_tlb(struct agp_softc *); 92 static int agp_i810_enable(struct agp_softc *, u_int32_t mode); 93 static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int, 94 vsize_t); 95 static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *); 96 static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, off_t); 97 static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *); 98 99 static bool agp_i810_resume(device_t, const pmf_qual_t *); 100 static int agp_i810_init(struct agp_softc *); 101 102 static int agp_i810_init(struct agp_softc *); 103 static void agp_i810_write_gtt_entry(struct agp_i810_softc *, off_t, 104 u_int32_t); 105 106 static struct agp_methods agp_i810_methods = { 107 agp_i810_get_aperture, 108 agp_i810_set_aperture, 109 agp_i810_bind_page, 110 agp_i810_unbind_page, 111 agp_i810_flush_tlb, 112 agp_i810_enable, 113 agp_i810_alloc_memory, 114 agp_i810_free_memory, 115 agp_i810_bind_memory, 116 agp_i810_unbind_memory, 117 }; 118 119 static void 120 agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, u_int32_t v) 121 { 122 u_int32_t base_off; 123 124 base_off = 0; 125 126 switch (isc->chiptype) { 127 case CHIP_I810: 128 case CHIP_I830: 129 case CHIP_I855: 130 base_off = AGP_I810_GTT; 131 break; 132 case CHIP_I965: 133 base_off = AGP_I965_GTT; 134 break; 135 case CHIP_G4X: 136 base_off = AGP_G4X_GTT; 137 break; 138 case CHIP_I915: 139 case CHIP_G33: 140 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, 141 (u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4, (v)); 142 return; 143 } 144 145 WRITE4(base_off + (u_int32_t)(off >> AGP_PAGE_SHIFT) * 4, v); 146 } 147 148 /* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */ 149 static int 150 agp_i810_vgamatch(struct pci_attach_args *pa) 151 { 152 153 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 154 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 155 return (0); 156 157 switch (PCI_PRODUCT(pa->pa_id)) { 158 case PCI_PRODUCT_INTEL_82810_GC: 159 case PCI_PRODUCT_INTEL_82810_DC100_GC: 160 case PCI_PRODUCT_INTEL_82810E_GC: 161 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 162 case PCI_PRODUCT_INTEL_82830MP_IV: 163 case PCI_PRODUCT_INTEL_82845G_IGD: 164 case PCI_PRODUCT_INTEL_82855GM_IGD: 165 case PCI_PRODUCT_INTEL_82865_IGD: 166 case PCI_PRODUCT_INTEL_82915G_IGD: 167 case PCI_PRODUCT_INTEL_82915GM_IGD: 168 case PCI_PRODUCT_INTEL_82945P_IGD: 169 case PCI_PRODUCT_INTEL_82945GM_IGD: 170 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 171 case PCI_PRODUCT_INTEL_82945GME_IGD: 172 case PCI_PRODUCT_INTEL_E7221_IGD: 173 case PCI_PRODUCT_INTEL_82965Q_IGD: 174 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 175 case PCI_PRODUCT_INTEL_82965PM_IGD: 176 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 177 case PCI_PRODUCT_INTEL_82G33_IGD: 178 case PCI_PRODUCT_INTEL_82G33_IGD_1: 179 case PCI_PRODUCT_INTEL_82965G_IGD: 180 case PCI_PRODUCT_INTEL_82965G_IGD_1: 181 case PCI_PRODUCT_INTEL_82965GME_IGD: 182 case PCI_PRODUCT_INTEL_82Q35_IGD: 183 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 184 case PCI_PRODUCT_INTEL_82Q33_IGD: 185 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 186 case PCI_PRODUCT_INTEL_82G35_IGD: 187 case PCI_PRODUCT_INTEL_82G35_IGD_1: 188 case PCI_PRODUCT_INTEL_82946GZ_IGD: 189 case PCI_PRODUCT_INTEL_82GM45_IGD: 190 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 191 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 192 case PCI_PRODUCT_INTEL_82Q45_IGD: 193 case PCI_PRODUCT_INTEL_82G45_IGD: 194 case PCI_PRODUCT_INTEL_82G41_IGD: 195 case PCI_PRODUCT_INTEL_82B43_IGD: 196 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 197 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 198 return (1); 199 } 200 201 return (0); 202 } 203 204 static int 205 agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg) 206 { 207 /* 208 * Find the aperture. Don't map it (yet), this would 209 * eat KVA. 210 */ 211 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 212 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize, 213 &sc->as_apflags) != 0) 214 return ENXIO; 215 216 sc->as_apt = pa->pa_memt; 217 218 return 0; 219 } 220 221 int 222 agp_i810_attach(device_t parent, device_t self, void *aux) 223 { 224 struct agp_softc *sc = device_private(self); 225 struct agp_i810_softc *isc; 226 struct agp_gatt *gatt; 227 int error, apbase; 228 bus_addr_t mmadr; 229 bus_size_t mmadrsize; 230 231 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 232 if (isc == NULL) { 233 aprint_error(": can't allocate chipset-specific softc\n"); 234 return ENOMEM; 235 } 236 sc->as_chipc = isc; 237 sc->as_methods = &agp_i810_methods; 238 239 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) { 240 #if NAGP_INTEL > 0 241 const struct pci_attach_args *pa = aux; 242 243 switch (PCI_PRODUCT(pa->pa_id)) { 244 case PCI_PRODUCT_INTEL_82840_HB: 245 case PCI_PRODUCT_INTEL_82865_HB: 246 case PCI_PRODUCT_INTEL_82845G_DRAM: 247 case PCI_PRODUCT_INTEL_82815_FULL_HUB: 248 case PCI_PRODUCT_INTEL_82855GM_MCH: 249 return agp_intel_attach(parent, self, aux); 250 } 251 #endif 252 aprint_error(": can't find internal VGA device config space\n"); 253 free(isc, M_AGP); 254 return ENOENT; 255 } 256 257 /* XXXfvdl */ 258 sc->as_dmat = isc->vga_pa.pa_dmat; 259 260 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 261 case PCI_PRODUCT_INTEL_82810_GC: 262 case PCI_PRODUCT_INTEL_82810_DC100_GC: 263 case PCI_PRODUCT_INTEL_82810E_GC: 264 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 265 isc->chiptype = CHIP_I810; 266 break; 267 case PCI_PRODUCT_INTEL_82830MP_IV: 268 case PCI_PRODUCT_INTEL_82845G_IGD: 269 isc->chiptype = CHIP_I830; 270 break; 271 case PCI_PRODUCT_INTEL_82855GM_IGD: 272 case PCI_PRODUCT_INTEL_82865_IGD: 273 isc->chiptype = CHIP_I855; 274 break; 275 case PCI_PRODUCT_INTEL_82915G_IGD: 276 case PCI_PRODUCT_INTEL_82915GM_IGD: 277 case PCI_PRODUCT_INTEL_82945P_IGD: 278 case PCI_PRODUCT_INTEL_82945GM_IGD: 279 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 280 case PCI_PRODUCT_INTEL_82945GME_IGD: 281 case PCI_PRODUCT_INTEL_E7221_IGD: 282 isc->chiptype = CHIP_I915; 283 break; 284 case PCI_PRODUCT_INTEL_82965Q_IGD: 285 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 286 case PCI_PRODUCT_INTEL_82965PM_IGD: 287 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 288 case PCI_PRODUCT_INTEL_82965G_IGD: 289 case PCI_PRODUCT_INTEL_82965G_IGD_1: 290 case PCI_PRODUCT_INTEL_82965GME_IGD: 291 case PCI_PRODUCT_INTEL_82946GZ_IGD: 292 case PCI_PRODUCT_INTEL_82G35_IGD: 293 case PCI_PRODUCT_INTEL_82G35_IGD_1: 294 isc->chiptype = CHIP_I965; 295 break; 296 case PCI_PRODUCT_INTEL_82Q35_IGD: 297 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 298 case PCI_PRODUCT_INTEL_82G33_IGD: 299 case PCI_PRODUCT_INTEL_82G33_IGD_1: 300 case PCI_PRODUCT_INTEL_82Q33_IGD: 301 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 302 isc->chiptype = CHIP_G33; 303 break; 304 case PCI_PRODUCT_INTEL_82GM45_IGD: 305 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 306 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 307 case PCI_PRODUCT_INTEL_82Q45_IGD: 308 case PCI_PRODUCT_INTEL_82G45_IGD: 309 case PCI_PRODUCT_INTEL_82G41_IGD: 310 case PCI_PRODUCT_INTEL_82B43_IGD: 311 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 312 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 313 isc->chiptype = CHIP_G4X; 314 break; 315 } 316 317 switch (isc->chiptype) { 318 case CHIP_I915: 319 case CHIP_G33: 320 apbase = AGP_I915_GMADR; 321 break; 322 case CHIP_I965: 323 case CHIP_G4X: 324 apbase = AGP_I965_GMADR; 325 break; 326 default: 327 apbase = AGP_I810_GMADR; 328 break; 329 } 330 331 if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) { 332 error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase); 333 } else { 334 error = agp_map_aperture(&isc->vga_pa, sc, apbase); 335 } 336 if (error != 0) { 337 aprint_error(": can't map aperture\n"); 338 free(isc, M_AGP); 339 return error; 340 } 341 342 if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33) { 343 error = pci_mapreg_map(&isc->vga_pa, AGP_I915_MMADR, 344 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 345 &mmadr, &mmadrsize); 346 if (error != 0) { 347 aprint_error(": can't map mmadr registers\n"); 348 agp_generic_detach(sc); 349 return error; 350 } 351 error = pci_mapreg_map(&isc->vga_pa, AGP_I915_GTTADR, 352 PCI_MAPREG_TYPE_MEM, 0, &isc->gtt_bst, &isc->gtt_bsh, 353 NULL, NULL); 354 if (error != 0) { 355 aprint_error(": can't map gttadr registers\n"); 356 /* XXX we should release mmadr here */ 357 agp_generic_detach(sc); 358 return error; 359 } 360 } else if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) { 361 error = pci_mapreg_map(&isc->vga_pa, AGP_I965_MMADR, 362 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 363 &mmadr, &mmadrsize); 364 if (error != 0) { 365 aprint_error(": can't map mmadr registers\n"); 366 agp_generic_detach(sc); 367 return error; 368 } 369 } else { 370 error = pci_mapreg_map(&isc->vga_pa, AGP_I810_MMADR, 371 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 372 &mmadr, &mmadrsize); 373 if (error != 0) { 374 aprint_error(": can't map mmadr registers\n"); 375 agp_generic_detach(sc); 376 return error; 377 } 378 } 379 380 isc->initial_aperture = AGP_GET_APERTURE(sc); 381 382 gatt = malloc(sizeof(struct agp_gatt), M_AGP, M_NOWAIT); 383 if (!gatt) { 384 agp_generic_detach(sc); 385 return ENOMEM; 386 } 387 isc->gatt = gatt; 388 389 gatt->ag_entries = AGP_GET_APERTURE(sc) >> AGP_PAGE_SHIFT; 390 391 if (!pmf_device_register(self, NULL, agp_i810_resume)) 392 aprint_error_dev(self, "couldn't establish power handler\n"); 393 394 /* 395 * XXX horrible hack to allow drm code to use our mapping 396 * of VGA chip registers 397 */ 398 agp_i810_vga_regbase = mmadr; 399 agp_i810_vga_bsh = isc->bsh; 400 401 return agp_i810_init(sc); 402 } 403 404 /* 405 * XXX horrible hack to allow drm code to use our mapping 406 * of VGA chip registers 407 */ 408 int 409 agp_i810_borrow(bus_addr_t base, bus_space_handle_t *hdlp) 410 { 411 412 if (!agp_i810_vga_regbase || base != agp_i810_vga_regbase) 413 return 0; 414 *hdlp = agp_i810_vga_bsh; 415 return 1; 416 } 417 418 static int agp_i810_init(struct agp_softc *sc) 419 { 420 struct agp_i810_softc *isc; 421 struct agp_gatt *gatt; 422 423 isc = sc->as_chipc; 424 gatt = isc->gatt; 425 426 if (isc->chiptype == CHIP_I810) { 427 void *virtual; 428 int dummyseg; 429 430 /* Some i810s have on-chip memory called dcache */ 431 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 432 isc->dcache_size = 4 * 1024 * 1024; 433 else 434 isc->dcache_size = 0; 435 436 /* According to the specs the gatt on the i810 must be 64k */ 437 if (agp_alloc_dmamem(sc->as_dmat, 64 * 1024, 438 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical, 439 &gatt->ag_dmaseg, 1, &dummyseg) != 0) { 440 free(gatt, M_AGP); 441 agp_generic_detach(sc); 442 return ENOMEM; 443 } 444 gatt->ag_virtual = (uint32_t *)virtual; 445 gatt->ag_size = gatt->ag_entries * sizeof(u_int32_t); 446 memset(gatt->ag_virtual, 0, gatt->ag_size); 447 448 agp_flush_cache(); 449 /* Install the GATT. */ 450 WRITE4(AGP_I810_PGTBL_CTL, gatt->ag_physical | 1); 451 } else if (isc->chiptype == CHIP_I830) { 452 /* The i830 automatically initializes the 128k gatt on boot. */ 453 pcireg_t reg; 454 u_int32_t pgtblctl; 455 u_int16_t gcc1; 456 457 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 458 gcc1 = (u_int16_t)(reg >> 16); 459 switch (gcc1 & AGP_I830_GCC1_GMS) { 460 case AGP_I830_GCC1_GMS_STOLEN_512: 461 isc->stolen = (512 - 132) * 1024 / 4096; 462 break; 463 case AGP_I830_GCC1_GMS_STOLEN_1024: 464 isc->stolen = (1024 - 132) * 1024 / 4096; 465 break; 466 case AGP_I830_GCC1_GMS_STOLEN_8192: 467 isc->stolen = (8192 - 132) * 1024 / 4096; 468 break; 469 default: 470 isc->stolen = 0; 471 aprint_error( 472 ": unknown memory configuration, disabling\n"); 473 agp_generic_detach(sc); 474 return EINVAL; 475 } 476 477 if (isc->stolen > 0) { 478 aprint_normal(": detected %dk stolen memory\n%s", 479 isc->stolen * 4, device_xname(sc->as_dev)); 480 } 481 482 /* GATT address is already in there, make sure it's enabled */ 483 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 484 pgtblctl |= 1; 485 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 486 487 gatt->ag_physical = pgtblctl & ~1; 488 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 489 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 || 490 isc->chiptype == CHIP_G4X) { 491 pcireg_t reg; 492 u_int32_t pgtblctl, gtt_size, stolen; 493 u_int16_t gcc1; 494 495 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1); 496 gcc1 = (u_int16_t)(reg >> 16); 497 498 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 499 500 /* Stolen memory is set up at the beginning of the aperture by 501 * the BIOS, consisting of the GATT followed by 4kb for the 502 * BIOS display. 503 */ 504 switch (isc->chiptype) { 505 case CHIP_I855: 506 gtt_size = 128; 507 break; 508 case CHIP_I915: 509 gtt_size = 256; 510 break; 511 case CHIP_I965: 512 switch (pgtblctl & AGP_I810_PGTBL_SIZE_MASK) { 513 case AGP_I810_PGTBL_SIZE_128KB: 514 case AGP_I810_PGTBL_SIZE_512KB: 515 gtt_size = 512; 516 break; 517 case AGP_I965_PGTBL_SIZE_1MB: 518 gtt_size = 1024; 519 break; 520 case AGP_I965_PGTBL_SIZE_2MB: 521 gtt_size = 2048; 522 break; 523 case AGP_I965_PGTBL_SIZE_1_5MB: 524 gtt_size = 1024 + 512; 525 break; 526 default: 527 aprint_error("Bad PGTBL size\n"); 528 agp_generic_detach(sc); 529 return EINVAL; 530 } 531 break; 532 case CHIP_G33: 533 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 534 case AGP_G33_PGTBL_SIZE_1M: 535 gtt_size = 1024; 536 break; 537 case AGP_G33_PGTBL_SIZE_2M: 538 gtt_size = 2048; 539 break; 540 default: 541 aprint_error(": Bad PGTBL size\n"); 542 agp_generic_detach(sc); 543 return EINVAL; 544 } 545 break; 546 case CHIP_G4X: 547 gtt_size = 0; 548 break; 549 default: 550 aprint_error(": bad chiptype\n"); 551 agp_generic_detach(sc); 552 return EINVAL; 553 } 554 555 switch (gcc1 & AGP_I855_GCC1_GMS) { 556 case AGP_I855_GCC1_GMS_STOLEN_1M: 557 stolen = 1024; 558 break; 559 case AGP_I855_GCC1_GMS_STOLEN_4M: 560 stolen = 4 * 1024; 561 break; 562 case AGP_I855_GCC1_GMS_STOLEN_8M: 563 stolen = 8 * 1024; 564 break; 565 case AGP_I855_GCC1_GMS_STOLEN_16M: 566 stolen = 16 * 1024; 567 break; 568 case AGP_I855_GCC1_GMS_STOLEN_32M: 569 stolen = 32 * 1024; 570 break; 571 case AGP_I915_GCC1_GMS_STOLEN_48M: 572 stolen = 48 * 1024; 573 break; 574 case AGP_I915_GCC1_GMS_STOLEN_64M: 575 stolen = 64 * 1024; 576 break; 577 case AGP_G33_GCC1_GMS_STOLEN_128M: 578 stolen = 128 * 1024; 579 break; 580 case AGP_G33_GCC1_GMS_STOLEN_256M: 581 stolen = 256 * 1024; 582 break; 583 case AGP_G4X_GCC1_GMS_STOLEN_96M: 584 stolen = 96 * 1024; 585 break; 586 case AGP_G4X_GCC1_GMS_STOLEN_160M: 587 stolen = 160 * 1024; 588 break; 589 case AGP_G4X_GCC1_GMS_STOLEN_224M: 590 stolen = 224 * 1024; 591 break; 592 case AGP_G4X_GCC1_GMS_STOLEN_352M: 593 stolen = 352 * 1024; 594 break; 595 default: 596 aprint_error( 597 ": unknown memory configuration, disabling\n"); 598 agp_generic_detach(sc); 599 return EINVAL; 600 } 601 602 switch (gcc1 & AGP_I855_GCC1_GMS) { 603 case AGP_I915_GCC1_GMS_STOLEN_48M: 604 case AGP_I915_GCC1_GMS_STOLEN_64M: 605 if (isc->chiptype != CHIP_I915 && 606 isc->chiptype != CHIP_I965 && 607 isc->chiptype != CHIP_G33 && 608 isc->chiptype != CHIP_G4X) 609 stolen = 0; 610 break; 611 case AGP_G33_GCC1_GMS_STOLEN_128M: 612 case AGP_G33_GCC1_GMS_STOLEN_256M: 613 if (isc->chiptype != CHIP_I965 && 614 isc->chiptype != CHIP_G33 && 615 isc->chiptype != CHIP_G4X) 616 stolen = 0; 617 break; 618 case AGP_G4X_GCC1_GMS_STOLEN_96M: 619 case AGP_G4X_GCC1_GMS_STOLEN_160M: 620 case AGP_G4X_GCC1_GMS_STOLEN_224M: 621 case AGP_G4X_GCC1_GMS_STOLEN_352M: 622 if (isc->chiptype != CHIP_I965 && 623 isc->chiptype != CHIP_G4X) 624 stolen = 0; 625 break; 626 } 627 628 /* BIOS space */ 629 gtt_size += 4; 630 631 isc->stolen = (stolen - gtt_size) * 1024 / 4096; 632 633 if (isc->stolen > 0) { 634 aprint_normal(": detected %dk stolen memory\n%s", 635 isc->stolen * 4, device_xname(sc->as_dev)); 636 } 637 638 /* GATT address is already in there, make sure it's enabled */ 639 pgtblctl |= 1; 640 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 641 642 gatt->ag_physical = pgtblctl & ~1; 643 } 644 645 /* 646 * Make sure the chipset can see everything. 647 */ 648 agp_flush_cache(); 649 650 return 0; 651 } 652 653 #if 0 654 static int 655 agp_i810_detach(struct agp_softc *sc) 656 { 657 int error; 658 struct agp_i810_softc *isc = sc->as_chipc; 659 660 error = agp_generic_detach(sc); 661 if (error) 662 return error; 663 664 /* Clear the GATT base. */ 665 if (sc->chiptype == CHIP_I810) { 666 WRITE4(AGP_I810_PGTBL_CTL, 0); 667 } else { 668 unsigned int pgtblctl; 669 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 670 pgtblctl &= ~1; 671 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 672 } 673 674 /* Put the aperture back the way it started. */ 675 AGP_SET_APERTURE(sc, isc->initial_aperture); 676 677 if (sc->chiptype == CHIP_I810) { 678 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap, 679 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 680 } 681 free(sc->gatt, M_AGP); 682 683 return 0; 684 } 685 #endif 686 687 static u_int32_t 688 agp_i810_get_aperture(struct agp_softc *sc) 689 { 690 struct agp_i810_softc *isc = sc->as_chipc; 691 pcireg_t reg; 692 u_int32_t size; 693 u_int16_t miscc, gcc1, msac; 694 695 size = 0; 696 697 switch (isc->chiptype) { 698 case CHIP_I810: 699 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 700 miscc = (u_int16_t)(reg >> 16); 701 if ((miscc & AGP_I810_MISCC_WINSIZE) == 702 AGP_I810_MISCC_WINSIZE_32) 703 size = 32 * 1024 * 1024; 704 else 705 size = 64 * 1024 * 1024; 706 break; 707 case CHIP_I830: 708 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 709 gcc1 = (u_int16_t)(reg >> 16); 710 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 711 size = 64 * 1024 * 1024; 712 else 713 size = 128 * 1024 * 1024; 714 break; 715 case CHIP_I855: 716 size = 128 * 1024 * 1024; 717 break; 718 case CHIP_I915: 719 case CHIP_G33: 720 case CHIP_G4X: 721 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I915_MSAC); 722 msac = (u_int16_t)(reg >> 16); 723 if (msac & AGP_I915_MSAC_APER_128M) 724 size = 128 * 1024 * 1024; 725 else 726 size = 256 * 1024 * 1024; 727 break; 728 case CHIP_I965: 729 size = 512 * 1024 * 1024; 730 break; 731 default: 732 aprint_error(": Unknown chipset\n"); 733 } 734 735 return size; 736 } 737 738 static int 739 agp_i810_set_aperture(struct agp_softc *sc, u_int32_t aperture) 740 { 741 struct agp_i810_softc *isc = sc->as_chipc; 742 pcireg_t reg; 743 u_int16_t miscc, gcc1; 744 745 switch (isc->chiptype) { 746 case CHIP_I810: 747 /* 748 * Double check for sanity. 749 */ 750 if (aperture != (32 * 1024 * 1024) && 751 aperture != (64 * 1024 * 1024)) { 752 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 753 aperture); 754 return EINVAL; 755 } 756 757 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 758 miscc = (u_int16_t)(reg >> 16); 759 miscc &= ~AGP_I810_MISCC_WINSIZE; 760 if (aperture == 32 * 1024 * 1024) 761 miscc |= AGP_I810_MISCC_WINSIZE_32; 762 else 763 miscc |= AGP_I810_MISCC_WINSIZE_64; 764 765 reg &= 0x0000ffff; 766 reg |= ((pcireg_t)miscc) << 16; 767 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I810_SMRAM, reg); 768 break; 769 case CHIP_I830: 770 if (aperture != (64 * 1024 * 1024) && 771 aperture != (128 * 1024 * 1024)) { 772 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 773 aperture); 774 return EINVAL; 775 } 776 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 777 gcc1 = (u_int16_t)(reg >> 16); 778 gcc1 &= ~AGP_I830_GCC1_GMASIZE; 779 if (aperture == 64 * 1024 * 1024) 780 gcc1 |= AGP_I830_GCC1_GMASIZE_64; 781 else 782 gcc1 |= AGP_I830_GCC1_GMASIZE_128; 783 784 reg &= 0x0000ffff; 785 reg |= ((pcireg_t)gcc1) << 16; 786 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I830_GCC0, reg); 787 break; 788 case CHIP_I855: 789 case CHIP_I915: 790 if (aperture != agp_i810_get_aperture(sc)) { 791 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 792 aperture); 793 return EINVAL; 794 } 795 break; 796 case CHIP_I965: 797 if (aperture != 512 * 1024 * 1024) { 798 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 799 aperture); 800 return EINVAL; 801 } 802 break; 803 } 804 805 return 0; 806 } 807 808 static int 809 agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 810 { 811 struct agp_i810_softc *isc = sc->as_chipc; 812 813 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) { 814 #ifdef AGP_DEBUG 815 printf("%s: failed: offset 0x%08x, shift %d, entries %d\n", 816 device_xname(sc->as_dev), (int)offset, AGP_PAGE_SHIFT, 817 isc->gatt->ag_entries); 818 #endif 819 return EINVAL; 820 } 821 822 if (isc->chiptype != CHIP_I810) { 823 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 824 #ifdef AGP_DEBUG 825 printf("%s: trying to bind into stolen memory\n", 826 device_xname(sc->as_dev)); 827 #endif 828 return EINVAL; 829 } 830 } 831 832 agp_i810_write_gtt_entry(isc, offset, physical | 1); 833 return 0; 834 } 835 836 static int 837 agp_i810_unbind_page(struct agp_softc *sc, off_t offset) 838 { 839 struct agp_i810_softc *isc = sc->as_chipc; 840 841 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 842 return EINVAL; 843 844 if (isc->chiptype != CHIP_I810 ) { 845 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 846 #ifdef AGP_DEBUG 847 printf("%s: trying to unbind from stolen memory\n", 848 device_xname(sc->as_dev)); 849 #endif 850 return EINVAL; 851 } 852 } 853 854 agp_i810_write_gtt_entry(isc, offset, 0); 855 return 0; 856 } 857 858 /* 859 * Writing via memory mapped registers already flushes all TLBs. 860 */ 861 static void 862 agp_i810_flush_tlb(struct agp_softc *sc) 863 { 864 } 865 866 static int 867 agp_i810_enable(struct agp_softc *sc, u_int32_t mode) 868 { 869 870 return 0; 871 } 872 873 static struct agp_memory * 874 agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size) 875 { 876 struct agp_i810_softc *isc = sc->as_chipc; 877 struct agp_memory *mem; 878 879 #ifdef AGP_DEBUG 880 printf("AGP: alloc(%d, 0x%x)\n", type, (int) size); 881 #endif 882 883 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 884 return 0; 885 886 if (sc->as_allocated + size > sc->as_maxmem) 887 return 0; 888 889 if (type == 1) { 890 /* 891 * Mapping local DRAM into GATT. 892 */ 893 if (isc->chiptype != CHIP_I810 ) 894 return 0; 895 if (size != isc->dcache_size) 896 return 0; 897 } else if (type == 2) { 898 /* 899 * Bogus mapping for the hardware cursor. 900 */ 901 if (size != AGP_PAGE_SIZE && size != 4 * AGP_PAGE_SIZE) 902 return 0; 903 } 904 905 mem = malloc(sizeof *mem, M_AGP, M_WAITOK|M_ZERO); 906 if (mem == NULL) 907 return NULL; 908 mem->am_id = sc->as_nextid++; 909 mem->am_size = size; 910 mem->am_type = type; 911 912 if (type == 2) { 913 /* 914 * Allocate and wire down the memory now so that we can 915 * get its physical address. 916 */ 917 mem->am_dmaseg = malloc(sizeof *mem->am_dmaseg, M_AGP, 918 M_WAITOK); 919 if (mem->am_dmaseg == NULL) { 920 free(mem, M_AGP); 921 return NULL; 922 } 923 if (agp_alloc_dmamem(sc->as_dmat, size, 0, 924 &mem->am_dmamap, &mem->am_virtual, &mem->am_physical, 925 mem->am_dmaseg, 1, &mem->am_nseg) != 0) { 926 free(mem->am_dmaseg, M_AGP); 927 free(mem, M_AGP); 928 return NULL; 929 } 930 memset(mem->am_virtual, 0, size); 931 } else if (type != 1) { 932 if (bus_dmamap_create(sc->as_dmat, size, size / PAGE_SIZE + 1, 933 size, 0, BUS_DMA_NOWAIT, 934 &mem->am_dmamap) != 0) { 935 free(mem, M_AGP); 936 return NULL; 937 } 938 } 939 940 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link); 941 sc->as_allocated += size; 942 943 return mem; 944 } 945 946 static int 947 agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem) 948 { 949 if (mem->am_is_bound) 950 return EBUSY; 951 952 if (mem->am_type == 2) { 953 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap, 954 mem->am_virtual, mem->am_dmaseg, mem->am_nseg); 955 free(mem->am_dmaseg, M_AGP); 956 } 957 958 sc->as_allocated -= mem->am_size; 959 TAILQ_REMOVE(&sc->as_memory, mem, am_link); 960 free(mem, M_AGP); 961 return 0; 962 } 963 964 static int 965 agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem, 966 off_t offset) 967 { 968 struct agp_i810_softc *isc = sc->as_chipc; 969 u_int32_t regval, i; 970 971 if (mem->am_is_bound != 0) 972 return EINVAL; 973 974 /* 975 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 976 * X server for mysterious reasons which leads to crashes if we write 977 * to the GTT through the MMIO window. 978 * Until the issue is solved, simply restore it. 979 */ 980 regval = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL); 981 if (regval != (isc->gatt->ag_physical | 1)) { 982 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%x - fixing\n", 983 regval); 984 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 985 isc->gatt->ag_physical | 1); 986 } 987 988 if (mem->am_type == 2) { 989 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 990 agp_i810_bind_page(sc, offset + i, 991 mem->am_physical + i); 992 mem->am_offset = offset; 993 mem->am_is_bound = 1; 994 return 0; 995 } 996 997 if (mem->am_type != 1) 998 return agp_generic_bind_memory(sc, mem, offset); 999 1000 if (isc->chiptype != CHIP_I810) 1001 return EINVAL; 1002 1003 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1004 agp_i810_write_gtt_entry(isc, i, i | 3); 1005 mem->am_is_bound = 1; 1006 return 0; 1007 } 1008 1009 static int 1010 agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem) 1011 { 1012 struct agp_i810_softc *isc = sc->as_chipc; 1013 u_int32_t i; 1014 1015 if (mem->am_is_bound == 0) 1016 return EINVAL; 1017 1018 if (mem->am_type == 2) { 1019 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1020 agp_i810_unbind_page(sc, mem->am_offset + i); 1021 mem->am_offset = 0; 1022 mem->am_is_bound = 0; 1023 return 0; 1024 } 1025 1026 if (mem->am_type != 1) 1027 return agp_generic_unbind_memory(sc, mem); 1028 1029 if (isc->chiptype != CHIP_I810) 1030 return EINVAL; 1031 1032 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1033 agp_i810_write_gtt_entry(isc, i, 0); 1034 mem->am_is_bound = 0; 1035 return 0; 1036 } 1037 1038 static bool 1039 agp_i810_resume(device_t dv, const pmf_qual_t *qual) 1040 { 1041 struct agp_softc *sc = device_private(dv); 1042 struct agp_i810_softc *isc = sc->as_chipc; 1043 1044 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 1045 agp_flush_cache(); 1046 1047 return true; 1048 } 1049
Indexes created Tue Sep 23 21:09:50 GMT 2025