agp_i810.c revision 1.73.26.1
1 /* $NetBSD: agp_i810.c,v 1.73.26.1 2014/03/05 14:42:40 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.73.26.1 2014/03/05 14:42:40 riastradh Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/proc.h> 40 #include <sys/device.h> 41 #include <sys/conf.h> 42 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcidevs.h> 46 #include <dev/pci/agpvar.h> 47 #include <dev/pci/agpreg.h> 48 #include <dev/pci/agp_i810var.h> 49 50 #include <sys/agpio.h> 51 52 #include <sys/bus.h> 53 54 #include "agp_intel.h" 55 56 struct agp_softc *agp_i810_sc = NULL; 57 58 #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off) 59 #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off) 60 #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v) 61 62 #define CHIP_I810 0 /* i810/i815 */ 63 #define CHIP_I830 1 /* 830M/845G */ 64 #define CHIP_I855 2 /* 852GM/855GM/865G */ 65 #define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */ 66 #define CHIP_I965 4 /* 965Q/965PM */ 67 #define CHIP_G33 5 /* G33/Q33/Q35 */ 68 #define CHIP_G4X 6 /* G45/Q45 */ 69 70 /* XXX hack, see below */ 71 static bus_addr_t agp_i810_vga_regbase; 72 static bus_space_handle_t agp_i810_vga_bsh; 73 74 static u_int32_t agp_i810_get_aperture(struct agp_softc *); 75 static int agp_i810_set_aperture(struct agp_softc *, u_int32_t); 76 static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t); 77 static int agp_i810_unbind_page(struct agp_softc *, off_t); 78 static void agp_i810_flush_tlb(struct agp_softc *); 79 static int agp_i810_enable(struct agp_softc *, u_int32_t mode); 80 static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int, 81 vsize_t); 82 static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *); 83 static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, off_t); 84 static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *); 85 86 static bool agp_i810_resume(device_t, const pmf_qual_t *); 87 static int agp_i810_init(struct agp_softc *); 88 89 static int agp_i810_init(struct agp_softc *); 90 static int agp_i810_write_gtt_entry(struct agp_i810_softc *, off_t, 91 bus_addr_t); 92 93 static struct agp_methods agp_i810_methods = { 94 agp_i810_get_aperture, 95 agp_i810_set_aperture, 96 agp_i810_bind_page, 97 agp_i810_unbind_page, 98 agp_i810_flush_tlb, 99 agp_i810_enable, 100 agp_i810_alloc_memory, 101 agp_i810_free_memory, 102 agp_i810_bind_memory, 103 agp_i810_unbind_memory, 104 }; 105 106 static int 107 agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, bus_addr_t v) 108 { 109 u_int32_t pte; 110 bus_size_t base_off, wroff; 111 112 /* Bits 11:4 (physical start address extension) should be zero. */ 113 if ((v & 0xff0) != 0) 114 return EINVAL; 115 116 pte = (u_int32_t)v; 117 /* 118 * We need to massage the pte if bus_addr_t is wider than 32 bits. 119 * The compiler isn't smart enough, hence the casts to uintmax_t. 120 */ 121 if (sizeof(bus_addr_t) > sizeof(u_int32_t)) { 122 /* 965+ can do 36-bit addressing, add in the extra bits. */ 123 if (isc->chiptype == CHIP_I965 || 124 isc->chiptype == CHIP_G33 || 125 isc->chiptype == CHIP_G4X) { 126 if (((uintmax_t)v >> 36) != 0) 127 return EINVAL; 128 pte |= (v >> 28) & 0xf0; 129 } else { 130 if (((uintmax_t)v >> 32) != 0) 131 return EINVAL; 132 } 133 } 134 135 base_off = 0; 136 wroff = (off >> AGP_PAGE_SHIFT) * 4; 137 138 switch (isc->chiptype) { 139 case CHIP_I810: 140 case CHIP_I830: 141 case CHIP_I855: 142 base_off = AGP_I810_GTT; 143 break; 144 case CHIP_I965: 145 base_off = AGP_I965_GTT; 146 break; 147 case CHIP_G4X: 148 base_off = AGP_G4X_GTT; 149 break; 150 case CHIP_I915: 151 case CHIP_G33: 152 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, wroff, pte); 153 return 0; 154 } 155 156 WRITE4(base_off + wroff, pte); 157 return 0; 158 } 159 160 /* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */ 161 static int 162 agp_i810_vgamatch(const struct pci_attach_args *pa) 163 { 164 165 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 166 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 167 return (0); 168 169 switch (PCI_PRODUCT(pa->pa_id)) { 170 case PCI_PRODUCT_INTEL_82810_GC: 171 case PCI_PRODUCT_INTEL_82810_DC100_GC: 172 case PCI_PRODUCT_INTEL_82810E_GC: 173 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 174 case PCI_PRODUCT_INTEL_82830MP_IV: 175 case PCI_PRODUCT_INTEL_82845G_IGD: 176 case PCI_PRODUCT_INTEL_82855GM_IGD: 177 case PCI_PRODUCT_INTEL_82865_IGD: 178 case PCI_PRODUCT_INTEL_82915G_IGD: 179 case PCI_PRODUCT_INTEL_82915GM_IGD: 180 case PCI_PRODUCT_INTEL_82945P_IGD: 181 case PCI_PRODUCT_INTEL_82945GM_IGD: 182 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 183 case PCI_PRODUCT_INTEL_82945GME_IGD: 184 case PCI_PRODUCT_INTEL_E7221_IGD: 185 case PCI_PRODUCT_INTEL_82965Q_IGD: 186 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 187 case PCI_PRODUCT_INTEL_82965PM_IGD: 188 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 189 case PCI_PRODUCT_INTEL_82G33_IGD: 190 case PCI_PRODUCT_INTEL_82G33_IGD_1: 191 case PCI_PRODUCT_INTEL_82965G_IGD: 192 case PCI_PRODUCT_INTEL_82965G_IGD_1: 193 case PCI_PRODUCT_INTEL_82965GME_IGD: 194 case PCI_PRODUCT_INTEL_82Q35_IGD: 195 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 196 case PCI_PRODUCT_INTEL_82Q33_IGD: 197 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 198 case PCI_PRODUCT_INTEL_82G35_IGD: 199 case PCI_PRODUCT_INTEL_82G35_IGD_1: 200 case PCI_PRODUCT_INTEL_82946GZ_IGD: 201 case PCI_PRODUCT_INTEL_82GM45_IGD: 202 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 203 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 204 case PCI_PRODUCT_INTEL_82Q45_IGD: 205 case PCI_PRODUCT_INTEL_82G45_IGD: 206 case PCI_PRODUCT_INTEL_82G41_IGD: 207 case PCI_PRODUCT_INTEL_82B43_IGD: 208 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 209 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 210 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 211 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 212 return (1); 213 } 214 215 return (0); 216 } 217 218 static int 219 agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg) 220 { 221 /* 222 * Find the aperture. Don't map it (yet), this would 223 * eat KVA. 224 */ 225 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 226 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize, 227 &sc->as_apflags) != 0) 228 return ENXIO; 229 230 sc->as_apt = pa->pa_memt; 231 232 return 0; 233 } 234 235 int 236 agp_i810_attach(device_t parent, device_t self, void *aux) 237 { 238 struct agp_softc *sc = device_private(self); 239 struct agp_i810_softc *isc; 240 struct agp_gatt *gatt; 241 int error, apbase; 242 bus_addr_t mmadr; 243 bus_size_t mmadrsize; 244 245 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 246 if (isc == NULL) { 247 aprint_error(": can't allocate chipset-specific softc\n"); 248 return ENOMEM; 249 } 250 sc->as_chipc = isc; 251 sc->as_methods = &agp_i810_methods; 252 253 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) { 254 #if NAGP_INTEL > 0 255 const struct pci_attach_args *pa = aux; 256 257 switch (PCI_PRODUCT(pa->pa_id)) { 258 case PCI_PRODUCT_INTEL_82840_HB: 259 case PCI_PRODUCT_INTEL_82865_HB: 260 case PCI_PRODUCT_INTEL_82845G_DRAM: 261 case PCI_PRODUCT_INTEL_82815_FULL_HUB: 262 case PCI_PRODUCT_INTEL_82855GM_MCH: 263 return agp_intel_attach(parent, self, aux); 264 } 265 #endif 266 aprint_error(": can't find internal VGA device config space\n"); 267 free(isc, M_AGP); 268 return ENOENT; 269 } 270 271 /* XXXfvdl */ 272 sc->as_dmat = isc->vga_pa.pa_dmat; 273 274 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 275 case PCI_PRODUCT_INTEL_82810_GC: 276 case PCI_PRODUCT_INTEL_82810_DC100_GC: 277 case PCI_PRODUCT_INTEL_82810E_GC: 278 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 279 isc->chiptype = CHIP_I810; 280 break; 281 case PCI_PRODUCT_INTEL_82830MP_IV: 282 case PCI_PRODUCT_INTEL_82845G_IGD: 283 isc->chiptype = CHIP_I830; 284 break; 285 case PCI_PRODUCT_INTEL_82855GM_IGD: 286 case PCI_PRODUCT_INTEL_82865_IGD: 287 isc->chiptype = CHIP_I855; 288 break; 289 case PCI_PRODUCT_INTEL_82915G_IGD: 290 case PCI_PRODUCT_INTEL_82915GM_IGD: 291 case PCI_PRODUCT_INTEL_82945P_IGD: 292 case PCI_PRODUCT_INTEL_82945GM_IGD: 293 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 294 case PCI_PRODUCT_INTEL_82945GME_IGD: 295 case PCI_PRODUCT_INTEL_E7221_IGD: 296 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 297 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 298 isc->chiptype = CHIP_I915; 299 break; 300 case PCI_PRODUCT_INTEL_82965Q_IGD: 301 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 302 case PCI_PRODUCT_INTEL_82965PM_IGD: 303 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 304 case PCI_PRODUCT_INTEL_82965G_IGD: 305 case PCI_PRODUCT_INTEL_82965G_IGD_1: 306 case PCI_PRODUCT_INTEL_82965GME_IGD: 307 case PCI_PRODUCT_INTEL_82946GZ_IGD: 308 case PCI_PRODUCT_INTEL_82G35_IGD: 309 case PCI_PRODUCT_INTEL_82G35_IGD_1: 310 isc->chiptype = CHIP_I965; 311 break; 312 case PCI_PRODUCT_INTEL_82Q35_IGD: 313 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 314 case PCI_PRODUCT_INTEL_82G33_IGD: 315 case PCI_PRODUCT_INTEL_82G33_IGD_1: 316 case PCI_PRODUCT_INTEL_82Q33_IGD: 317 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 318 isc->chiptype = CHIP_G33; 319 break; 320 case PCI_PRODUCT_INTEL_82GM45_IGD: 321 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 322 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 323 case PCI_PRODUCT_INTEL_82Q45_IGD: 324 case PCI_PRODUCT_INTEL_82G45_IGD: 325 case PCI_PRODUCT_INTEL_82G41_IGD: 326 case PCI_PRODUCT_INTEL_82B43_IGD: 327 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 328 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 329 isc->chiptype = CHIP_G4X; 330 break; 331 } 332 333 switch (isc->chiptype) { 334 case CHIP_I915: 335 case CHIP_G33: 336 apbase = AGP_I915_GMADR; 337 break; 338 case CHIP_I965: 339 case CHIP_G4X: 340 apbase = AGP_I965_GMADR; 341 break; 342 default: 343 apbase = AGP_I810_GMADR; 344 break; 345 } 346 347 if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) { 348 error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase); 349 } else { 350 error = agp_map_aperture(&isc->vga_pa, sc, apbase); 351 } 352 if (error != 0) { 353 aprint_error(": can't map aperture\n"); 354 free(isc, M_AGP); 355 return error; 356 } 357 358 if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33) { 359 error = pci_mapreg_map(&isc->vga_pa, AGP_I915_MMADR, 360 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 361 &mmadr, &mmadrsize); 362 if (error != 0) { 363 aprint_error(": can't map mmadr registers\n"); 364 agp_generic_detach(sc); 365 return error; 366 } 367 error = pci_mapreg_map(&isc->vga_pa, AGP_I915_GTTADR, 368 PCI_MAPREG_TYPE_MEM, 0, &isc->gtt_bst, &isc->gtt_bsh, 369 NULL, NULL); 370 if (error != 0) { 371 aprint_error(": can't map gttadr registers\n"); 372 /* XXX we should release mmadr here */ 373 agp_generic_detach(sc); 374 return error; 375 } 376 } else if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) { 377 error = pci_mapreg_map(&isc->vga_pa, AGP_I965_MMADR, 378 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 379 &mmadr, &mmadrsize); 380 if (error != 0) { 381 aprint_error(": can't map mmadr registers\n"); 382 agp_generic_detach(sc); 383 return error; 384 } 385 } else { 386 error = pci_mapreg_map(&isc->vga_pa, AGP_I810_MMADR, 387 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 388 &mmadr, &mmadrsize); 389 if (error != 0) { 390 aprint_error(": can't map mmadr registers\n"); 391 agp_generic_detach(sc); 392 return error; 393 } 394 } 395 396 isc->initial_aperture = AGP_GET_APERTURE(sc); 397 398 gatt = malloc(sizeof(struct agp_gatt), M_AGP, M_NOWAIT); 399 if (!gatt) { 400 agp_generic_detach(sc); 401 return ENOMEM; 402 } 403 isc->gatt = gatt; 404 405 gatt->ag_entries = AGP_GET_APERTURE(sc) >> AGP_PAGE_SHIFT; 406 407 if (!pmf_device_register(self, NULL, agp_i810_resume)) 408 aprint_error_dev(self, "couldn't establish power handler\n"); 409 410 /* 411 * XXX horrible hack to allow drm code to use our mapping 412 * of VGA chip registers 413 */ 414 agp_i810_vga_regbase = mmadr; 415 agp_i810_vga_bsh = isc->bsh; 416 417 return agp_i810_init(sc); 418 } 419 420 /* 421 * XXX horrible hack to allow drm code to use our mapping 422 * of VGA chip registers 423 */ 424 int 425 agp_i810_borrow(bus_addr_t base, bus_space_handle_t *hdlp) 426 { 427 428 if (!agp_i810_vga_regbase || base != agp_i810_vga_regbase) 429 return 0; 430 *hdlp = agp_i810_vga_bsh; 431 return 1; 432 } 433 434 static int agp_i810_init(struct agp_softc *sc) 435 { 436 struct agp_i810_softc *isc; 437 struct agp_gatt *gatt; 438 439 isc = sc->as_chipc; 440 gatt = isc->gatt; 441 442 if (isc->chiptype == CHIP_I810) { 443 void *virtual; 444 int dummyseg; 445 446 /* Some i810s have on-chip memory called dcache */ 447 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 448 isc->dcache_size = 4 * 1024 * 1024; 449 else 450 isc->dcache_size = 0; 451 452 /* According to the specs the gatt on the i810 must be 64k */ 453 if (agp_alloc_dmamem(sc->as_dmat, 64 * 1024, 454 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical, 455 &gatt->ag_dmaseg, 1, &dummyseg) != 0) { 456 free(gatt, M_AGP); 457 agp_generic_detach(sc); 458 return ENOMEM; 459 } 460 gatt->ag_virtual = (uint32_t *)virtual; 461 gatt->ag_size = gatt->ag_entries * sizeof(u_int32_t); 462 memset(gatt->ag_virtual, 0, gatt->ag_size); 463 464 agp_flush_cache(); 465 /* Install the GATT. */ 466 WRITE4(AGP_I810_PGTBL_CTL, gatt->ag_physical | 1); 467 } else if (isc->chiptype == CHIP_I830) { 468 /* The i830 automatically initializes the 128k gatt on boot. */ 469 pcireg_t reg; 470 u_int32_t pgtblctl; 471 u_int16_t gcc1; 472 473 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 474 gcc1 = (u_int16_t)(reg >> 16); 475 switch (gcc1 & AGP_I830_GCC1_GMS) { 476 case AGP_I830_GCC1_GMS_STOLEN_512: 477 isc->stolen = (512 - 132) * 1024 / 4096; 478 break; 479 case AGP_I830_GCC1_GMS_STOLEN_1024: 480 isc->stolen = (1024 - 132) * 1024 / 4096; 481 break; 482 case AGP_I830_GCC1_GMS_STOLEN_8192: 483 isc->stolen = (8192 - 132) * 1024 / 4096; 484 break; 485 default: 486 isc->stolen = 0; 487 aprint_error( 488 ": unknown memory configuration, disabling\n"); 489 agp_generic_detach(sc); 490 return EINVAL; 491 } 492 493 if (isc->stolen > 0) { 494 aprint_normal(": detected %dk stolen memory\n%s", 495 isc->stolen * 4, device_xname(sc->as_dev)); 496 } 497 498 /* GATT address is already in there, make sure it's enabled */ 499 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 500 pgtblctl |= 1; 501 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 502 503 gatt->ag_physical = pgtblctl & ~1; 504 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 505 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 || 506 isc->chiptype == CHIP_G4X) { 507 pcireg_t reg; 508 u_int32_t pgtblctl, gtt_size, stolen; 509 u_int16_t gcc1; 510 511 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1); 512 gcc1 = (u_int16_t)(reg >> 16); 513 514 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 515 516 /* Stolen memory is set up at the beginning of the aperture by 517 * the BIOS, consisting of the GATT followed by 4kb for the 518 * BIOS display. 519 */ 520 switch (isc->chiptype) { 521 case CHIP_I855: 522 gtt_size = 128; 523 break; 524 case CHIP_I915: 525 gtt_size = 256; 526 break; 527 case CHIP_I965: 528 switch (pgtblctl & AGP_I810_PGTBL_SIZE_MASK) { 529 case AGP_I810_PGTBL_SIZE_128KB: 530 case AGP_I810_PGTBL_SIZE_512KB: 531 gtt_size = 512; 532 break; 533 case AGP_I965_PGTBL_SIZE_1MB: 534 gtt_size = 1024; 535 break; 536 case AGP_I965_PGTBL_SIZE_2MB: 537 gtt_size = 2048; 538 break; 539 case AGP_I965_PGTBL_SIZE_1_5MB: 540 gtt_size = 1024 + 512; 541 break; 542 default: 543 aprint_error("Bad PGTBL size\n"); 544 agp_generic_detach(sc); 545 return EINVAL; 546 } 547 break; 548 case CHIP_G33: 549 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 550 case AGP_G33_PGTBL_SIZE_1M: 551 gtt_size = 1024; 552 break; 553 case AGP_G33_PGTBL_SIZE_2M: 554 gtt_size = 2048; 555 break; 556 default: 557 aprint_error(": Bad PGTBL size\n"); 558 agp_generic_detach(sc); 559 return EINVAL; 560 } 561 break; 562 case CHIP_G4X: 563 gtt_size = 0; 564 break; 565 default: 566 aprint_error(": bad chiptype\n"); 567 agp_generic_detach(sc); 568 return EINVAL; 569 } 570 571 switch (gcc1 & AGP_I855_GCC1_GMS) { 572 case AGP_I855_GCC1_GMS_STOLEN_1M: 573 stolen = 1024; 574 break; 575 case AGP_I855_GCC1_GMS_STOLEN_4M: 576 stolen = 4 * 1024; 577 break; 578 case AGP_I855_GCC1_GMS_STOLEN_8M: 579 stolen = 8 * 1024; 580 break; 581 case AGP_I855_GCC1_GMS_STOLEN_16M: 582 stolen = 16 * 1024; 583 break; 584 case AGP_I855_GCC1_GMS_STOLEN_32M: 585 stolen = 32 * 1024; 586 break; 587 case AGP_I915_GCC1_GMS_STOLEN_48M: 588 stolen = 48 * 1024; 589 break; 590 case AGP_I915_GCC1_GMS_STOLEN_64M: 591 stolen = 64 * 1024; 592 break; 593 case AGP_G33_GCC1_GMS_STOLEN_128M: 594 stolen = 128 * 1024; 595 break; 596 case AGP_G33_GCC1_GMS_STOLEN_256M: 597 stolen = 256 * 1024; 598 break; 599 case AGP_G4X_GCC1_GMS_STOLEN_96M: 600 stolen = 96 * 1024; 601 break; 602 case AGP_G4X_GCC1_GMS_STOLEN_160M: 603 stolen = 160 * 1024; 604 break; 605 case AGP_G4X_GCC1_GMS_STOLEN_224M: 606 stolen = 224 * 1024; 607 break; 608 case AGP_G4X_GCC1_GMS_STOLEN_352M: 609 stolen = 352 * 1024; 610 break; 611 default: 612 aprint_error( 613 ": unknown memory configuration, disabling\n"); 614 agp_generic_detach(sc); 615 return EINVAL; 616 } 617 618 switch (gcc1 & AGP_I855_GCC1_GMS) { 619 case AGP_I915_GCC1_GMS_STOLEN_48M: 620 case AGP_I915_GCC1_GMS_STOLEN_64M: 621 if (isc->chiptype != CHIP_I915 && 622 isc->chiptype != CHIP_I965 && 623 isc->chiptype != CHIP_G33 && 624 isc->chiptype != CHIP_G4X) 625 stolen = 0; 626 break; 627 case AGP_G33_GCC1_GMS_STOLEN_128M: 628 case AGP_G33_GCC1_GMS_STOLEN_256M: 629 if (isc->chiptype != CHIP_I965 && 630 isc->chiptype != CHIP_G33 && 631 isc->chiptype != CHIP_G4X) 632 stolen = 0; 633 break; 634 case AGP_G4X_GCC1_GMS_STOLEN_96M: 635 case AGP_G4X_GCC1_GMS_STOLEN_160M: 636 case AGP_G4X_GCC1_GMS_STOLEN_224M: 637 case AGP_G4X_GCC1_GMS_STOLEN_352M: 638 if (isc->chiptype != CHIP_I965 && 639 isc->chiptype != CHIP_G4X) 640 stolen = 0; 641 break; 642 } 643 644 /* BIOS space */ 645 gtt_size += 4; 646 647 isc->stolen = (stolen - gtt_size) * 1024 / 4096; 648 649 if (isc->stolen > 0) { 650 aprint_normal(": detected %dk stolen memory\n%s", 651 isc->stolen * 4, device_xname(sc->as_dev)); 652 } 653 654 /* GATT address is already in there, make sure it's enabled */ 655 pgtblctl |= 1; 656 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 657 658 gatt->ag_physical = pgtblctl & ~1; 659 } 660 661 /* 662 * Make sure the chipset can see everything. 663 */ 664 agp_flush_cache(); 665 666 /* 667 * Publish what we found for kludgey drivers (I'm looking at 668 * you, drm). 669 */ 670 if (agp_i810_sc == NULL) 671 agp_i810_sc = sc; 672 else 673 aprint_error_dev(sc->as_dev, "i810 agp already attached\n"); 674 675 return 0; 676 } 677 678 #if 0 679 static int 680 agp_i810_detach(struct agp_softc *sc) 681 { 682 int error; 683 struct agp_i810_softc *isc = sc->as_chipc; 684 685 error = agp_generic_detach(sc); 686 if (error) 687 return error; 688 689 /* Clear the GATT base. */ 690 if (sc->chiptype == CHIP_I810) { 691 WRITE4(AGP_I810_PGTBL_CTL, 0); 692 } else { 693 unsigned int pgtblctl; 694 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 695 pgtblctl &= ~1; 696 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 697 } 698 699 /* Put the aperture back the way it started. */ 700 AGP_SET_APERTURE(sc, isc->initial_aperture); 701 702 if (sc->chiptype == CHIP_I810) { 703 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap, 704 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 705 } 706 free(sc->gatt, M_AGP); 707 708 return 0; 709 } 710 #endif 711 712 static u_int32_t 713 agp_i810_get_aperture(struct agp_softc *sc) 714 { 715 struct agp_i810_softc *isc = sc->as_chipc; 716 pcireg_t reg; 717 u_int32_t size; 718 u_int16_t miscc, gcc1, msac; 719 720 size = 0; 721 722 switch (isc->chiptype) { 723 case CHIP_I810: 724 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 725 miscc = (u_int16_t)(reg >> 16); 726 if ((miscc & AGP_I810_MISCC_WINSIZE) == 727 AGP_I810_MISCC_WINSIZE_32) 728 size = 32 * 1024 * 1024; 729 else 730 size = 64 * 1024 * 1024; 731 break; 732 case CHIP_I830: 733 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 734 gcc1 = (u_int16_t)(reg >> 16); 735 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 736 size = 64 * 1024 * 1024; 737 else 738 size = 128 * 1024 * 1024; 739 break; 740 case CHIP_I855: 741 size = 128 * 1024 * 1024; 742 break; 743 case CHIP_I915: 744 case CHIP_G33: 745 case CHIP_G4X: 746 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I915_MSAC); 747 msac = (u_int16_t)(reg >> 16); 748 if (msac & AGP_I915_MSAC_APER_128M) 749 size = 128 * 1024 * 1024; 750 else 751 size = 256 * 1024 * 1024; 752 break; 753 case CHIP_I965: 754 size = 512 * 1024 * 1024; 755 break; 756 default: 757 aprint_error(": Unknown chipset\n"); 758 } 759 760 return size; 761 } 762 763 static int 764 agp_i810_set_aperture(struct agp_softc *sc, u_int32_t aperture) 765 { 766 struct agp_i810_softc *isc = sc->as_chipc; 767 pcireg_t reg; 768 u_int16_t miscc, gcc1; 769 770 switch (isc->chiptype) { 771 case CHIP_I810: 772 /* 773 * Double check for sanity. 774 */ 775 if (aperture != (32 * 1024 * 1024) && 776 aperture != (64 * 1024 * 1024)) { 777 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 778 aperture); 779 return EINVAL; 780 } 781 782 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 783 miscc = (u_int16_t)(reg >> 16); 784 miscc &= ~AGP_I810_MISCC_WINSIZE; 785 if (aperture == 32 * 1024 * 1024) 786 miscc |= AGP_I810_MISCC_WINSIZE_32; 787 else 788 miscc |= AGP_I810_MISCC_WINSIZE_64; 789 790 reg &= 0x0000ffff; 791 reg |= ((pcireg_t)miscc) << 16; 792 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I810_SMRAM, reg); 793 break; 794 case CHIP_I830: 795 if (aperture != (64 * 1024 * 1024) && 796 aperture != (128 * 1024 * 1024)) { 797 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 798 aperture); 799 return EINVAL; 800 } 801 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 802 gcc1 = (u_int16_t)(reg >> 16); 803 gcc1 &= ~AGP_I830_GCC1_GMASIZE; 804 if (aperture == 64 * 1024 * 1024) 805 gcc1 |= AGP_I830_GCC1_GMASIZE_64; 806 else 807 gcc1 |= AGP_I830_GCC1_GMASIZE_128; 808 809 reg &= 0x0000ffff; 810 reg |= ((pcireg_t)gcc1) << 16; 811 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I830_GCC0, reg); 812 break; 813 case CHIP_I855: 814 case CHIP_I915: 815 if (aperture != agp_i810_get_aperture(sc)) { 816 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 817 aperture); 818 return EINVAL; 819 } 820 break; 821 case CHIP_I965: 822 if (aperture != 512 * 1024 * 1024) { 823 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 824 aperture); 825 return EINVAL; 826 } 827 break; 828 } 829 830 return 0; 831 } 832 833 static int 834 agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 835 { 836 struct agp_i810_softc *isc = sc->as_chipc; 837 838 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) { 839 #ifdef AGP_DEBUG 840 printf("%s: failed: offset 0x%08x, shift %d, entries %d\n", 841 device_xname(sc->as_dev), (int)offset, AGP_PAGE_SHIFT, 842 isc->gatt->ag_entries); 843 #endif 844 return EINVAL; 845 } 846 847 if (isc->chiptype != CHIP_I810) { 848 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 849 #ifdef AGP_DEBUG 850 printf("%s: trying to bind into stolen memory\n", 851 device_xname(sc->as_dev)); 852 #endif 853 return EINVAL; 854 } 855 } 856 857 return agp_i810_write_gtt_entry(isc, offset, physical | 1); 858 } 859 860 static int 861 agp_i810_unbind_page(struct agp_softc *sc, off_t offset) 862 { 863 struct agp_i810_softc *isc = sc->as_chipc; 864 865 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 866 return EINVAL; 867 868 if (isc->chiptype != CHIP_I810 ) { 869 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 870 #ifdef AGP_DEBUG 871 printf("%s: trying to unbind from stolen memory\n", 872 device_xname(sc->as_dev)); 873 #endif 874 return EINVAL; 875 } 876 } 877 878 return agp_i810_write_gtt_entry(isc, offset, 0); 879 } 880 881 /* 882 * Writing via memory mapped registers already flushes all TLBs. 883 */ 884 static void 885 agp_i810_flush_tlb(struct agp_softc *sc) 886 { 887 } 888 889 static int 890 agp_i810_enable(struct agp_softc *sc, u_int32_t mode) 891 { 892 893 return 0; 894 } 895 896 static struct agp_memory * 897 agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size) 898 { 899 struct agp_i810_softc *isc = sc->as_chipc; 900 struct agp_memory *mem; 901 902 #ifdef AGP_DEBUG 903 printf("AGP: alloc(%d, 0x%x)\n", type, (int) size); 904 #endif 905 906 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 907 return 0; 908 909 if (sc->as_allocated + size > sc->as_maxmem) 910 return 0; 911 912 if (type == 1) { 913 /* 914 * Mapping local DRAM into GATT. 915 */ 916 if (isc->chiptype != CHIP_I810 ) 917 return 0; 918 if (size != isc->dcache_size) 919 return 0; 920 } else if (type == 2) { 921 /* 922 * Bogus mapping for the hardware cursor. 923 */ 924 if (size != AGP_PAGE_SIZE && size != 4 * AGP_PAGE_SIZE) 925 return 0; 926 } 927 928 mem = malloc(sizeof *mem, M_AGP, M_WAITOK|M_ZERO); 929 if (mem == NULL) 930 return NULL; 931 mem->am_id = sc->as_nextid++; 932 mem->am_size = size; 933 mem->am_type = type; 934 935 if (type == 2) { 936 /* 937 * Allocate and wire down the memory now so that we can 938 * get its physical address. 939 */ 940 mem->am_dmaseg = malloc(sizeof *mem->am_dmaseg, M_AGP, 941 M_WAITOK); 942 if (mem->am_dmaseg == NULL) { 943 free(mem, M_AGP); 944 return NULL; 945 } 946 if (agp_alloc_dmamem(sc->as_dmat, size, 0, 947 &mem->am_dmamap, &mem->am_virtual, &mem->am_physical, 948 mem->am_dmaseg, 1, &mem->am_nseg) != 0) { 949 free(mem->am_dmaseg, M_AGP); 950 free(mem, M_AGP); 951 return NULL; 952 } 953 memset(mem->am_virtual, 0, size); 954 } else if (type != 1) { 955 if (bus_dmamap_create(sc->as_dmat, size, size / PAGE_SIZE + 1, 956 size, 0, BUS_DMA_NOWAIT, 957 &mem->am_dmamap) != 0) { 958 free(mem, M_AGP); 959 return NULL; 960 } 961 } 962 963 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link); 964 sc->as_allocated += size; 965 966 return mem; 967 } 968 969 static int 970 agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem) 971 { 972 if (mem->am_is_bound) 973 return EBUSY; 974 975 if (mem->am_type == 2) { 976 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap, 977 mem->am_virtual, mem->am_dmaseg, mem->am_nseg); 978 free(mem->am_dmaseg, M_AGP); 979 } 980 981 sc->as_allocated -= mem->am_size; 982 TAILQ_REMOVE(&sc->as_memory, mem, am_link); 983 free(mem, M_AGP); 984 return 0; 985 } 986 987 static int 988 agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem, 989 off_t offset) 990 { 991 struct agp_i810_softc *isc = sc->as_chipc; 992 u_int32_t regval, i; 993 994 if (mem->am_is_bound != 0) 995 return EINVAL; 996 997 /* 998 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 999 * X server for mysterious reasons which leads to crashes if we write 1000 * to the GTT through the MMIO window. 1001 * Until the issue is solved, simply restore it. 1002 */ 1003 regval = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL); 1004 if (regval != (isc->gatt->ag_physical | 1)) { 1005 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%x - fixing\n", 1006 regval); 1007 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 1008 isc->gatt->ag_physical | 1); 1009 } 1010 1011 if (mem->am_type == 2) { 1012 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1013 agp_i810_bind_page(sc, offset + i, 1014 mem->am_physical + i); 1015 mem->am_offset = offset; 1016 mem->am_is_bound = 1; 1017 return 0; 1018 } 1019 1020 if (mem->am_type != 1) 1021 return agp_generic_bind_memory(sc, mem, offset); 1022 1023 if (isc->chiptype != CHIP_I810) 1024 return EINVAL; 1025 1026 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1027 agp_i810_write_gtt_entry(isc, i, i | 3); 1028 mem->am_is_bound = 1; 1029 return 0; 1030 } 1031 1032 static int 1033 agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem) 1034 { 1035 struct agp_i810_softc *isc = sc->as_chipc; 1036 u_int32_t i; 1037 1038 if (mem->am_is_bound == 0) 1039 return EINVAL; 1040 1041 if (mem->am_type == 2) { 1042 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1043 agp_i810_unbind_page(sc, mem->am_offset + i); 1044 mem->am_offset = 0; 1045 mem->am_is_bound = 0; 1046 return 0; 1047 } 1048 1049 if (mem->am_type != 1) 1050 return agp_generic_unbind_memory(sc, mem); 1051 1052 if (isc->chiptype != CHIP_I810) 1053 return EINVAL; 1054 1055 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1056 agp_i810_write_gtt_entry(isc, i, 0); 1057 mem->am_is_bound = 0; 1058 return 0; 1059 } 1060 1061 static bool 1062 agp_i810_resume(device_t dv, const pmf_qual_t *qual) 1063 { 1064 struct agp_softc *sc = device_private(dv); 1065 struct agp_i810_softc *isc = sc->as_chipc; 1066 1067 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 1068 agp_flush_cache(); 1069 1070 return true; 1071 } 1072
Indexes created Tue Oct 07 21:09:53 GMT 2025