agp_i810.c revision 1.75
1 /* $NetBSD: agp_i810.c,v 1.75 2014/05/23 22:58:56 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.75 2014/05/23 22:58:56 riastradh Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/proc.h> 40 #include <sys/device.h> 41 #include <sys/conf.h> 42 #include <sys/xcall.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcidevs.h> 47 #include <dev/pci/agpvar.h> 48 #include <dev/pci/agpreg.h> 49 #include <dev/pci/agp_i810var.h> 50 51 #include <sys/agpio.h> 52 53 #include <sys/bus.h> 54 55 #include "agp_intel.h" 56 57 struct agp_softc *agp_i810_sc = NULL; 58 59 #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off) 60 #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off) 61 #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v) 62 63 #define CHIP_I810 0 /* i810/i815 */ 64 #define CHIP_I830 1 /* 830M/845G */ 65 #define CHIP_I855 2 /* 852GM/855GM/865G */ 66 #define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */ 67 #define CHIP_I965 4 /* 965Q/965PM */ 68 #define CHIP_G33 5 /* G33/Q33/Q35 */ 69 #define CHIP_G4X 6 /* G45/Q45 */ 70 71 /* XXX hack, see below */ 72 static bus_addr_t agp_i810_vga_regbase; 73 static bus_space_handle_t agp_i810_vga_bsh; 74 75 static u_int32_t agp_i810_get_aperture(struct agp_softc *); 76 static int agp_i810_set_aperture(struct agp_softc *, u_int32_t); 77 static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t); 78 static int agp_i810_unbind_page(struct agp_softc *, off_t); 79 static void agp_i810_flush_tlb(struct agp_softc *); 80 static int agp_i810_enable(struct agp_softc *, u_int32_t mode); 81 static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int, 82 vsize_t); 83 static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *); 84 static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, off_t); 85 static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *); 86 87 static bool agp_i810_resume(device_t, const pmf_qual_t *); 88 static int agp_i810_init(struct agp_softc *); 89 90 static int agp_i810_setup_chipset_flush_page(struct agp_softc *); 91 static int agp_i810_init(struct agp_softc *); 92 93 static struct agp_methods agp_i810_methods = { 94 agp_i810_get_aperture, 95 agp_i810_set_aperture, 96 agp_i810_bind_page, 97 agp_i810_unbind_page, 98 agp_i810_flush_tlb, 99 agp_i810_enable, 100 agp_i810_alloc_memory, 101 agp_i810_free_memory, 102 agp_i810_bind_memory, 103 agp_i810_unbind_memory, 104 }; 105 106 int 107 agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, bus_addr_t v) 108 { 109 u_int32_t pte; 110 bus_size_t base_off, wroff; 111 112 /* Bits 11:4 (physical start address extension) should be zero. */ 113 if ((v & 0xff0) != 0) 114 return EINVAL; 115 116 pte = (u_int32_t)v; 117 /* 118 * We need to massage the pte if bus_addr_t is wider than 32 bits. 119 * The compiler isn't smart enough, hence the casts to uintmax_t. 120 */ 121 if (sizeof(bus_addr_t) > sizeof(u_int32_t)) { 122 /* 965+ can do 36-bit addressing, add in the extra bits. */ 123 if (isc->chiptype == CHIP_I965 || 124 isc->chiptype == CHIP_G33 || 125 isc->chiptype == CHIP_G4X) { 126 if (((uintmax_t)v >> 36) != 0) 127 return EINVAL; 128 pte |= (v >> 28) & 0xf0; 129 } else { 130 if (((uintmax_t)v >> 32) != 0) 131 return EINVAL; 132 } 133 } 134 135 base_off = 0; 136 wroff = (off >> AGP_PAGE_SHIFT) * 4; 137 138 switch (isc->chiptype) { 139 case CHIP_I810: 140 case CHIP_I830: 141 case CHIP_I855: 142 base_off = AGP_I810_GTT; 143 break; 144 case CHIP_I965: 145 base_off = AGP_I965_GTT; 146 break; 147 case CHIP_G4X: 148 base_off = AGP_G4X_GTT; 149 break; 150 case CHIP_I915: 151 case CHIP_G33: 152 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, wroff, pte); 153 return 0; 154 } 155 156 WRITE4(base_off + wroff, pte); 157 return 0; 158 } 159 160 void 161 agp_i810_post_gtt_entry(struct agp_i810_softc *isc, off_t off) 162 { 163 bus_size_t base_off, wroff; 164 165 base_off = 0; 166 wroff = (off >> AGP_PAGE_SHIFT) * 4; 167 168 switch (isc->chiptype) { 169 case CHIP_I810: 170 case CHIP_I830: 171 case CHIP_I855: 172 base_off = AGP_I810_GTT; 173 break; 174 case CHIP_I965: 175 base_off = AGP_I965_GTT; 176 break; 177 case CHIP_G4X: 178 base_off = AGP_G4X_GTT; 179 break; 180 case CHIP_I915: 181 case CHIP_G33: 182 (void)bus_space_read_4(isc->gtt_bst, isc->gtt_bsh, wroff); 183 return; 184 } 185 186 (void)READ4(base_off + wroff); 187 } 188 189 static void 190 agp_flush_cache_xc(void *a __unused, void *b __unused) 191 { 192 193 agp_flush_cache(); 194 } 195 196 void 197 agp_i810_chipset_flush(struct agp_i810_softc *isc) 198 { 199 unsigned int timo = 20000; /* * 50 us = 1 s */ 200 201 switch (isc->chiptype) { 202 case CHIP_I810: 203 break; 204 case CHIP_I830: 205 case CHIP_I855: 206 xc_wait(xc_broadcast(0, &agp_flush_cache_xc, NULL, NULL)); 207 WRITE4(AGP_I830_HIC, READ4(AGP_I830_HIC) | __BIT(31)); 208 while (ISSET(READ4(AGP_I830_HIC), __BIT(31))) { 209 if (timo-- == 0) 210 break; 211 DELAY(50); 212 } 213 break; 214 case CHIP_I915: 215 case CHIP_I965: 216 case CHIP_G33: 217 case CHIP_G4X: 218 bus_space_write_4(isc->flush_bst, isc->flush_bsh, 0, 1); 219 break; 220 } 221 } 222 223 /* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */ 224 static int 225 agp_i810_vgamatch(const struct pci_attach_args *pa) 226 { 227 228 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 229 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 230 return (0); 231 232 switch (PCI_PRODUCT(pa->pa_id)) { 233 case PCI_PRODUCT_INTEL_82810_GC: 234 case PCI_PRODUCT_INTEL_82810_DC100_GC: 235 case PCI_PRODUCT_INTEL_82810E_GC: 236 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 237 case PCI_PRODUCT_INTEL_82830MP_IV: 238 case PCI_PRODUCT_INTEL_82845G_IGD: 239 case PCI_PRODUCT_INTEL_82855GM_IGD: 240 case PCI_PRODUCT_INTEL_82865_IGD: 241 case PCI_PRODUCT_INTEL_82915G_IGD: 242 case PCI_PRODUCT_INTEL_82915GM_IGD: 243 case PCI_PRODUCT_INTEL_82945P_IGD: 244 case PCI_PRODUCT_INTEL_82945GM_IGD: 245 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 246 case PCI_PRODUCT_INTEL_82945GME_IGD: 247 case PCI_PRODUCT_INTEL_E7221_IGD: 248 case PCI_PRODUCT_INTEL_82965Q_IGD: 249 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 250 case PCI_PRODUCT_INTEL_82965PM_IGD: 251 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 252 case PCI_PRODUCT_INTEL_82G33_IGD: 253 case PCI_PRODUCT_INTEL_82G33_IGD_1: 254 case PCI_PRODUCT_INTEL_82965G_IGD: 255 case PCI_PRODUCT_INTEL_82965G_IGD_1: 256 case PCI_PRODUCT_INTEL_82965GME_IGD: 257 case PCI_PRODUCT_INTEL_82Q35_IGD: 258 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 259 case PCI_PRODUCT_INTEL_82Q33_IGD: 260 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 261 case PCI_PRODUCT_INTEL_82G35_IGD: 262 case PCI_PRODUCT_INTEL_82G35_IGD_1: 263 case PCI_PRODUCT_INTEL_82946GZ_IGD: 264 case PCI_PRODUCT_INTEL_82GM45_IGD: 265 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 266 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 267 case PCI_PRODUCT_INTEL_82Q45_IGD: 268 case PCI_PRODUCT_INTEL_82G45_IGD: 269 case PCI_PRODUCT_INTEL_82G41_IGD: 270 case PCI_PRODUCT_INTEL_82B43_IGD: 271 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 272 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 273 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 274 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 275 return (1); 276 } 277 278 return (0); 279 } 280 281 static int 282 agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg) 283 { 284 /* 285 * Find the aperture. Don't map it (yet), this would 286 * eat KVA. 287 */ 288 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 289 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize, 290 &sc->as_apflags) != 0) 291 return ENXIO; 292 293 sc->as_apt = pa->pa_memt; 294 295 return 0; 296 } 297 298 int 299 agp_i810_attach(device_t parent, device_t self, void *aux) 300 { 301 struct agp_softc *sc = device_private(self); 302 struct agp_i810_softc *isc; 303 struct agp_gatt *gatt; 304 int error, apbase; 305 bus_addr_t mmadr; 306 bus_size_t mmadrsize; 307 308 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 309 if (isc == NULL) { 310 aprint_error(": can't allocate chipset-specific softc\n"); 311 return ENOMEM; 312 } 313 sc->as_chipc = isc; 314 sc->as_methods = &agp_i810_methods; 315 316 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) { 317 #if NAGP_INTEL > 0 318 const struct pci_attach_args *pa = aux; 319 320 switch (PCI_PRODUCT(pa->pa_id)) { 321 case PCI_PRODUCT_INTEL_82840_HB: 322 case PCI_PRODUCT_INTEL_82865_HB: 323 case PCI_PRODUCT_INTEL_82845G_DRAM: 324 case PCI_PRODUCT_INTEL_82815_FULL_HUB: 325 case PCI_PRODUCT_INTEL_82855GM_MCH: 326 return agp_intel_attach(parent, self, aux); 327 } 328 #endif 329 aprint_error(": can't find internal VGA device config space\n"); 330 free(isc, M_AGP); 331 return ENOENT; 332 } 333 334 /* XXXfvdl */ 335 sc->as_dmat = isc->vga_pa.pa_dmat; 336 337 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 338 case PCI_PRODUCT_INTEL_82810_GC: 339 case PCI_PRODUCT_INTEL_82810_DC100_GC: 340 case PCI_PRODUCT_INTEL_82810E_GC: 341 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 342 isc->chiptype = CHIP_I810; 343 break; 344 case PCI_PRODUCT_INTEL_82830MP_IV: 345 case PCI_PRODUCT_INTEL_82845G_IGD: 346 isc->chiptype = CHIP_I830; 347 break; 348 case PCI_PRODUCT_INTEL_82855GM_IGD: 349 case PCI_PRODUCT_INTEL_82865_IGD: 350 isc->chiptype = CHIP_I855; 351 break; 352 case PCI_PRODUCT_INTEL_82915G_IGD: 353 case PCI_PRODUCT_INTEL_82915GM_IGD: 354 case PCI_PRODUCT_INTEL_82945P_IGD: 355 case PCI_PRODUCT_INTEL_82945GM_IGD: 356 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 357 case PCI_PRODUCT_INTEL_82945GME_IGD: 358 case PCI_PRODUCT_INTEL_E7221_IGD: 359 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 360 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 361 isc->chiptype = CHIP_I915; 362 break; 363 case PCI_PRODUCT_INTEL_82965Q_IGD: 364 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 365 case PCI_PRODUCT_INTEL_82965PM_IGD: 366 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 367 case PCI_PRODUCT_INTEL_82965G_IGD: 368 case PCI_PRODUCT_INTEL_82965G_IGD_1: 369 case PCI_PRODUCT_INTEL_82965GME_IGD: 370 case PCI_PRODUCT_INTEL_82946GZ_IGD: 371 case PCI_PRODUCT_INTEL_82G35_IGD: 372 case PCI_PRODUCT_INTEL_82G35_IGD_1: 373 isc->chiptype = CHIP_I965; 374 break; 375 case PCI_PRODUCT_INTEL_82Q35_IGD: 376 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 377 case PCI_PRODUCT_INTEL_82G33_IGD: 378 case PCI_PRODUCT_INTEL_82G33_IGD_1: 379 case PCI_PRODUCT_INTEL_82Q33_IGD: 380 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 381 isc->chiptype = CHIP_G33; 382 break; 383 case PCI_PRODUCT_INTEL_82GM45_IGD: 384 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 385 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 386 case PCI_PRODUCT_INTEL_82Q45_IGD: 387 case PCI_PRODUCT_INTEL_82G45_IGD: 388 case PCI_PRODUCT_INTEL_82G41_IGD: 389 case PCI_PRODUCT_INTEL_82B43_IGD: 390 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 391 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 392 isc->chiptype = CHIP_G4X; 393 break; 394 } 395 396 switch (isc->chiptype) { 397 case CHIP_I915: 398 case CHIP_G33: 399 apbase = AGP_I915_GMADR; 400 break; 401 case CHIP_I965: 402 case CHIP_G4X: 403 apbase = AGP_I965_GMADR; 404 break; 405 default: 406 apbase = AGP_I810_GMADR; 407 break; 408 } 409 410 if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) { 411 error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase); 412 } else { 413 error = agp_map_aperture(&isc->vga_pa, sc, apbase); 414 } 415 if (error != 0) { 416 aprint_error(": can't map aperture\n"); 417 free(isc, M_AGP); 418 return error; 419 } 420 421 if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33) { 422 error = pci_mapreg_map(&isc->vga_pa, AGP_I915_MMADR, 423 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 424 &mmadr, &mmadrsize); 425 if (error != 0) { 426 aprint_error(": can't map mmadr registers\n"); 427 agp_generic_detach(sc); 428 return error; 429 } 430 error = pci_mapreg_map(&isc->vga_pa, AGP_I915_GTTADR, 431 PCI_MAPREG_TYPE_MEM, 0, &isc->gtt_bst, &isc->gtt_bsh, 432 NULL, NULL); 433 if (error != 0) { 434 aprint_error(": can't map gttadr registers\n"); 435 /* XXX we should release mmadr here */ 436 agp_generic_detach(sc); 437 return error; 438 } 439 } else if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) { 440 error = pci_mapreg_map(&isc->vga_pa, AGP_I965_MMADR, 441 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 442 &mmadr, &mmadrsize); 443 if (error != 0) { 444 aprint_error(": can't map mmadr registers\n"); 445 agp_generic_detach(sc); 446 return error; 447 } 448 } else { 449 error = pci_mapreg_map(&isc->vga_pa, AGP_I810_MMADR, 450 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 451 &mmadr, &mmadrsize); 452 if (error != 0) { 453 aprint_error(": can't map mmadr registers\n"); 454 agp_generic_detach(sc); 455 return error; 456 } 457 } 458 459 isc->initial_aperture = AGP_GET_APERTURE(sc); 460 461 gatt = malloc(sizeof(struct agp_gatt), M_AGP, M_NOWAIT); 462 if (!gatt) { 463 agp_generic_detach(sc); 464 return ENOMEM; 465 } 466 isc->gatt = gatt; 467 468 gatt->ag_entries = AGP_GET_APERTURE(sc) >> AGP_PAGE_SHIFT; 469 470 if (!pmf_device_register(self, NULL, agp_i810_resume)) 471 aprint_error_dev(self, "couldn't establish power handler\n"); 472 473 /* 474 * XXX horrible hack to allow drm code to use our mapping 475 * of VGA chip registers 476 */ 477 agp_i810_vga_regbase = mmadr; 478 agp_i810_vga_bsh = isc->bsh; 479 480 /* Set up a chipset flush page if necessary. */ 481 switch (isc->chiptype) { 482 case CHIP_I915: 483 case CHIP_I965: 484 case CHIP_G33: 485 case CHIP_G4X: 486 error = agp_i810_setup_chipset_flush_page(sc); 487 if (error) { 488 aprint_error_dev(self, 489 "failed to set up chipset flush page: %d\n", 490 error); 491 agp_generic_detach(sc); 492 return error; 493 } 494 break; 495 } 496 497 return agp_i810_init(sc); 498 } 499 500 static int 501 agp_i810_setup_chipset_flush_page(struct agp_softc *sc) 502 { 503 struct agp_i810_softc *const isc = sc->as_chipc; 504 pcireg_t reg, lo, hi; 505 bus_addr_t addr, minaddr, maxaddr; 506 int error; 507 508 /* We always use memory-mapped I/O. */ 509 isc->flush_bst = isc->vga_pa.pa_memt; 510 511 /* No page allocated yet. */ 512 isc->flush_addr = 0; 513 514 /* Read the PCI config register: 4-byte on gen3, 8-byte on gen>=4. */ 515 if (isc->chiptype == CHIP_I915) { 516 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR); 517 addr = reg; 518 minaddr = PAGE_SIZE; /* XXX PCIBIOS_MIN_MEM? */ 519 maxaddr = UINT32_MAX; 520 } else { 521 hi = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I965_IFPADDR+4); 522 lo = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I965_IFPADDR); 523 addr = ((bus_addr_t)hi << 32) | lo; 524 minaddr = PAGE_SIZE; /* XXX PCIBIOS_MIN_MEM? */ 525 maxaddr = UINT64_MAX; 526 } 527 528 /* Allocate or map a pre-allocated a page for it. */ 529 if (ISSET(addr, 1)) { 530 /* BIOS allocated it for us. Use that. */ 531 error = bus_space_map(isc->flush_bst, addr & ~1, PAGE_SIZE, 0, 532 &isc->flush_bsh); 533 if (error) 534 return error; 535 } else { 536 /* None allocated. Allocate one. */ 537 error = bus_space_alloc(isc->flush_bst, minaddr, maxaddr, 538 PAGE_SIZE, PAGE_SIZE, 0, 0, 539 &isc->flush_addr, &isc->flush_bsh); 540 if (error) 541 return error; 542 KASSERT(isc->flush_addr != 0); 543 /* Write it into the PCI config register. */ 544 addr = isc->flush_addr | 1; 545 if (isc->chiptype == CHIP_I915) { 546 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR, 547 addr); 548 } else { 549 pci_conf_write(sc->as_pc, sc->as_tag, 550 AGP_I965_IFPADDR + 4, 551 __SHIFTOUT(addr, __BITS(63, 32))); 552 pci_conf_write(sc->as_pc, sc->as_tag, 553 AGP_I965_IFPADDR, 554 __SHIFTOUT(addr, __BITS(31, 0))); 555 } 556 } 557 558 /* Success! */ 559 return 0; 560 } 561 562 /* 563 * XXX horrible hack to allow drm code to use our mapping 564 * of VGA chip registers 565 */ 566 int 567 agp_i810_borrow(bus_addr_t base, bus_space_handle_t *hdlp) 568 { 569 570 if (!agp_i810_vga_regbase || base != agp_i810_vga_regbase) 571 return 0; 572 *hdlp = agp_i810_vga_bsh; 573 return 1; 574 } 575 576 static int agp_i810_init(struct agp_softc *sc) 577 { 578 struct agp_i810_softc *isc; 579 struct agp_gatt *gatt; 580 581 isc = sc->as_chipc; 582 gatt = isc->gatt; 583 584 if (isc->chiptype == CHIP_I810) { 585 void *virtual; 586 int dummyseg; 587 588 /* Some i810s have on-chip memory called dcache */ 589 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 590 isc->dcache_size = 4 * 1024 * 1024; 591 else 592 isc->dcache_size = 0; 593 594 /* According to the specs the gatt on the i810 must be 64k */ 595 if (agp_alloc_dmamem(sc->as_dmat, 64 * 1024, 596 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical, 597 &gatt->ag_dmaseg, 1, &dummyseg) != 0) { 598 free(gatt, M_AGP); 599 agp_generic_detach(sc); 600 return ENOMEM; 601 } 602 gatt->ag_virtual = (uint32_t *)virtual; 603 gatt->ag_size = gatt->ag_entries * sizeof(u_int32_t); 604 memset(gatt->ag_virtual, 0, gatt->ag_size); 605 606 agp_flush_cache(); 607 /* Install the GATT. */ 608 WRITE4(AGP_I810_PGTBL_CTL, gatt->ag_physical | 1); 609 } else if (isc->chiptype == CHIP_I830) { 610 /* The i830 automatically initializes the 128k gatt on boot. */ 611 pcireg_t reg; 612 u_int32_t pgtblctl; 613 u_int16_t gcc1; 614 615 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 616 gcc1 = (u_int16_t)(reg >> 16); 617 switch (gcc1 & AGP_I830_GCC1_GMS) { 618 case AGP_I830_GCC1_GMS_STOLEN_512: 619 isc->stolen = (512 - 132) * 1024 / 4096; 620 break; 621 case AGP_I830_GCC1_GMS_STOLEN_1024: 622 isc->stolen = (1024 - 132) * 1024 / 4096; 623 break; 624 case AGP_I830_GCC1_GMS_STOLEN_8192: 625 isc->stolen = (8192 - 132) * 1024 / 4096; 626 break; 627 default: 628 isc->stolen = 0; 629 aprint_error( 630 ": unknown memory configuration, disabling\n"); 631 agp_generic_detach(sc); 632 return EINVAL; 633 } 634 635 if (isc->stolen > 0) { 636 aprint_normal(": detected %dk stolen memory\n%s", 637 isc->stolen * 4, device_xname(sc->as_dev)); 638 } 639 640 /* GATT address is already in there, make sure it's enabled */ 641 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 642 pgtblctl |= 1; 643 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 644 645 gatt->ag_physical = pgtblctl & ~1; 646 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 647 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 || 648 isc->chiptype == CHIP_G4X) { 649 pcireg_t reg; 650 u_int32_t pgtblctl, gtt_size, stolen; 651 u_int16_t gcc1; 652 653 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1); 654 gcc1 = (u_int16_t)(reg >> 16); 655 656 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 657 658 /* Stolen memory is set up at the beginning of the aperture by 659 * the BIOS, consisting of the GATT followed by 4kb for the 660 * BIOS display. 661 */ 662 switch (isc->chiptype) { 663 case CHIP_I855: 664 gtt_size = 128; 665 break; 666 case CHIP_I915: 667 gtt_size = 256; 668 break; 669 case CHIP_I965: 670 switch (pgtblctl & AGP_I810_PGTBL_SIZE_MASK) { 671 case AGP_I810_PGTBL_SIZE_128KB: 672 case AGP_I810_PGTBL_SIZE_512KB: 673 gtt_size = 512; 674 break; 675 case AGP_I965_PGTBL_SIZE_1MB: 676 gtt_size = 1024; 677 break; 678 case AGP_I965_PGTBL_SIZE_2MB: 679 gtt_size = 2048; 680 break; 681 case AGP_I965_PGTBL_SIZE_1_5MB: 682 gtt_size = 1024 + 512; 683 break; 684 default: 685 aprint_error("Bad PGTBL size\n"); 686 agp_generic_detach(sc); 687 return EINVAL; 688 } 689 break; 690 case CHIP_G33: 691 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 692 case AGP_G33_PGTBL_SIZE_1M: 693 gtt_size = 1024; 694 break; 695 case AGP_G33_PGTBL_SIZE_2M: 696 gtt_size = 2048; 697 break; 698 default: 699 aprint_error(": Bad PGTBL size\n"); 700 agp_generic_detach(sc); 701 return EINVAL; 702 } 703 break; 704 case CHIP_G4X: 705 gtt_size = 0; 706 break; 707 default: 708 aprint_error(": bad chiptype\n"); 709 agp_generic_detach(sc); 710 return EINVAL; 711 } 712 713 switch (gcc1 & AGP_I855_GCC1_GMS) { 714 case AGP_I855_GCC1_GMS_STOLEN_1M: 715 stolen = 1024; 716 break; 717 case AGP_I855_GCC1_GMS_STOLEN_4M: 718 stolen = 4 * 1024; 719 break; 720 case AGP_I855_GCC1_GMS_STOLEN_8M: 721 stolen = 8 * 1024; 722 break; 723 case AGP_I855_GCC1_GMS_STOLEN_16M: 724 stolen = 16 * 1024; 725 break; 726 case AGP_I855_GCC1_GMS_STOLEN_32M: 727 stolen = 32 * 1024; 728 break; 729 case AGP_I915_GCC1_GMS_STOLEN_48M: 730 stolen = 48 * 1024; 731 break; 732 case AGP_I915_GCC1_GMS_STOLEN_64M: 733 stolen = 64 * 1024; 734 break; 735 case AGP_G33_GCC1_GMS_STOLEN_128M: 736 stolen = 128 * 1024; 737 break; 738 case AGP_G33_GCC1_GMS_STOLEN_256M: 739 stolen = 256 * 1024; 740 break; 741 case AGP_G4X_GCC1_GMS_STOLEN_96M: 742 stolen = 96 * 1024; 743 break; 744 case AGP_G4X_GCC1_GMS_STOLEN_160M: 745 stolen = 160 * 1024; 746 break; 747 case AGP_G4X_GCC1_GMS_STOLEN_224M: 748 stolen = 224 * 1024; 749 break; 750 case AGP_G4X_GCC1_GMS_STOLEN_352M: 751 stolen = 352 * 1024; 752 break; 753 default: 754 aprint_error( 755 ": unknown memory configuration, disabling\n"); 756 agp_generic_detach(sc); 757 return EINVAL; 758 } 759 760 switch (gcc1 & AGP_I855_GCC1_GMS) { 761 case AGP_I915_GCC1_GMS_STOLEN_48M: 762 case AGP_I915_GCC1_GMS_STOLEN_64M: 763 if (isc->chiptype != CHIP_I915 && 764 isc->chiptype != CHIP_I965 && 765 isc->chiptype != CHIP_G33 && 766 isc->chiptype != CHIP_G4X) 767 stolen = 0; 768 break; 769 case AGP_G33_GCC1_GMS_STOLEN_128M: 770 case AGP_G33_GCC1_GMS_STOLEN_256M: 771 if (isc->chiptype != CHIP_I965 && 772 isc->chiptype != CHIP_G33 && 773 isc->chiptype != CHIP_G4X) 774 stolen = 0; 775 break; 776 case AGP_G4X_GCC1_GMS_STOLEN_96M: 777 case AGP_G4X_GCC1_GMS_STOLEN_160M: 778 case AGP_G4X_GCC1_GMS_STOLEN_224M: 779 case AGP_G4X_GCC1_GMS_STOLEN_352M: 780 if (isc->chiptype != CHIP_I965 && 781 isc->chiptype != CHIP_G4X) 782 stolen = 0; 783 break; 784 } 785 786 /* BIOS space */ 787 gtt_size += 4; 788 789 isc->stolen = (stolen - gtt_size) * 1024 / 4096; 790 791 if (isc->stolen > 0) { 792 aprint_normal(": detected %dk stolen memory\n%s", 793 isc->stolen * 4, device_xname(sc->as_dev)); 794 } 795 796 /* GATT address is already in there, make sure it's enabled */ 797 pgtblctl |= 1; 798 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 799 800 gatt->ag_physical = pgtblctl & ~1; 801 } 802 803 /* 804 * Make sure the chipset can see everything. 805 */ 806 agp_flush_cache(); 807 808 /* 809 * Publish what we found for kludgey drivers (I'm looking at 810 * you, drm). 811 */ 812 if (agp_i810_sc == NULL) 813 agp_i810_sc = sc; 814 else 815 aprint_error_dev(sc->as_dev, "i810 agp already attached\n"); 816 817 return 0; 818 } 819 820 #if 0 821 static int 822 agp_i810_detach(struct agp_softc *sc) 823 { 824 int error; 825 struct agp_i810_softc *isc = sc->as_chipc; 826 827 error = agp_generic_detach(sc); 828 if (error) 829 return error; 830 831 switch (isc->chiptype) { 832 case CHIP_I915: 833 case CHIP_I965: 834 case CHIP_G33: 835 case CHIP_G4X: 836 if (isc->flush_addr) { 837 /* If we allocated a page, clear it. */ 838 if (isc->chiptype == CHIP_I915) { 839 pci_conf_write(sc->as_pc, sc->as_tag, 840 AGP_I915_IFPADDR, 0); 841 } else { 842 pci_conf_write(sc->as_pc, sc->as_tag, 843 AGP_I915_IFPADDR, 0); 844 pci_conf_write(sc->as_pc, sc->as_tag, 845 AGP_I915_IFPADDR + 4, 0); 846 } 847 isc->flush_addr = 0; 848 bus_space_free(isc->flush_bst, isc->flush_bsh, 849 PAGE_SIZE); 850 } else { 851 /* Otherwise, just unmap the pre-allocated page. */ 852 bus_space_unmap(isc->flush_bst, isc->flush_bsh, 853 PAGE_SIZE); 854 } 855 break; 856 } 857 858 /* Clear the GATT base. */ 859 if (sc->chiptype == CHIP_I810) { 860 WRITE4(AGP_I810_PGTBL_CTL, 0); 861 } else { 862 unsigned int pgtblctl; 863 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 864 pgtblctl &= ~1; 865 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 866 } 867 868 /* Put the aperture back the way it started. */ 869 AGP_SET_APERTURE(sc, isc->initial_aperture); 870 871 if (sc->chiptype == CHIP_I810) { 872 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap, 873 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 874 } 875 free(sc->gatt, M_AGP); 876 877 return 0; 878 } 879 #endif 880 881 static u_int32_t 882 agp_i810_get_aperture(struct agp_softc *sc) 883 { 884 struct agp_i810_softc *isc = sc->as_chipc; 885 pcireg_t reg; 886 u_int32_t size; 887 u_int16_t miscc, gcc1, msac; 888 889 size = 0; 890 891 switch (isc->chiptype) { 892 case CHIP_I810: 893 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 894 miscc = (u_int16_t)(reg >> 16); 895 if ((miscc & AGP_I810_MISCC_WINSIZE) == 896 AGP_I810_MISCC_WINSIZE_32) 897 size = 32 * 1024 * 1024; 898 else 899 size = 64 * 1024 * 1024; 900 break; 901 case CHIP_I830: 902 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 903 gcc1 = (u_int16_t)(reg >> 16); 904 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 905 size = 64 * 1024 * 1024; 906 else 907 size = 128 * 1024 * 1024; 908 break; 909 case CHIP_I855: 910 size = 128 * 1024 * 1024; 911 break; 912 case CHIP_I915: 913 case CHIP_G33: 914 case CHIP_G4X: 915 reg = pci_conf_read(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, 916 AGP_I915_MSAC); 917 msac = (u_int16_t)(reg >> 16); 918 if (msac & AGP_I915_MSAC_APER_128M) 919 size = 128 * 1024 * 1024; 920 else 921 size = 256 * 1024 * 1024; 922 break; 923 case CHIP_I965: 924 size = 512 * 1024 * 1024; 925 break; 926 default: 927 aprint_error(": Unknown chipset\n"); 928 } 929 930 return size; 931 } 932 933 static int 934 agp_i810_set_aperture(struct agp_softc *sc, u_int32_t aperture) 935 { 936 struct agp_i810_softc *isc = sc->as_chipc; 937 pcireg_t reg; 938 u_int16_t miscc, gcc1; 939 940 switch (isc->chiptype) { 941 case CHIP_I810: 942 /* 943 * Double check for sanity. 944 */ 945 if (aperture != (32 * 1024 * 1024) && 946 aperture != (64 * 1024 * 1024)) { 947 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 948 aperture); 949 return EINVAL; 950 } 951 952 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 953 miscc = (u_int16_t)(reg >> 16); 954 miscc &= ~AGP_I810_MISCC_WINSIZE; 955 if (aperture == 32 * 1024 * 1024) 956 miscc |= AGP_I810_MISCC_WINSIZE_32; 957 else 958 miscc |= AGP_I810_MISCC_WINSIZE_64; 959 960 reg &= 0x0000ffff; 961 reg |= ((pcireg_t)miscc) << 16; 962 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I810_SMRAM, reg); 963 break; 964 case CHIP_I830: 965 if (aperture != (64 * 1024 * 1024) && 966 aperture != (128 * 1024 * 1024)) { 967 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 968 aperture); 969 return EINVAL; 970 } 971 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 972 gcc1 = (u_int16_t)(reg >> 16); 973 gcc1 &= ~AGP_I830_GCC1_GMASIZE; 974 if (aperture == 64 * 1024 * 1024) 975 gcc1 |= AGP_I830_GCC1_GMASIZE_64; 976 else 977 gcc1 |= AGP_I830_GCC1_GMASIZE_128; 978 979 reg &= 0x0000ffff; 980 reg |= ((pcireg_t)gcc1) << 16; 981 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I830_GCC0, reg); 982 break; 983 case CHIP_I855: 984 case CHIP_I915: 985 if (aperture != agp_i810_get_aperture(sc)) { 986 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 987 aperture); 988 return EINVAL; 989 } 990 break; 991 case CHIP_I965: 992 if (aperture != 512 * 1024 * 1024) { 993 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 994 aperture); 995 return EINVAL; 996 } 997 break; 998 } 999 1000 return 0; 1001 } 1002 1003 static int 1004 agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 1005 { 1006 struct agp_i810_softc *isc = sc->as_chipc; 1007 1008 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) { 1009 #ifdef AGP_DEBUG 1010 printf("%s: failed: offset 0x%08x, shift %d, entries %d\n", 1011 device_xname(sc->as_dev), (int)offset, AGP_PAGE_SHIFT, 1012 isc->gatt->ag_entries); 1013 #endif 1014 return EINVAL; 1015 } 1016 1017 if (isc->chiptype != CHIP_I810) { 1018 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1019 #ifdef AGP_DEBUG 1020 printf("%s: trying to bind into stolen memory\n", 1021 device_xname(sc->as_dev)); 1022 #endif 1023 return EINVAL; 1024 } 1025 } 1026 1027 return agp_i810_write_gtt_entry(isc, offset, physical | 1); 1028 } 1029 1030 static int 1031 agp_i810_unbind_page(struct agp_softc *sc, off_t offset) 1032 { 1033 struct agp_i810_softc *isc = sc->as_chipc; 1034 1035 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 1036 return EINVAL; 1037 1038 if (isc->chiptype != CHIP_I810 ) { 1039 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1040 #ifdef AGP_DEBUG 1041 printf("%s: trying to unbind from stolen memory\n", 1042 device_xname(sc->as_dev)); 1043 #endif 1044 return EINVAL; 1045 } 1046 } 1047 1048 return agp_i810_write_gtt_entry(isc, offset, 0); 1049 } 1050 1051 /* 1052 * Writing via memory mapped registers already flushes all TLBs. 1053 */ 1054 static void 1055 agp_i810_flush_tlb(struct agp_softc *sc) 1056 { 1057 } 1058 1059 static int 1060 agp_i810_enable(struct agp_softc *sc, u_int32_t mode) 1061 { 1062 1063 return 0; 1064 } 1065 1066 static struct agp_memory * 1067 agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size) 1068 { 1069 struct agp_i810_softc *isc = sc->as_chipc; 1070 struct agp_memory *mem; 1071 1072 #ifdef AGP_DEBUG 1073 printf("AGP: alloc(%d, 0x%x)\n", type, (int) size); 1074 #endif 1075 1076 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 1077 return 0; 1078 1079 if (sc->as_allocated + size > sc->as_maxmem) 1080 return 0; 1081 1082 if (type == 1) { 1083 /* 1084 * Mapping local DRAM into GATT. 1085 */ 1086 if (isc->chiptype != CHIP_I810 ) 1087 return 0; 1088 if (size != isc->dcache_size) 1089 return 0; 1090 } else if (type == 2) { 1091 /* 1092 * Bogus mapping for the hardware cursor. 1093 */ 1094 if (size != AGP_PAGE_SIZE && size != 4 * AGP_PAGE_SIZE) 1095 return 0; 1096 } 1097 1098 mem = malloc(sizeof *mem, M_AGP, M_WAITOK|M_ZERO); 1099 if (mem == NULL) 1100 return NULL; 1101 mem->am_id = sc->as_nextid++; 1102 mem->am_size = size; 1103 mem->am_type = type; 1104 1105 if (type == 2) { 1106 /* 1107 * Allocate and wire down the memory now so that we can 1108 * get its physical address. 1109 */ 1110 mem->am_dmaseg = malloc(sizeof *mem->am_dmaseg, M_AGP, 1111 M_WAITOK); 1112 if (mem->am_dmaseg == NULL) { 1113 free(mem, M_AGP); 1114 return NULL; 1115 } 1116 if (agp_alloc_dmamem(sc->as_dmat, size, 0, 1117 &mem->am_dmamap, &mem->am_virtual, &mem->am_physical, 1118 mem->am_dmaseg, 1, &mem->am_nseg) != 0) { 1119 free(mem->am_dmaseg, M_AGP); 1120 free(mem, M_AGP); 1121 return NULL; 1122 } 1123 memset(mem->am_virtual, 0, size); 1124 } else if (type != 1) { 1125 if (bus_dmamap_create(sc->as_dmat, size, size / PAGE_SIZE + 1, 1126 size, 0, BUS_DMA_NOWAIT, 1127 &mem->am_dmamap) != 0) { 1128 free(mem, M_AGP); 1129 return NULL; 1130 } 1131 } 1132 1133 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link); 1134 sc->as_allocated += size; 1135 1136 return mem; 1137 } 1138 1139 static int 1140 agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem) 1141 { 1142 if (mem->am_is_bound) 1143 return EBUSY; 1144 1145 if (mem->am_type == 2) { 1146 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap, 1147 mem->am_virtual, mem->am_dmaseg, mem->am_nseg); 1148 free(mem->am_dmaseg, M_AGP); 1149 } 1150 1151 sc->as_allocated -= mem->am_size; 1152 TAILQ_REMOVE(&sc->as_memory, mem, am_link); 1153 free(mem, M_AGP); 1154 return 0; 1155 } 1156 1157 static int 1158 agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem, 1159 off_t offset) 1160 { 1161 struct agp_i810_softc *isc = sc->as_chipc; 1162 u_int32_t regval, i; 1163 1164 if (mem->am_is_bound != 0) 1165 return EINVAL; 1166 1167 /* 1168 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 1169 * X server for mysterious reasons which leads to crashes if we write 1170 * to the GTT through the MMIO window. 1171 * Until the issue is solved, simply restore it. 1172 */ 1173 regval = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL); 1174 if (regval != (isc->gatt->ag_physical | 1)) { 1175 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%x - fixing\n", 1176 regval); 1177 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 1178 isc->gatt->ag_physical | 1); 1179 } 1180 1181 if (mem->am_type == 2) { 1182 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1183 agp_i810_bind_page(sc, offset + i, 1184 mem->am_physical + i); 1185 mem->am_offset = offset; 1186 mem->am_is_bound = 1; 1187 return 0; 1188 } 1189 1190 if (mem->am_type != 1) 1191 return agp_generic_bind_memory(sc, mem, offset); 1192 1193 if (isc->chiptype != CHIP_I810) 1194 return EINVAL; 1195 1196 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1197 agp_i810_write_gtt_entry(isc, i, i | 3); 1198 mem->am_is_bound = 1; 1199 return 0; 1200 } 1201 1202 static int 1203 agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem) 1204 { 1205 struct agp_i810_softc *isc = sc->as_chipc; 1206 u_int32_t i; 1207 1208 if (mem->am_is_bound == 0) 1209 return EINVAL; 1210 1211 if (mem->am_type == 2) { 1212 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1213 agp_i810_unbind_page(sc, mem->am_offset + i); 1214 mem->am_offset = 0; 1215 mem->am_is_bound = 0; 1216 return 0; 1217 } 1218 1219 if (mem->am_type != 1) 1220 return agp_generic_unbind_memory(sc, mem); 1221 1222 if (isc->chiptype != CHIP_I810) 1223 return EINVAL; 1224 1225 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1226 agp_i810_write_gtt_entry(isc, i, 0); 1227 mem->am_is_bound = 0; 1228 return 0; 1229 } 1230 1231 static bool 1232 agp_i810_resume(device_t dv, const pmf_qual_t *qual) 1233 { 1234 struct agp_softc *sc = device_private(dv); 1235 struct agp_i810_softc *isc = sc->as_chipc; 1236 1237 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 1238 agp_flush_cache(); 1239 1240 return true; 1241 } 1242
Indexes created Tue Sep 23 22:09:46 GMT 2025