agp_i810.c revision 1.78
1 /* $NetBSD: agp_i810.c,v 1.78 2014/05/26 19:15:39 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.78 2014/05/26 19:15:39 riastradh Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/proc.h> 40 #include <sys/device.h> 41 #include <sys/conf.h> 42 #include <sys/xcall.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcidevs.h> 47 #include <dev/pci/agpvar.h> 48 #include <dev/pci/agpreg.h> 49 #include <dev/pci/agp_i810var.h> 50 51 #include <sys/agpio.h> 52 53 #include <sys/bus.h> 54 55 #include "agp_intel.h" 56 57 struct agp_softc *agp_i810_sc = NULL; 58 59 #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off) 60 #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off) 61 #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v) 62 63 #define CHIP_I810 0 /* i810/i815 */ 64 #define CHIP_I830 1 /* 830M/845G */ 65 #define CHIP_I855 2 /* 852GM/855GM/865G */ 66 #define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */ 67 #define CHIP_I965 4 /* 965Q/965PM */ 68 #define CHIP_G33 5 /* G33/Q33/Q35 */ 69 #define CHIP_G4X 6 /* G45/Q45 */ 70 71 /* XXX hack, see below */ 72 static bus_addr_t agp_i810_vga_regbase; 73 static bus_space_handle_t agp_i810_vga_bsh; 74 75 static u_int32_t agp_i810_get_aperture(struct agp_softc *); 76 static int agp_i810_set_aperture(struct agp_softc *, u_int32_t); 77 static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t); 78 static int agp_i810_unbind_page(struct agp_softc *, off_t); 79 static void agp_i810_flush_tlb(struct agp_softc *); 80 static int agp_i810_enable(struct agp_softc *, u_int32_t mode); 81 static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int, 82 vsize_t); 83 static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *); 84 static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, off_t); 85 static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *); 86 87 static bool agp_i810_resume(device_t, const pmf_qual_t *); 88 static int agp_i810_init(struct agp_softc *); 89 90 static int agp_i810_setup_chipset_flush_page(struct agp_softc *); 91 static int agp_i810_init(struct agp_softc *); 92 93 static struct agp_methods agp_i810_methods = { 94 agp_i810_get_aperture, 95 agp_i810_set_aperture, 96 agp_i810_bind_page, 97 agp_i810_unbind_page, 98 agp_i810_flush_tlb, 99 agp_i810_enable, 100 agp_i810_alloc_memory, 101 agp_i810_free_memory, 102 agp_i810_bind_memory, 103 agp_i810_unbind_memory, 104 }; 105 106 int 107 agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, bus_addr_t v) 108 { 109 u_int32_t pte; 110 bus_size_t base_off, wroff; 111 112 /* Bits 11:4 (physical start address extension) should be zero. */ 113 if ((v & 0xff0) != 0) 114 return EINVAL; 115 116 pte = (u_int32_t)v; 117 /* 118 * We need to massage the pte if bus_addr_t is wider than 32 bits. 119 * The compiler isn't smart enough, hence the casts to uintmax_t. 120 */ 121 if (sizeof(bus_addr_t) > sizeof(u_int32_t)) { 122 /* 965+ can do 36-bit addressing, add in the extra bits. */ 123 if (isc->chiptype == CHIP_I965 || 124 isc->chiptype == CHIP_G33 || 125 isc->chiptype == CHIP_G4X) { 126 if (((uintmax_t)v >> 36) != 0) 127 return EINVAL; 128 pte |= (v >> 28) & 0xf0; 129 } else { 130 if (((uintmax_t)v >> 32) != 0) 131 return EINVAL; 132 } 133 } 134 135 base_off = 0; 136 wroff = (off >> AGP_PAGE_SHIFT) * 4; 137 138 switch (isc->chiptype) { 139 case CHIP_I810: 140 case CHIP_I830: 141 case CHIP_I855: 142 base_off = AGP_I810_GTT; 143 break; 144 case CHIP_I965: 145 base_off = AGP_I965_GTT; 146 break; 147 case CHIP_G4X: 148 base_off = AGP_G4X_GTT; 149 break; 150 case CHIP_I915: 151 case CHIP_G33: 152 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, wroff, pte); 153 return 0; 154 } 155 156 WRITE4(base_off + wroff, pte); 157 return 0; 158 } 159 160 void 161 agp_i810_post_gtt_entry(struct agp_i810_softc *isc, off_t off) 162 { 163 bus_size_t base_off, wroff; 164 165 base_off = 0; 166 wroff = (off >> AGP_PAGE_SHIFT) * 4; 167 168 switch (isc->chiptype) { 169 case CHIP_I810: 170 case CHIP_I830: 171 case CHIP_I855: 172 base_off = AGP_I810_GTT; 173 break; 174 case CHIP_I965: 175 base_off = AGP_I965_GTT; 176 break; 177 case CHIP_G4X: 178 base_off = AGP_G4X_GTT; 179 break; 180 case CHIP_I915: 181 case CHIP_G33: 182 (void)bus_space_read_4(isc->gtt_bst, isc->gtt_bsh, wroff); 183 return; 184 } 185 186 (void)READ4(base_off + wroff); 187 } 188 189 static void 190 agp_flush_cache_xc(void *a __unused, void *b __unused) 191 { 192 193 agp_flush_cache(); 194 } 195 196 void 197 agp_i810_chipset_flush(struct agp_i810_softc *isc) 198 { 199 unsigned int timo = 20000; /* * 50 us = 1 s */ 200 201 switch (isc->chiptype) { 202 case CHIP_I810: 203 break; 204 case CHIP_I830: 205 case CHIP_I855: 206 /* 207 * Flush all CPU caches. If we're cold, we can't run 208 * xcalls, but there should be only one CPU up, so 209 * flushing only the local CPU's cache should suffice. 210 * 211 * XXX Come to think of it, do these chipsets appear in 212 * any multi-CPU systems? 213 */ 214 if (cold) 215 agp_flush_cache(); 216 else 217 xc_wait(xc_broadcast(0, &agp_flush_cache_xc, 218 NULL, NULL)); 219 WRITE4(AGP_I830_HIC, READ4(AGP_I830_HIC) | __BIT(31)); 220 while (ISSET(READ4(AGP_I830_HIC), __BIT(31))) { 221 if (timo-- == 0) 222 break; 223 DELAY(50); 224 } 225 break; 226 case CHIP_I915: 227 case CHIP_I965: 228 case CHIP_G33: 229 case CHIP_G4X: 230 bus_space_write_4(isc->flush_bst, isc->flush_bsh, 0, 1); 231 break; 232 } 233 } 234 235 /* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */ 236 static int 237 agp_i810_vgamatch(const struct pci_attach_args *pa) 238 { 239 240 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 241 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 242 return (0); 243 244 switch (PCI_PRODUCT(pa->pa_id)) { 245 case PCI_PRODUCT_INTEL_82810_GC: 246 case PCI_PRODUCT_INTEL_82810_DC100_GC: 247 case PCI_PRODUCT_INTEL_82810E_GC: 248 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 249 case PCI_PRODUCT_INTEL_82830MP_IV: 250 case PCI_PRODUCT_INTEL_82845G_IGD: 251 case PCI_PRODUCT_INTEL_82855GM_IGD: 252 case PCI_PRODUCT_INTEL_82865_IGD: 253 case PCI_PRODUCT_INTEL_82915G_IGD: 254 case PCI_PRODUCT_INTEL_82915GM_IGD: 255 case PCI_PRODUCT_INTEL_82945P_IGD: 256 case PCI_PRODUCT_INTEL_82945GM_IGD: 257 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 258 case PCI_PRODUCT_INTEL_82945GME_IGD: 259 case PCI_PRODUCT_INTEL_E7221_IGD: 260 case PCI_PRODUCT_INTEL_82965Q_IGD: 261 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 262 case PCI_PRODUCT_INTEL_82965PM_IGD: 263 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 264 case PCI_PRODUCT_INTEL_82G33_IGD: 265 case PCI_PRODUCT_INTEL_82G33_IGD_1: 266 case PCI_PRODUCT_INTEL_82965G_IGD: 267 case PCI_PRODUCT_INTEL_82965G_IGD_1: 268 case PCI_PRODUCT_INTEL_82965GME_IGD: 269 case PCI_PRODUCT_INTEL_82Q35_IGD: 270 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 271 case PCI_PRODUCT_INTEL_82Q33_IGD: 272 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 273 case PCI_PRODUCT_INTEL_82G35_IGD: 274 case PCI_PRODUCT_INTEL_82G35_IGD_1: 275 case PCI_PRODUCT_INTEL_82946GZ_IGD: 276 case PCI_PRODUCT_INTEL_82GM45_IGD: 277 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 278 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 279 case PCI_PRODUCT_INTEL_82Q45_IGD: 280 case PCI_PRODUCT_INTEL_82G45_IGD: 281 case PCI_PRODUCT_INTEL_82G41_IGD: 282 case PCI_PRODUCT_INTEL_82B43_IGD: 283 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 284 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 285 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 286 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 287 return (1); 288 } 289 290 return (0); 291 } 292 293 static int 294 agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg) 295 { 296 /* 297 * Find the aperture. Don't map it (yet), this would 298 * eat KVA. 299 */ 300 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 301 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize, 302 &sc->as_apflags) != 0) 303 return ENXIO; 304 305 sc->as_apt = pa->pa_memt; 306 307 return 0; 308 } 309 310 int 311 agp_i810_attach(device_t parent, device_t self, void *aux) 312 { 313 struct agp_softc *sc = device_private(self); 314 struct agp_i810_softc *isc; 315 struct agp_gatt *gatt; 316 int error, apbase; 317 bus_addr_t mmadr; 318 bus_size_t mmadrsize; 319 320 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 321 if (isc == NULL) { 322 aprint_error(": can't allocate chipset-specific softc\n"); 323 return ENOMEM; 324 } 325 sc->as_chipc = isc; 326 sc->as_methods = &agp_i810_methods; 327 328 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) { 329 #if NAGP_INTEL > 0 330 const struct pci_attach_args *pa = aux; 331 332 switch (PCI_PRODUCT(pa->pa_id)) { 333 case PCI_PRODUCT_INTEL_82840_HB: 334 case PCI_PRODUCT_INTEL_82865_HB: 335 case PCI_PRODUCT_INTEL_82845G_DRAM: 336 case PCI_PRODUCT_INTEL_82815_FULL_HUB: 337 case PCI_PRODUCT_INTEL_82855GM_MCH: 338 return agp_intel_attach(parent, self, aux); 339 } 340 #endif 341 aprint_error(": can't find internal VGA device config space\n"); 342 free(isc, M_AGP); 343 return ENOENT; 344 } 345 346 /* XXXfvdl */ 347 sc->as_dmat = isc->vga_pa.pa_dmat; 348 349 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 350 case PCI_PRODUCT_INTEL_82810_GC: 351 case PCI_PRODUCT_INTEL_82810_DC100_GC: 352 case PCI_PRODUCT_INTEL_82810E_GC: 353 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 354 isc->chiptype = CHIP_I810; 355 break; 356 case PCI_PRODUCT_INTEL_82830MP_IV: 357 case PCI_PRODUCT_INTEL_82845G_IGD: 358 isc->chiptype = CHIP_I830; 359 break; 360 case PCI_PRODUCT_INTEL_82855GM_IGD: 361 case PCI_PRODUCT_INTEL_82865_IGD: 362 isc->chiptype = CHIP_I855; 363 break; 364 case PCI_PRODUCT_INTEL_82915G_IGD: 365 case PCI_PRODUCT_INTEL_82915GM_IGD: 366 case PCI_PRODUCT_INTEL_82945P_IGD: 367 case PCI_PRODUCT_INTEL_82945GM_IGD: 368 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 369 case PCI_PRODUCT_INTEL_82945GME_IGD: 370 case PCI_PRODUCT_INTEL_E7221_IGD: 371 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 372 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 373 isc->chiptype = CHIP_I915; 374 break; 375 case PCI_PRODUCT_INTEL_82965Q_IGD: 376 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 377 case PCI_PRODUCT_INTEL_82965PM_IGD: 378 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 379 case PCI_PRODUCT_INTEL_82965G_IGD: 380 case PCI_PRODUCT_INTEL_82965G_IGD_1: 381 case PCI_PRODUCT_INTEL_82965GME_IGD: 382 case PCI_PRODUCT_INTEL_82946GZ_IGD: 383 case PCI_PRODUCT_INTEL_82G35_IGD: 384 case PCI_PRODUCT_INTEL_82G35_IGD_1: 385 isc->chiptype = CHIP_I965; 386 break; 387 case PCI_PRODUCT_INTEL_82Q35_IGD: 388 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 389 case PCI_PRODUCT_INTEL_82G33_IGD: 390 case PCI_PRODUCT_INTEL_82G33_IGD_1: 391 case PCI_PRODUCT_INTEL_82Q33_IGD: 392 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 393 isc->chiptype = CHIP_G33; 394 break; 395 case PCI_PRODUCT_INTEL_82GM45_IGD: 396 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 397 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 398 case PCI_PRODUCT_INTEL_82Q45_IGD: 399 case PCI_PRODUCT_INTEL_82G45_IGD: 400 case PCI_PRODUCT_INTEL_82G41_IGD: 401 case PCI_PRODUCT_INTEL_82B43_IGD: 402 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 403 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 404 isc->chiptype = CHIP_G4X; 405 break; 406 } 407 408 switch (isc->chiptype) { 409 case CHIP_I915: 410 case CHIP_G33: 411 apbase = AGP_I915_GMADR; 412 break; 413 case CHIP_I965: 414 case CHIP_G4X: 415 apbase = AGP_I965_GMADR; 416 break; 417 default: 418 apbase = AGP_I810_GMADR; 419 break; 420 } 421 422 if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) { 423 error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase); 424 } else { 425 error = agp_map_aperture(&isc->vga_pa, sc, apbase); 426 } 427 if (error != 0) { 428 aprint_error(": can't map aperture\n"); 429 free(isc, M_AGP); 430 return error; 431 } 432 433 if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33) { 434 error = pci_mapreg_map(&isc->vga_pa, AGP_I915_MMADR, 435 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 436 &mmadr, &mmadrsize); 437 if (error != 0) { 438 aprint_error(": can't map mmadr registers\n"); 439 agp_generic_detach(sc); 440 return error; 441 } 442 error = pci_mapreg_map(&isc->vga_pa, AGP_I915_GTTADR, 443 PCI_MAPREG_TYPE_MEM, 0, &isc->gtt_bst, &isc->gtt_bsh, 444 NULL, NULL); 445 if (error != 0) { 446 aprint_error(": can't map gttadr registers\n"); 447 /* XXX we should release mmadr here */ 448 agp_generic_detach(sc); 449 return error; 450 } 451 } else if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) { 452 error = pci_mapreg_map(&isc->vga_pa, AGP_I965_MMADR, 453 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 454 &mmadr, &mmadrsize); 455 if (error != 0) { 456 aprint_error(": can't map mmadr registers\n"); 457 agp_generic_detach(sc); 458 return error; 459 } 460 } else { 461 error = pci_mapreg_map(&isc->vga_pa, AGP_I810_MMADR, 462 PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh, 463 &mmadr, &mmadrsize); 464 if (error != 0) { 465 aprint_error(": can't map mmadr registers\n"); 466 agp_generic_detach(sc); 467 return error; 468 } 469 } 470 471 isc->initial_aperture = AGP_GET_APERTURE(sc); 472 473 gatt = malloc(sizeof(struct agp_gatt), M_AGP, M_NOWAIT); 474 if (!gatt) { 475 agp_generic_detach(sc); 476 return ENOMEM; 477 } 478 isc->gatt = gatt; 479 480 gatt->ag_entries = AGP_GET_APERTURE(sc) >> AGP_PAGE_SHIFT; 481 482 if (!pmf_device_register(self, NULL, agp_i810_resume)) 483 aprint_error_dev(self, "couldn't establish power handler\n"); 484 485 /* 486 * XXX horrible hack to allow drm code to use our mapping 487 * of VGA chip registers 488 */ 489 agp_i810_vga_regbase = mmadr; 490 agp_i810_vga_bsh = isc->bsh; 491 492 /* Set up a chipset flush page if necessary. */ 493 switch (isc->chiptype) { 494 case CHIP_I915: 495 case CHIP_I965: 496 case CHIP_G33: 497 case CHIP_G4X: 498 error = agp_i810_setup_chipset_flush_page(sc); 499 if (error) { 500 aprint_error_dev(self, 501 "failed to set up chipset flush page: %d\n", 502 error); 503 agp_generic_detach(sc); 504 return error; 505 } 506 break; 507 } 508 509 return agp_i810_init(sc); 510 } 511 512 static int 513 agp_i810_setup_chipset_flush_page(struct agp_softc *sc) 514 { 515 struct agp_i810_softc *const isc = sc->as_chipc; 516 pcireg_t reg, lo, hi; 517 bus_addr_t addr, minaddr, maxaddr; 518 int error; 519 520 /* We always use memory-mapped I/O. */ 521 isc->flush_bst = isc->vga_pa.pa_memt; 522 523 /* No page allocated yet. */ 524 isc->flush_addr = 0; 525 526 /* Read the PCI config register: 4-byte on gen3, 8-byte on gen>=4. */ 527 if (isc->chiptype == CHIP_I915) { 528 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR); 529 addr = reg; 530 minaddr = PAGE_SIZE; /* XXX PCIBIOS_MIN_MEM? */ 531 maxaddr = UINT32_MAX; 532 } else { 533 hi = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I965_IFPADDR+4); 534 lo = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I965_IFPADDR); 535 /* 536 * Convert to uint64_t, rather than bus_addr_t which 537 * may be 32-bit, to avoid undefined behaviour with a 538 * too-wide shift. Since the BIOS doesn't know whether 539 * the OS will run 64-bit or with PAE, it ought to 540 * configure at most a 32-bit physical address, so 541 * let's print a warning in case that happens. 542 */ 543 addr = ((uint64_t)hi << 32) | lo; 544 if (hi) { 545 aprint_error_dev(sc->as_dev, 546 "BIOS configured >32-bit flush page address" 547 ": %"PRIx64"\n", ((uint64_t)hi << 32) | lo); 548 #if __i386__ && !PAE 549 return EIO; 550 #endif 551 } 552 minaddr = PAGE_SIZE; /* XXX PCIBIOS_MIN_MEM? */ 553 maxaddr = MIN(UINT64_MAX, ~(bus_addr_t)0); 554 } 555 556 /* Allocate or map a pre-allocated a page for it. */ 557 if (ISSET(addr, 1)) { 558 /* BIOS allocated it for us. Use that. */ 559 error = bus_space_map(isc->flush_bst, addr & ~1, PAGE_SIZE, 0, 560 &isc->flush_bsh); 561 if (error) 562 return error; 563 } else { 564 /* None allocated. Allocate one. */ 565 error = bus_space_alloc(isc->flush_bst, minaddr, maxaddr, 566 PAGE_SIZE, PAGE_SIZE, 0, 0, 567 &isc->flush_addr, &isc->flush_bsh); 568 if (error) 569 return error; 570 KASSERT(isc->flush_addr != 0); 571 /* Write it into the PCI config register. */ 572 addr = isc->flush_addr | 1; 573 if (isc->chiptype == CHIP_I915) { 574 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR, 575 addr); 576 } else { 577 pci_conf_write(sc->as_pc, sc->as_tag, 578 AGP_I965_IFPADDR + 4, 579 __SHIFTOUT(addr, __BITS(63, 32))); 580 pci_conf_write(sc->as_pc, sc->as_tag, 581 AGP_I965_IFPADDR, 582 __SHIFTOUT(addr, __BITS(31, 0))); 583 } 584 } 585 586 /* Success! */ 587 return 0; 588 } 589 590 /* 591 * XXX horrible hack to allow drm code to use our mapping 592 * of VGA chip registers 593 */ 594 int 595 agp_i810_borrow(bus_addr_t base, bus_space_handle_t *hdlp) 596 { 597 598 if (!agp_i810_vga_regbase || base != agp_i810_vga_regbase) 599 return 0; 600 *hdlp = agp_i810_vga_bsh; 601 return 1; 602 } 603 604 static int agp_i810_init(struct agp_softc *sc) 605 { 606 struct agp_i810_softc *isc; 607 struct agp_gatt *gatt; 608 609 isc = sc->as_chipc; 610 gatt = isc->gatt; 611 612 if (isc->chiptype == CHIP_I810) { 613 void *virtual; 614 int dummyseg; 615 616 /* Some i810s have on-chip memory called dcache */ 617 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 618 isc->dcache_size = 4 * 1024 * 1024; 619 else 620 isc->dcache_size = 0; 621 622 /* According to the specs the gatt on the i810 must be 64k */ 623 if (agp_alloc_dmamem(sc->as_dmat, 64 * 1024, 624 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical, 625 &gatt->ag_dmaseg, 1, &dummyseg) != 0) { 626 free(gatt, M_AGP); 627 agp_generic_detach(sc); 628 return ENOMEM; 629 } 630 gatt->ag_virtual = (uint32_t *)virtual; 631 gatt->ag_size = gatt->ag_entries * sizeof(u_int32_t); 632 memset(gatt->ag_virtual, 0, gatt->ag_size); 633 634 agp_flush_cache(); 635 /* Install the GATT. */ 636 WRITE4(AGP_I810_PGTBL_CTL, gatt->ag_physical | 1); 637 } else if (isc->chiptype == CHIP_I830) { 638 /* The i830 automatically initializes the 128k gatt on boot. */ 639 pcireg_t reg; 640 u_int32_t pgtblctl; 641 u_int16_t gcc1; 642 643 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 644 gcc1 = (u_int16_t)(reg >> 16); 645 switch (gcc1 & AGP_I830_GCC1_GMS) { 646 case AGP_I830_GCC1_GMS_STOLEN_512: 647 isc->stolen = (512 - 132) * 1024 / 4096; 648 break; 649 case AGP_I830_GCC1_GMS_STOLEN_1024: 650 isc->stolen = (1024 - 132) * 1024 / 4096; 651 break; 652 case AGP_I830_GCC1_GMS_STOLEN_8192: 653 isc->stolen = (8192 - 132) * 1024 / 4096; 654 break; 655 default: 656 isc->stolen = 0; 657 aprint_error( 658 ": unknown memory configuration, disabling\n"); 659 agp_generic_detach(sc); 660 return EINVAL; 661 } 662 663 if (isc->stolen > 0) { 664 aprint_normal(": detected %dk stolen memory\n%s", 665 isc->stolen * 4, device_xname(sc->as_dev)); 666 } 667 668 /* GATT address is already in there, make sure it's enabled */ 669 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 670 pgtblctl |= 1; 671 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 672 673 gatt->ag_physical = pgtblctl & ~1; 674 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 675 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 || 676 isc->chiptype == CHIP_G4X) { 677 pcireg_t reg; 678 u_int32_t pgtblctl, gtt_size, stolen; 679 u_int16_t gcc1; 680 681 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1); 682 gcc1 = (u_int16_t)(reg >> 16); 683 684 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 685 686 /* Stolen memory is set up at the beginning of the aperture by 687 * the BIOS, consisting of the GATT followed by 4kb for the 688 * BIOS display. 689 */ 690 switch (isc->chiptype) { 691 case CHIP_I855: 692 gtt_size = 128; 693 break; 694 case CHIP_I915: 695 gtt_size = 256; 696 break; 697 case CHIP_I965: 698 switch (pgtblctl & AGP_I810_PGTBL_SIZE_MASK) { 699 case AGP_I810_PGTBL_SIZE_128KB: 700 case AGP_I810_PGTBL_SIZE_512KB: 701 gtt_size = 512; 702 break; 703 case AGP_I965_PGTBL_SIZE_1MB: 704 gtt_size = 1024; 705 break; 706 case AGP_I965_PGTBL_SIZE_2MB: 707 gtt_size = 2048; 708 break; 709 case AGP_I965_PGTBL_SIZE_1_5MB: 710 gtt_size = 1024 + 512; 711 break; 712 default: 713 aprint_error("Bad PGTBL size\n"); 714 agp_generic_detach(sc); 715 return EINVAL; 716 } 717 break; 718 case CHIP_G33: 719 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 720 case AGP_G33_PGTBL_SIZE_1M: 721 gtt_size = 1024; 722 break; 723 case AGP_G33_PGTBL_SIZE_2M: 724 gtt_size = 2048; 725 break; 726 default: 727 aprint_error(": Bad PGTBL size\n"); 728 agp_generic_detach(sc); 729 return EINVAL; 730 } 731 break; 732 case CHIP_G4X: 733 gtt_size = 0; 734 break; 735 default: 736 aprint_error(": bad chiptype\n"); 737 agp_generic_detach(sc); 738 return EINVAL; 739 } 740 741 switch (gcc1 & AGP_I855_GCC1_GMS) { 742 case AGP_I855_GCC1_GMS_STOLEN_1M: 743 stolen = 1024; 744 break; 745 case AGP_I855_GCC1_GMS_STOLEN_4M: 746 stolen = 4 * 1024; 747 break; 748 case AGP_I855_GCC1_GMS_STOLEN_8M: 749 stolen = 8 * 1024; 750 break; 751 case AGP_I855_GCC1_GMS_STOLEN_16M: 752 stolen = 16 * 1024; 753 break; 754 case AGP_I855_GCC1_GMS_STOLEN_32M: 755 stolen = 32 * 1024; 756 break; 757 case AGP_I915_GCC1_GMS_STOLEN_48M: 758 stolen = 48 * 1024; 759 break; 760 case AGP_I915_GCC1_GMS_STOLEN_64M: 761 stolen = 64 * 1024; 762 break; 763 case AGP_G33_GCC1_GMS_STOLEN_128M: 764 stolen = 128 * 1024; 765 break; 766 case AGP_G33_GCC1_GMS_STOLEN_256M: 767 stolen = 256 * 1024; 768 break; 769 case AGP_G4X_GCC1_GMS_STOLEN_96M: 770 stolen = 96 * 1024; 771 break; 772 case AGP_G4X_GCC1_GMS_STOLEN_160M: 773 stolen = 160 * 1024; 774 break; 775 case AGP_G4X_GCC1_GMS_STOLEN_224M: 776 stolen = 224 * 1024; 777 break; 778 case AGP_G4X_GCC1_GMS_STOLEN_352M: 779 stolen = 352 * 1024; 780 break; 781 default: 782 aprint_error( 783 ": unknown memory configuration, disabling\n"); 784 agp_generic_detach(sc); 785 return EINVAL; 786 } 787 788 switch (gcc1 & AGP_I855_GCC1_GMS) { 789 case AGP_I915_GCC1_GMS_STOLEN_48M: 790 case AGP_I915_GCC1_GMS_STOLEN_64M: 791 if (isc->chiptype != CHIP_I915 && 792 isc->chiptype != CHIP_I965 && 793 isc->chiptype != CHIP_G33 && 794 isc->chiptype != CHIP_G4X) 795 stolen = 0; 796 break; 797 case AGP_G33_GCC1_GMS_STOLEN_128M: 798 case AGP_G33_GCC1_GMS_STOLEN_256M: 799 if (isc->chiptype != CHIP_I965 && 800 isc->chiptype != CHIP_G33 && 801 isc->chiptype != CHIP_G4X) 802 stolen = 0; 803 break; 804 case AGP_G4X_GCC1_GMS_STOLEN_96M: 805 case AGP_G4X_GCC1_GMS_STOLEN_160M: 806 case AGP_G4X_GCC1_GMS_STOLEN_224M: 807 case AGP_G4X_GCC1_GMS_STOLEN_352M: 808 if (isc->chiptype != CHIP_I965 && 809 isc->chiptype != CHIP_G4X) 810 stolen = 0; 811 break; 812 } 813 814 /* BIOS space */ 815 gtt_size += 4; 816 817 isc->stolen = (stolen - gtt_size) * 1024 / 4096; 818 819 if (isc->stolen > 0) { 820 aprint_normal(": detected %dk stolen memory\n%s", 821 isc->stolen * 4, device_xname(sc->as_dev)); 822 } 823 824 /* GATT address is already in there, make sure it's enabled */ 825 pgtblctl |= 1; 826 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 827 828 gatt->ag_physical = pgtblctl & ~1; 829 } 830 831 /* 832 * Make sure the chipset can see everything. 833 */ 834 agp_flush_cache(); 835 836 /* 837 * Publish what we found for kludgey drivers (I'm looking at 838 * you, drm). 839 */ 840 if (agp_i810_sc == NULL) 841 agp_i810_sc = sc; 842 else 843 aprint_error_dev(sc->as_dev, "i810 agp already attached\n"); 844 845 return 0; 846 } 847 848 #if 0 849 static int 850 agp_i810_detach(struct agp_softc *sc) 851 { 852 int error; 853 struct agp_i810_softc *isc = sc->as_chipc; 854 855 error = agp_generic_detach(sc); 856 if (error) 857 return error; 858 859 switch (isc->chiptype) { 860 case CHIP_I915: 861 case CHIP_I965: 862 case CHIP_G33: 863 case CHIP_G4X: 864 if (isc->flush_addr) { 865 /* If we allocated a page, clear it. */ 866 if (isc->chiptype == CHIP_I915) { 867 pci_conf_write(sc->as_pc, sc->as_tag, 868 AGP_I915_IFPADDR, 0); 869 } else { 870 pci_conf_write(sc->as_pc, sc->as_tag, 871 AGP_I965_IFPADDR, 0); 872 pci_conf_write(sc->as_pc, sc->as_tag, 873 AGP_I965_IFPADDR + 4, 0); 874 } 875 isc->flush_addr = 0; 876 bus_space_free(isc->flush_bst, isc->flush_bsh, 877 PAGE_SIZE); 878 } else { 879 /* Otherwise, just unmap the pre-allocated page. */ 880 bus_space_unmap(isc->flush_bst, isc->flush_bsh, 881 PAGE_SIZE); 882 } 883 break; 884 } 885 886 /* Clear the GATT base. */ 887 if (sc->chiptype == CHIP_I810) { 888 WRITE4(AGP_I810_PGTBL_CTL, 0); 889 } else { 890 unsigned int pgtblctl; 891 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 892 pgtblctl &= ~1; 893 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 894 } 895 896 /* Put the aperture back the way it started. */ 897 AGP_SET_APERTURE(sc, isc->initial_aperture); 898 899 if (sc->chiptype == CHIP_I810) { 900 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap, 901 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 902 } 903 free(sc->gatt, M_AGP); 904 905 return 0; 906 } 907 #endif 908 909 static u_int32_t 910 agp_i810_get_aperture(struct agp_softc *sc) 911 { 912 struct agp_i810_softc *isc = sc->as_chipc; 913 pcireg_t reg; 914 u_int32_t size; 915 u_int16_t miscc, gcc1, msac; 916 917 size = 0; 918 919 switch (isc->chiptype) { 920 case CHIP_I810: 921 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 922 miscc = (u_int16_t)(reg >> 16); 923 if ((miscc & AGP_I810_MISCC_WINSIZE) == 924 AGP_I810_MISCC_WINSIZE_32) 925 size = 32 * 1024 * 1024; 926 else 927 size = 64 * 1024 * 1024; 928 break; 929 case CHIP_I830: 930 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 931 gcc1 = (u_int16_t)(reg >> 16); 932 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 933 size = 64 * 1024 * 1024; 934 else 935 size = 128 * 1024 * 1024; 936 break; 937 case CHIP_I855: 938 size = 128 * 1024 * 1024; 939 break; 940 case CHIP_I915: 941 case CHIP_G33: 942 case CHIP_G4X: 943 reg = pci_conf_read(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, 944 AGP_I915_MSAC); 945 msac = (u_int16_t)(reg >> 16); 946 if (msac & AGP_I915_MSAC_APER_128M) 947 size = 128 * 1024 * 1024; 948 else 949 size = 256 * 1024 * 1024; 950 break; 951 case CHIP_I965: 952 size = 512 * 1024 * 1024; 953 break; 954 default: 955 aprint_error(": Unknown chipset\n"); 956 } 957 958 return size; 959 } 960 961 static int 962 agp_i810_set_aperture(struct agp_softc *sc, u_int32_t aperture) 963 { 964 struct agp_i810_softc *isc = sc->as_chipc; 965 pcireg_t reg; 966 u_int16_t miscc, gcc1; 967 968 switch (isc->chiptype) { 969 case CHIP_I810: 970 /* 971 * Double check for sanity. 972 */ 973 if (aperture != (32 * 1024 * 1024) && 974 aperture != (64 * 1024 * 1024)) { 975 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 976 aperture); 977 return EINVAL; 978 } 979 980 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 981 miscc = (u_int16_t)(reg >> 16); 982 miscc &= ~AGP_I810_MISCC_WINSIZE; 983 if (aperture == 32 * 1024 * 1024) 984 miscc |= AGP_I810_MISCC_WINSIZE_32; 985 else 986 miscc |= AGP_I810_MISCC_WINSIZE_64; 987 988 reg &= 0x0000ffff; 989 reg |= ((pcireg_t)miscc) << 16; 990 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I810_SMRAM, reg); 991 break; 992 case CHIP_I830: 993 if (aperture != (64 * 1024 * 1024) && 994 aperture != (128 * 1024 * 1024)) { 995 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 996 aperture); 997 return EINVAL; 998 } 999 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 1000 gcc1 = (u_int16_t)(reg >> 16); 1001 gcc1 &= ~AGP_I830_GCC1_GMASIZE; 1002 if (aperture == 64 * 1024 * 1024) 1003 gcc1 |= AGP_I830_GCC1_GMASIZE_64; 1004 else 1005 gcc1 |= AGP_I830_GCC1_GMASIZE_128; 1006 1007 reg &= 0x0000ffff; 1008 reg |= ((pcireg_t)gcc1) << 16; 1009 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I830_GCC0, reg); 1010 break; 1011 case CHIP_I855: 1012 case CHIP_I915: 1013 if (aperture != agp_i810_get_aperture(sc)) { 1014 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 1015 aperture); 1016 return EINVAL; 1017 } 1018 break; 1019 case CHIP_I965: 1020 if (aperture != 512 * 1024 * 1024) { 1021 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 1022 aperture); 1023 return EINVAL; 1024 } 1025 break; 1026 } 1027 1028 return 0; 1029 } 1030 1031 static int 1032 agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 1033 { 1034 struct agp_i810_softc *isc = sc->as_chipc; 1035 1036 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) { 1037 #ifdef AGP_DEBUG 1038 printf("%s: failed: offset 0x%08x, shift %d, entries %d\n", 1039 device_xname(sc->as_dev), (int)offset, AGP_PAGE_SHIFT, 1040 isc->gatt->ag_entries); 1041 #endif 1042 return EINVAL; 1043 } 1044 1045 if (isc->chiptype != CHIP_I810) { 1046 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1047 #ifdef AGP_DEBUG 1048 printf("%s: trying to bind into stolen memory\n", 1049 device_xname(sc->as_dev)); 1050 #endif 1051 return EINVAL; 1052 } 1053 } 1054 1055 return agp_i810_write_gtt_entry(isc, offset, physical | 1); 1056 } 1057 1058 static int 1059 agp_i810_unbind_page(struct agp_softc *sc, off_t offset) 1060 { 1061 struct agp_i810_softc *isc = sc->as_chipc; 1062 1063 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 1064 return EINVAL; 1065 1066 if (isc->chiptype != CHIP_I810 ) { 1067 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1068 #ifdef AGP_DEBUG 1069 printf("%s: trying to unbind from stolen memory\n", 1070 device_xname(sc->as_dev)); 1071 #endif 1072 return EINVAL; 1073 } 1074 } 1075 1076 return agp_i810_write_gtt_entry(isc, offset, 0); 1077 } 1078 1079 /* 1080 * Writing via memory mapped registers already flushes all TLBs. 1081 */ 1082 static void 1083 agp_i810_flush_tlb(struct agp_softc *sc) 1084 { 1085 } 1086 1087 static int 1088 agp_i810_enable(struct agp_softc *sc, u_int32_t mode) 1089 { 1090 1091 return 0; 1092 } 1093 1094 static struct agp_memory * 1095 agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size) 1096 { 1097 struct agp_i810_softc *isc = sc->as_chipc; 1098 struct agp_memory *mem; 1099 1100 #ifdef AGP_DEBUG 1101 printf("AGP: alloc(%d, 0x%x)\n", type, (int) size); 1102 #endif 1103 1104 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 1105 return 0; 1106 1107 if (sc->as_allocated + size > sc->as_maxmem) 1108 return 0; 1109 1110 if (type == 1) { 1111 /* 1112 * Mapping local DRAM into GATT. 1113 */ 1114 if (isc->chiptype != CHIP_I810 ) 1115 return 0; 1116 if (size != isc->dcache_size) 1117 return 0; 1118 } else if (type == 2) { 1119 /* 1120 * Bogus mapping for the hardware cursor. 1121 */ 1122 if (size != AGP_PAGE_SIZE && size != 4 * AGP_PAGE_SIZE) 1123 return 0; 1124 } 1125 1126 mem = malloc(sizeof *mem, M_AGP, M_WAITOK|M_ZERO); 1127 if (mem == NULL) 1128 return NULL; 1129 mem->am_id = sc->as_nextid++; 1130 mem->am_size = size; 1131 mem->am_type = type; 1132 1133 if (type == 2) { 1134 /* 1135 * Allocate and wire down the memory now so that we can 1136 * get its physical address. 1137 */ 1138 mem->am_dmaseg = malloc(sizeof *mem->am_dmaseg, M_AGP, 1139 M_WAITOK); 1140 if (mem->am_dmaseg == NULL) { 1141 free(mem, M_AGP); 1142 return NULL; 1143 } 1144 if (agp_alloc_dmamem(sc->as_dmat, size, 0, 1145 &mem->am_dmamap, &mem->am_virtual, &mem->am_physical, 1146 mem->am_dmaseg, 1, &mem->am_nseg) != 0) { 1147 free(mem->am_dmaseg, M_AGP); 1148 free(mem, M_AGP); 1149 return NULL; 1150 } 1151 memset(mem->am_virtual, 0, size); 1152 } else if (type != 1) { 1153 if (bus_dmamap_create(sc->as_dmat, size, size / PAGE_SIZE + 1, 1154 size, 0, BUS_DMA_NOWAIT, 1155 &mem->am_dmamap) != 0) { 1156 free(mem, M_AGP); 1157 return NULL; 1158 } 1159 } 1160 1161 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link); 1162 sc->as_allocated += size; 1163 1164 return mem; 1165 } 1166 1167 static int 1168 agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem) 1169 { 1170 if (mem->am_is_bound) 1171 return EBUSY; 1172 1173 if (mem->am_type == 2) { 1174 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap, 1175 mem->am_virtual, mem->am_dmaseg, mem->am_nseg); 1176 free(mem->am_dmaseg, M_AGP); 1177 } 1178 1179 sc->as_allocated -= mem->am_size; 1180 TAILQ_REMOVE(&sc->as_memory, mem, am_link); 1181 free(mem, M_AGP); 1182 return 0; 1183 } 1184 1185 static int 1186 agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem, 1187 off_t offset) 1188 { 1189 struct agp_i810_softc *isc = sc->as_chipc; 1190 u_int32_t regval, i; 1191 1192 if (mem->am_is_bound != 0) 1193 return EINVAL; 1194 1195 /* 1196 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 1197 * X server for mysterious reasons which leads to crashes if we write 1198 * to the GTT through the MMIO window. 1199 * Until the issue is solved, simply restore it. 1200 */ 1201 regval = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL); 1202 if (regval != (isc->gatt->ag_physical | 1)) { 1203 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%x - fixing\n", 1204 regval); 1205 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 1206 isc->gatt->ag_physical | 1); 1207 } 1208 1209 if (mem->am_type == 2) { 1210 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1211 agp_i810_bind_page(sc, offset + i, 1212 mem->am_physical + i); 1213 mem->am_offset = offset; 1214 mem->am_is_bound = 1; 1215 return 0; 1216 } 1217 1218 if (mem->am_type != 1) 1219 return agp_generic_bind_memory(sc, mem, offset); 1220 1221 if (isc->chiptype != CHIP_I810) 1222 return EINVAL; 1223 1224 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1225 agp_i810_write_gtt_entry(isc, i, i | 3); 1226 mem->am_is_bound = 1; 1227 return 0; 1228 } 1229 1230 static int 1231 agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem) 1232 { 1233 struct agp_i810_softc *isc = sc->as_chipc; 1234 u_int32_t i; 1235 1236 if (mem->am_is_bound == 0) 1237 return EINVAL; 1238 1239 if (mem->am_type == 2) { 1240 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1241 agp_i810_unbind_page(sc, mem->am_offset + i); 1242 mem->am_offset = 0; 1243 mem->am_is_bound = 0; 1244 return 0; 1245 } 1246 1247 if (mem->am_type != 1) 1248 return agp_generic_unbind_memory(sc, mem); 1249 1250 if (isc->chiptype != CHIP_I810) 1251 return EINVAL; 1252 1253 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1254 agp_i810_write_gtt_entry(isc, i, 0); 1255 mem->am_is_bound = 0; 1256 return 0; 1257 } 1258 1259 static bool 1260 agp_i810_resume(device_t dv, const pmf_qual_t *qual) 1261 { 1262 struct agp_softc *sc = device_private(dv); 1263 struct agp_i810_softc *isc = sc->as_chipc; 1264 1265 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 1266 agp_flush_cache(); 1267 1268 return true; 1269 } 1270
Indexes created Tue Oct 07 21:09:53 GMT 2025