agp_i810.c revision 1.79
1 /* $NetBSD: agp_i810.c,v 1.79 2014/05/27 03:17:33 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.79 2014/05/27 03:17:33 riastradh Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/proc.h> 40 #include <sys/device.h> 41 #include <sys/conf.h> 42 #include <sys/xcall.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcidevs.h> 47 #include <dev/pci/agpvar.h> 48 #include <dev/pci/agpreg.h> 49 #include <dev/pci/agp_i810var.h> 50 51 #include <sys/agpio.h> 52 53 #include <sys/bus.h> 54 55 #include "agp_intel.h" 56 57 struct agp_softc *agp_i810_sc = NULL; 58 59 #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off) 60 #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off) 61 #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v) 62 63 #define CHIP_I810 0 /* i810/i815 */ 64 #define CHIP_I830 1 /* 830M/845G */ 65 #define CHIP_I855 2 /* 852GM/855GM/865G */ 66 #define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */ 67 #define CHIP_I965 4 /* 965Q/965PM */ 68 #define CHIP_G33 5 /* G33/Q33/Q35 */ 69 #define CHIP_G4X 6 /* G45/Q45 */ 70 71 /* XXX hack, see below */ 72 static bus_addr_t agp_i810_vga_regbase; 73 static bus_space_handle_t agp_i810_vga_bsh; 74 75 static u_int32_t agp_i810_get_aperture(struct agp_softc *); 76 static int agp_i810_set_aperture(struct agp_softc *, u_int32_t); 77 static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t); 78 static int agp_i810_unbind_page(struct agp_softc *, off_t); 79 static void agp_i810_flush_tlb(struct agp_softc *); 80 static int agp_i810_enable(struct agp_softc *, u_int32_t mode); 81 static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int, 82 vsize_t); 83 static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *); 84 static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, off_t); 85 static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *); 86 87 static bool agp_i810_resume(device_t, const pmf_qual_t *); 88 static int agp_i810_init(struct agp_softc *); 89 90 static int agp_i810_setup_chipset_flush_page(struct agp_softc *); 91 static void agp_i810_teardown_chipset_flush_page(struct agp_softc *); 92 static int agp_i810_init(struct agp_softc *); 93 94 static struct agp_methods agp_i810_methods = { 95 agp_i810_get_aperture, 96 agp_i810_set_aperture, 97 agp_i810_bind_page, 98 agp_i810_unbind_page, 99 agp_i810_flush_tlb, 100 agp_i810_enable, 101 agp_i810_alloc_memory, 102 agp_i810_free_memory, 103 agp_i810_bind_memory, 104 agp_i810_unbind_memory, 105 }; 106 107 int 108 agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, bus_addr_t v) 109 { 110 u_int32_t pte; 111 112 /* Bits 11:4 (physical start address extension) should be zero. */ 113 if ((v & 0xff0) != 0) 114 return EINVAL; 115 116 pte = (u_int32_t)v; 117 /* 118 * We need to massage the pte if bus_addr_t is wider than 32 bits. 119 * The compiler isn't smart enough, hence the casts to uintmax_t. 120 */ 121 if (sizeof(bus_addr_t) > sizeof(u_int32_t)) { 122 /* 965+ can do 36-bit addressing, add in the extra bits. */ 123 if (isc->chiptype == CHIP_I965 || 124 isc->chiptype == CHIP_G33 || 125 isc->chiptype == CHIP_G4X) { 126 if (((uintmax_t)v >> 36) != 0) 127 return EINVAL; 128 pte |= (v >> 28) & 0xf0; 129 } else { 130 if (((uintmax_t)v >> 32) != 0) 131 return EINVAL; 132 } 133 } 134 135 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, 136 4*(off >> AGP_PAGE_SHIFT), pte); 137 138 return 0; 139 } 140 141 void 142 agp_i810_post_gtt_entry(struct agp_i810_softc *isc, off_t off) 143 { 144 145 (void)bus_space_read_4(isc->gtt_bst, isc->gtt_bsh, 146 4*(off >> AGP_PAGE_SHIFT)); 147 } 148 149 static void 150 agp_flush_cache_xc(void *a __unused, void *b __unused) 151 { 152 153 agp_flush_cache(); 154 } 155 156 void 157 agp_i810_chipset_flush(struct agp_i810_softc *isc) 158 { 159 unsigned int timo = 20000; /* * 50 us = 1 s */ 160 161 switch (isc->chiptype) { 162 case CHIP_I810: 163 break; 164 case CHIP_I830: 165 case CHIP_I855: 166 /* 167 * Flush all CPU caches. If we're cold, we can't run 168 * xcalls, but there should be only one CPU up, so 169 * flushing only the local CPU's cache should suffice. 170 * 171 * XXX Come to think of it, do these chipsets appear in 172 * any multi-CPU systems? 173 */ 174 if (cold) 175 agp_flush_cache(); 176 else 177 xc_wait(xc_broadcast(0, &agp_flush_cache_xc, 178 NULL, NULL)); 179 WRITE4(AGP_I830_HIC, READ4(AGP_I830_HIC) | __BIT(31)); 180 while (ISSET(READ4(AGP_I830_HIC), __BIT(31))) { 181 if (timo-- == 0) 182 break; 183 DELAY(50); 184 } 185 break; 186 case CHIP_I915: 187 case CHIP_I965: 188 case CHIP_G33: 189 case CHIP_G4X: 190 bus_space_write_4(isc->flush_bst, isc->flush_bsh, 0, 1); 191 break; 192 } 193 } 194 195 /* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */ 196 static int 197 agp_i810_vgamatch(const struct pci_attach_args *pa) 198 { 199 200 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 201 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 202 return (0); 203 204 switch (PCI_PRODUCT(pa->pa_id)) { 205 case PCI_PRODUCT_INTEL_82810_GC: 206 case PCI_PRODUCT_INTEL_82810_DC100_GC: 207 case PCI_PRODUCT_INTEL_82810E_GC: 208 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 209 case PCI_PRODUCT_INTEL_82830MP_IV: 210 case PCI_PRODUCT_INTEL_82845G_IGD: 211 case PCI_PRODUCT_INTEL_82855GM_IGD: 212 case PCI_PRODUCT_INTEL_82865_IGD: 213 case PCI_PRODUCT_INTEL_82915G_IGD: 214 case PCI_PRODUCT_INTEL_82915GM_IGD: 215 case PCI_PRODUCT_INTEL_82945P_IGD: 216 case PCI_PRODUCT_INTEL_82945GM_IGD: 217 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 218 case PCI_PRODUCT_INTEL_82945GME_IGD: 219 case PCI_PRODUCT_INTEL_E7221_IGD: 220 case PCI_PRODUCT_INTEL_82965Q_IGD: 221 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 222 case PCI_PRODUCT_INTEL_82965PM_IGD: 223 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 224 case PCI_PRODUCT_INTEL_82G33_IGD: 225 case PCI_PRODUCT_INTEL_82G33_IGD_1: 226 case PCI_PRODUCT_INTEL_82965G_IGD: 227 case PCI_PRODUCT_INTEL_82965G_IGD_1: 228 case PCI_PRODUCT_INTEL_82965GME_IGD: 229 case PCI_PRODUCT_INTEL_82Q35_IGD: 230 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 231 case PCI_PRODUCT_INTEL_82Q33_IGD: 232 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 233 case PCI_PRODUCT_INTEL_82G35_IGD: 234 case PCI_PRODUCT_INTEL_82G35_IGD_1: 235 case PCI_PRODUCT_INTEL_82946GZ_IGD: 236 case PCI_PRODUCT_INTEL_82GM45_IGD: 237 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 238 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 239 case PCI_PRODUCT_INTEL_82Q45_IGD: 240 case PCI_PRODUCT_INTEL_82G45_IGD: 241 case PCI_PRODUCT_INTEL_82G41_IGD: 242 case PCI_PRODUCT_INTEL_82B43_IGD: 243 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 244 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 245 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 246 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 247 return (1); 248 } 249 250 return (0); 251 } 252 253 static int 254 agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg) 255 { 256 /* 257 * Find the aperture. Don't map it (yet), this would 258 * eat KVA. 259 */ 260 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 261 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize, 262 &sc->as_apflags) != 0) 263 return ENXIO; 264 265 sc->as_apt = pa->pa_memt; 266 267 return 0; 268 } 269 270 int 271 agp_i810_attach(device_t parent, device_t self, void *aux) 272 { 273 struct agp_softc *sc = device_private(self); 274 struct agp_i810_softc *isc; 275 struct agp_gatt *gatt; 276 int apbase, mmadr_bar, gtt_bar; 277 int mmadr_type, mmadr_flags; 278 bus_addr_t mmadr, gtt_off; 279 bus_size_t mmadr_size; 280 int error; 281 282 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 283 if (isc == NULL) { 284 aprint_error(": can't allocate chipset-specific softc\n"); 285 error = ENOMEM; 286 goto fail0; 287 } 288 sc->as_chipc = isc; 289 sc->as_methods = &agp_i810_methods; 290 291 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) { 292 #if NAGP_INTEL > 0 293 const struct pci_attach_args *pa = aux; 294 295 switch (PCI_PRODUCT(pa->pa_id)) { 296 case PCI_PRODUCT_INTEL_82840_HB: 297 case PCI_PRODUCT_INTEL_82865_HB: 298 case PCI_PRODUCT_INTEL_82845G_DRAM: 299 case PCI_PRODUCT_INTEL_82815_FULL_HUB: 300 case PCI_PRODUCT_INTEL_82855GM_MCH: 301 free(isc, M_AGP); 302 return agp_intel_attach(parent, self, aux); 303 } 304 #endif 305 aprint_error(": can't find internal VGA device config space\n"); 306 error = ENOENT; 307 goto fail1; 308 } 309 310 /* XXXfvdl */ 311 sc->as_dmat = isc->vga_pa.pa_dmat; 312 313 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 314 case PCI_PRODUCT_INTEL_82810_GC: 315 case PCI_PRODUCT_INTEL_82810_DC100_GC: 316 case PCI_PRODUCT_INTEL_82810E_GC: 317 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 318 isc->chiptype = CHIP_I810; 319 break; 320 case PCI_PRODUCT_INTEL_82830MP_IV: 321 case PCI_PRODUCT_INTEL_82845G_IGD: 322 isc->chiptype = CHIP_I830; 323 break; 324 case PCI_PRODUCT_INTEL_82855GM_IGD: 325 case PCI_PRODUCT_INTEL_82865_IGD: 326 isc->chiptype = CHIP_I855; 327 break; 328 case PCI_PRODUCT_INTEL_82915G_IGD: 329 case PCI_PRODUCT_INTEL_82915GM_IGD: 330 case PCI_PRODUCT_INTEL_82945P_IGD: 331 case PCI_PRODUCT_INTEL_82945GM_IGD: 332 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 333 case PCI_PRODUCT_INTEL_82945GME_IGD: 334 case PCI_PRODUCT_INTEL_E7221_IGD: 335 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 336 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 337 isc->chiptype = CHIP_I915; 338 break; 339 case PCI_PRODUCT_INTEL_82965Q_IGD: 340 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 341 case PCI_PRODUCT_INTEL_82965PM_IGD: 342 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 343 case PCI_PRODUCT_INTEL_82965G_IGD: 344 case PCI_PRODUCT_INTEL_82965G_IGD_1: 345 case PCI_PRODUCT_INTEL_82965GME_IGD: 346 case PCI_PRODUCT_INTEL_82946GZ_IGD: 347 case PCI_PRODUCT_INTEL_82G35_IGD: 348 case PCI_PRODUCT_INTEL_82G35_IGD_1: 349 isc->chiptype = CHIP_I965; 350 break; 351 case PCI_PRODUCT_INTEL_82Q35_IGD: 352 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 353 case PCI_PRODUCT_INTEL_82G33_IGD: 354 case PCI_PRODUCT_INTEL_82G33_IGD_1: 355 case PCI_PRODUCT_INTEL_82Q33_IGD: 356 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 357 isc->chiptype = CHIP_G33; 358 break; 359 case PCI_PRODUCT_INTEL_82GM45_IGD: 360 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 361 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 362 case PCI_PRODUCT_INTEL_82Q45_IGD: 363 case PCI_PRODUCT_INTEL_82G45_IGD: 364 case PCI_PRODUCT_INTEL_82G41_IGD: 365 case PCI_PRODUCT_INTEL_82B43_IGD: 366 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 367 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 368 isc->chiptype = CHIP_G4X; 369 break; 370 } 371 372 mmadr_type = PCI_MAPREG_TYPE_MEM; 373 switch (isc->chiptype) { 374 case CHIP_I915: 375 case CHIP_G33: 376 apbase = AGP_I915_GMADR; 377 mmadr_bar = AGP_I915_MMADR; 378 gtt_bar = AGP_I915_GTTADR; 379 break; 380 case CHIP_I965: 381 apbase = AGP_I965_GMADR; 382 mmadr_bar = AGP_I965_MMADR; 383 mmadr_type |= PCI_MAPREG_MEM_TYPE_64BIT; 384 gtt_bar = 0; 385 gtt_off = AGP_I965_GTT; 386 break; 387 case CHIP_G4X: 388 apbase = AGP_I965_GMADR; 389 mmadr_bar = AGP_I965_MMADR; 390 mmadr_type |= PCI_MAPREG_MEM_TYPE_64BIT; 391 gtt_bar = 0; 392 gtt_off = AGP_G4X_GTT; 393 break; 394 default: 395 apbase = AGP_I810_GMADR; 396 mmadr_bar = AGP_I810_MMADR; 397 gtt_bar = 0; 398 gtt_off = AGP_I810_GTT; 399 break; 400 } 401 402 /* Map (or, rather, find the address and size of) the aperture. */ 403 if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) 404 error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase); 405 else 406 error = agp_map_aperture(&isc->vga_pa, sc, apbase); 407 if (error) { 408 aprint_error(": can't map aperture\n"); 409 goto fail1; 410 } 411 412 /* Map the memory-mapped I/O registers, or the non-GTT part. */ 413 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, mmadr_bar, 414 mmadr_type, &mmadr, &mmadr_size, &mmadr_flags)) { 415 aprint_error_dev(self, "can't find MMIO registers\n"); 416 error = ENXIO; 417 goto fail1; 418 } 419 if (gtt_bar == 0) { 420 if (mmadr_size < gtt_off) { 421 aprint_error_dev(self, "MMIO registers too small" 422 ": %"PRIuMAX" < %"PRIuMAX"\n", 423 (uintmax_t)mmadr_size, (uintmax_t)gtt_off); 424 error = ENXIO; 425 goto fail1; 426 } 427 isc->size = gtt_off; 428 } else { 429 isc->size = mmadr_size; 430 } 431 isc->bst = isc->vga_pa.pa_memt; 432 error = bus_space_map(isc->bst, mmadr, isc->size, mmadr_flags, 433 &isc->bsh); 434 if (error) { 435 aprint_error_dev(self, "can't map MMIO registers: %d\n", 436 error); 437 error = ENXIO; 438 goto fail1; 439 } 440 441 /* Map the GTT, from either part of the MMIO region or its own BAR. */ 442 if (gtt_bar == 0) { 443 isc->gtt_bst = isc->bst; 444 isc->gtt_size = (mmadr_size - gtt_off); 445 error = bus_space_map(isc->gtt_bst, gtt_off, isc->gtt_size, 446 mmadr_flags, &isc->gtt_bsh); 447 if (error) { 448 aprint_error_dev(self, "can't map GTT: %d\n", error); 449 error = ENXIO; 450 goto fail2; 451 } 452 } else { 453 /* 454 * All chipsets with a separate BAR for the GTT, namely 455 * the i915 and G33 families, have 32-bit GTT BARs. 456 * 457 * XXX [citation needed] 458 */ 459 if (pci_mapreg_map(&isc->vga_pa, gtt_bar, PCI_MAPREG_TYPE_MEM, 460 0, 461 &isc->gtt_bst, &isc->gtt_bsh, NULL, &isc->gtt_size)) { 462 aprint_error_dev(self, "can't map GTT\n"); 463 error = ENXIO; 464 goto fail2; 465 } 466 } 467 468 /* Set up a chipset flush page if necessary. */ 469 switch (isc->chiptype) { 470 case CHIP_I915: 471 case CHIP_I965: 472 case CHIP_G33: 473 case CHIP_G4X: 474 error = agp_i810_setup_chipset_flush_page(sc); 475 if (error) { 476 aprint_error_dev(self, 477 "failed to set up chipset flush page: %d\n", 478 error); 479 goto fail3; 480 } 481 break; 482 } 483 484 /* Set up the generic AGP GATT record. */ 485 isc->initial_aperture = AGP_GET_APERTURE(sc); 486 gatt = malloc(sizeof(struct agp_gatt), M_AGP, M_NOWAIT); 487 if (!gatt) { 488 error = ENOMEM; 489 goto fail4; 490 } 491 isc->gatt = gatt; 492 gatt->ag_entries = AGP_GET_APERTURE(sc) >> AGP_PAGE_SHIFT; 493 494 /* Power management. (XXX Nothing to save on suspend? Fishy...) */ 495 if (!pmf_device_register(self, NULL, agp_i810_resume)) 496 aprint_error_dev(self, "couldn't establish power handler\n"); 497 498 /* 499 * XXX horrible hack to allow drm code to use our mapping 500 * of VGA chip registers 501 */ 502 agp_i810_vga_regbase = mmadr; 503 agp_i810_vga_bsh = isc->bsh; 504 505 /* Initialize the chipset. */ 506 error = agp_i810_init(sc); 507 if (error) 508 goto fail5; 509 510 /* Success! */ 511 return 0; 512 513 #if notyet 514 fail6: __unused 515 agp_i810_fini(sc); 516 #endif 517 fail5: pmf_device_deregister(self); 518 free(gatt, M_AGP); 519 isc->gatt = NULL; 520 fail4: switch (isc->chiptype) { 521 case CHIP_I915: 522 case CHIP_I965: 523 case CHIP_G33: 524 case CHIP_G4X: 525 agp_i810_teardown_chipset_flush_page(sc); 526 break; 527 } 528 fail3: bus_space_unmap(isc->gtt_bst, isc->gtt_bsh, isc->gtt_size); 529 isc->gtt_size = 0; 530 fail2: bus_space_unmap(isc->bst, isc->bsh, isc->size); 531 isc->size = 0; 532 fail1: free(isc, M_AGP); 533 sc->as_chipc = NULL; 534 fail0: agp_generic_detach(sc); 535 KASSERT(error); 536 return error; 537 } 538 539 static int 540 agp_i810_setup_chipset_flush_page(struct agp_softc *sc) 541 { 542 struct agp_i810_softc *const isc = sc->as_chipc; 543 pcireg_t reg, lo, hi; 544 bus_addr_t addr, minaddr, maxaddr; 545 int error; 546 547 /* We always use memory-mapped I/O. */ 548 isc->flush_bst = isc->vga_pa.pa_memt; 549 550 /* No page allocated yet. */ 551 isc->flush_addr = 0; 552 553 /* Read the PCI config register: 4-byte on gen3, 8-byte on gen>=4. */ 554 if (isc->chiptype == CHIP_I915) { 555 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR); 556 addr = reg; 557 minaddr = PAGE_SIZE; /* XXX PCIBIOS_MIN_MEM? */ 558 maxaddr = UINT32_MAX; 559 } else { 560 hi = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I965_IFPADDR+4); 561 lo = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I965_IFPADDR); 562 /* 563 * Convert to uint64_t, rather than bus_addr_t which 564 * may be 32-bit, to avoid undefined behaviour with a 565 * too-wide shift. Since the BIOS doesn't know whether 566 * the OS will run 64-bit or with PAE, it ought to 567 * configure at most a 32-bit physical address, so 568 * let's print a warning in case that happens. 569 */ 570 addr = ((uint64_t)hi << 32) | lo; 571 if (hi) { 572 aprint_error_dev(sc->as_dev, 573 "BIOS configured >32-bit flush page address" 574 ": %"PRIx64"\n", ((uint64_t)hi << 32) | lo); 575 #if __i386__ && !PAE 576 return EIO; 577 #endif 578 } 579 minaddr = PAGE_SIZE; /* XXX PCIBIOS_MIN_MEM? */ 580 maxaddr = MIN(UINT64_MAX, ~(bus_addr_t)0); 581 } 582 583 /* Allocate or map a pre-allocated a page for it. */ 584 if (ISSET(addr, 1)) { 585 /* BIOS allocated it for us. Use that. */ 586 error = bus_space_map(isc->flush_bst, addr & ~1, PAGE_SIZE, 0, 587 &isc->flush_bsh); 588 if (error) 589 return error; 590 } else { 591 /* None allocated. Allocate one. */ 592 error = bus_space_alloc(isc->flush_bst, minaddr, maxaddr, 593 PAGE_SIZE, PAGE_SIZE, 0, 0, 594 &isc->flush_addr, &isc->flush_bsh); 595 if (error) 596 return error; 597 KASSERT(isc->flush_addr != 0); 598 /* Write it into the PCI config register. */ 599 addr = isc->flush_addr | 1; 600 if (isc->chiptype == CHIP_I915) { 601 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR, 602 addr); 603 } else { 604 pci_conf_write(sc->as_pc, sc->as_tag, 605 AGP_I965_IFPADDR + 4, 606 __SHIFTOUT(addr, __BITS(63, 32))); 607 pci_conf_write(sc->as_pc, sc->as_tag, 608 AGP_I965_IFPADDR, 609 __SHIFTOUT(addr, __BITS(31, 0))); 610 } 611 } 612 613 /* Success! */ 614 return 0; 615 } 616 617 static void 618 agp_i810_teardown_chipset_flush_page(struct agp_softc *sc) 619 { 620 struct agp_i810_softc *const isc = sc->as_chipc; 621 622 if (isc->flush_addr) { 623 /* If we allocated a page, clear it. */ 624 if (isc->chiptype == CHIP_I915) { 625 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR, 626 0); 627 } else { 628 pci_conf_write(sc->as_pc, sc->as_tag, 629 AGP_I965_IFPADDR, 0); 630 pci_conf_write(sc->as_pc, sc->as_tag, 631 AGP_I965_IFPADDR + 4, 0); 632 } 633 isc->flush_addr = 0; 634 bus_space_free(isc->flush_bst, isc->flush_bsh, 635 PAGE_SIZE); 636 } else { 637 /* Otherwise, just unmap the pre-allocated page. */ 638 bus_space_unmap(isc->flush_bst, isc->flush_bsh, PAGE_SIZE); 639 } 640 } 641 642 /* 643 * XXX horrible hack to allow drm code to use our mapping 644 * of VGA chip registers 645 */ 646 int 647 agp_i810_borrow(bus_addr_t base, bus_space_handle_t *hdlp) 648 { 649 650 if (!agp_i810_vga_regbase || base != agp_i810_vga_regbase) 651 return 0; 652 *hdlp = agp_i810_vga_bsh; 653 return 1; 654 } 655 656 static int agp_i810_init(struct agp_softc *sc) 657 { 658 struct agp_i810_softc *isc; 659 struct agp_gatt *gatt; 660 661 isc = sc->as_chipc; 662 gatt = isc->gatt; 663 664 if (isc->chiptype == CHIP_I810) { 665 void *virtual; 666 int dummyseg; 667 668 /* Some i810s have on-chip memory called dcache */ 669 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 670 isc->dcache_size = 4 * 1024 * 1024; 671 else 672 isc->dcache_size = 0; 673 674 /* According to the specs the gatt on the i810 must be 64k */ 675 if (agp_alloc_dmamem(sc->as_dmat, 64 * 1024, 676 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical, 677 &gatt->ag_dmaseg, 1, &dummyseg) != 0) { 678 free(gatt, M_AGP); 679 agp_generic_detach(sc); 680 return ENOMEM; 681 } 682 gatt->ag_virtual = (uint32_t *)virtual; 683 gatt->ag_size = gatt->ag_entries * sizeof(u_int32_t); 684 memset(gatt->ag_virtual, 0, gatt->ag_size); 685 686 agp_flush_cache(); 687 /* Install the GATT. */ 688 WRITE4(AGP_I810_PGTBL_CTL, gatt->ag_physical | 1); 689 } else if (isc->chiptype == CHIP_I830) { 690 /* The i830 automatically initializes the 128k gatt on boot. */ 691 pcireg_t reg; 692 u_int32_t pgtblctl; 693 u_int16_t gcc1; 694 695 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 696 gcc1 = (u_int16_t)(reg >> 16); 697 switch (gcc1 & AGP_I830_GCC1_GMS) { 698 case AGP_I830_GCC1_GMS_STOLEN_512: 699 isc->stolen = (512 - 132) * 1024 / 4096; 700 break; 701 case AGP_I830_GCC1_GMS_STOLEN_1024: 702 isc->stolen = (1024 - 132) * 1024 / 4096; 703 break; 704 case AGP_I830_GCC1_GMS_STOLEN_8192: 705 isc->stolen = (8192 - 132) * 1024 / 4096; 706 break; 707 default: 708 isc->stolen = 0; 709 aprint_error( 710 ": unknown memory configuration, disabling\n"); 711 agp_generic_detach(sc); 712 return EINVAL; 713 } 714 715 if (isc->stolen > 0) { 716 aprint_normal(": detected %dk stolen memory\n%s", 717 isc->stolen * 4, device_xname(sc->as_dev)); 718 } 719 720 /* GATT address is already in there, make sure it's enabled */ 721 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 722 pgtblctl |= 1; 723 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 724 725 gatt->ag_physical = pgtblctl & ~1; 726 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 727 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 || 728 isc->chiptype == CHIP_G4X) { 729 pcireg_t reg; 730 u_int32_t pgtblctl, gtt_size, stolen; 731 u_int16_t gcc1; 732 733 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1); 734 gcc1 = (u_int16_t)(reg >> 16); 735 736 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 737 738 /* Stolen memory is set up at the beginning of the aperture by 739 * the BIOS, consisting of the GATT followed by 4kb for the 740 * BIOS display. 741 */ 742 switch (isc->chiptype) { 743 case CHIP_I855: 744 gtt_size = 128; 745 break; 746 case CHIP_I915: 747 gtt_size = 256; 748 break; 749 case CHIP_I965: 750 switch (pgtblctl & AGP_I810_PGTBL_SIZE_MASK) { 751 case AGP_I810_PGTBL_SIZE_128KB: 752 case AGP_I810_PGTBL_SIZE_512KB: 753 gtt_size = 512; 754 break; 755 case AGP_I965_PGTBL_SIZE_1MB: 756 gtt_size = 1024; 757 break; 758 case AGP_I965_PGTBL_SIZE_2MB: 759 gtt_size = 2048; 760 break; 761 case AGP_I965_PGTBL_SIZE_1_5MB: 762 gtt_size = 1024 + 512; 763 break; 764 default: 765 aprint_error("Bad PGTBL size\n"); 766 agp_generic_detach(sc); 767 return EINVAL; 768 } 769 break; 770 case CHIP_G33: 771 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 772 case AGP_G33_PGTBL_SIZE_1M: 773 gtt_size = 1024; 774 break; 775 case AGP_G33_PGTBL_SIZE_2M: 776 gtt_size = 2048; 777 break; 778 default: 779 aprint_error(": Bad PGTBL size\n"); 780 agp_generic_detach(sc); 781 return EINVAL; 782 } 783 break; 784 case CHIP_G4X: 785 gtt_size = 0; 786 break; 787 default: 788 aprint_error(": bad chiptype\n"); 789 agp_generic_detach(sc); 790 return EINVAL; 791 } 792 793 switch (gcc1 & AGP_I855_GCC1_GMS) { 794 case AGP_I855_GCC1_GMS_STOLEN_1M: 795 stolen = 1024; 796 break; 797 case AGP_I855_GCC1_GMS_STOLEN_4M: 798 stolen = 4 * 1024; 799 break; 800 case AGP_I855_GCC1_GMS_STOLEN_8M: 801 stolen = 8 * 1024; 802 break; 803 case AGP_I855_GCC1_GMS_STOLEN_16M: 804 stolen = 16 * 1024; 805 break; 806 case AGP_I855_GCC1_GMS_STOLEN_32M: 807 stolen = 32 * 1024; 808 break; 809 case AGP_I915_GCC1_GMS_STOLEN_48M: 810 stolen = 48 * 1024; 811 break; 812 case AGP_I915_GCC1_GMS_STOLEN_64M: 813 stolen = 64 * 1024; 814 break; 815 case AGP_G33_GCC1_GMS_STOLEN_128M: 816 stolen = 128 * 1024; 817 break; 818 case AGP_G33_GCC1_GMS_STOLEN_256M: 819 stolen = 256 * 1024; 820 break; 821 case AGP_G4X_GCC1_GMS_STOLEN_96M: 822 stolen = 96 * 1024; 823 break; 824 case AGP_G4X_GCC1_GMS_STOLEN_160M: 825 stolen = 160 * 1024; 826 break; 827 case AGP_G4X_GCC1_GMS_STOLEN_224M: 828 stolen = 224 * 1024; 829 break; 830 case AGP_G4X_GCC1_GMS_STOLEN_352M: 831 stolen = 352 * 1024; 832 break; 833 default: 834 aprint_error( 835 ": unknown memory configuration, disabling\n"); 836 agp_generic_detach(sc); 837 return EINVAL; 838 } 839 840 switch (gcc1 & AGP_I855_GCC1_GMS) { 841 case AGP_I915_GCC1_GMS_STOLEN_48M: 842 case AGP_I915_GCC1_GMS_STOLEN_64M: 843 if (isc->chiptype != CHIP_I915 && 844 isc->chiptype != CHIP_I965 && 845 isc->chiptype != CHIP_G33 && 846 isc->chiptype != CHIP_G4X) 847 stolen = 0; 848 break; 849 case AGP_G33_GCC1_GMS_STOLEN_128M: 850 case AGP_G33_GCC1_GMS_STOLEN_256M: 851 if (isc->chiptype != CHIP_I965 && 852 isc->chiptype != CHIP_G33 && 853 isc->chiptype != CHIP_G4X) 854 stolen = 0; 855 break; 856 case AGP_G4X_GCC1_GMS_STOLEN_96M: 857 case AGP_G4X_GCC1_GMS_STOLEN_160M: 858 case AGP_G4X_GCC1_GMS_STOLEN_224M: 859 case AGP_G4X_GCC1_GMS_STOLEN_352M: 860 if (isc->chiptype != CHIP_I965 && 861 isc->chiptype != CHIP_G4X) 862 stolen = 0; 863 break; 864 } 865 866 /* BIOS space */ 867 gtt_size += 4; 868 869 isc->stolen = (stolen - gtt_size) * 1024 / 4096; 870 871 if (isc->stolen > 0) { 872 aprint_normal(": detected %dk stolen memory\n%s", 873 isc->stolen * 4, device_xname(sc->as_dev)); 874 } 875 876 /* GATT address is already in there, make sure it's enabled */ 877 pgtblctl |= 1; 878 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 879 880 gatt->ag_physical = pgtblctl & ~1; 881 } 882 883 /* 884 * Make sure the chipset can see everything. 885 */ 886 agp_flush_cache(); 887 888 /* 889 * Publish what we found for kludgey drivers (I'm looking at 890 * you, drm). 891 */ 892 if (agp_i810_sc == NULL) 893 agp_i810_sc = sc; 894 else 895 aprint_error_dev(sc->as_dev, "i810 agp already attached\n"); 896 897 return 0; 898 } 899 900 #if 0 901 static int 902 agp_i810_detach(struct agp_softc *sc) 903 { 904 int error; 905 struct agp_i810_softc *isc = sc->as_chipc; 906 907 error = agp_generic_detach(sc); 908 if (error) 909 return error; 910 911 switch (isc->chiptype) { 912 case CHIP_I915: 913 case CHIP_I965: 914 case CHIP_G33: 915 case CHIP_G4X: 916 agp_i810_teardown_chipset_flush_page(sc); 917 break; 918 } 919 920 /* Clear the GATT base. */ 921 if (sc->chiptype == CHIP_I810) { 922 WRITE4(AGP_I810_PGTBL_CTL, 0); 923 } else { 924 unsigned int pgtblctl; 925 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 926 pgtblctl &= ~1; 927 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 928 } 929 930 /* Put the aperture back the way it started. */ 931 AGP_SET_APERTURE(sc, isc->initial_aperture); 932 933 if (sc->chiptype == CHIP_I810) { 934 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap, 935 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 936 } 937 free(sc->gatt, M_AGP); 938 939 return 0; 940 } 941 #endif 942 943 static u_int32_t 944 agp_i810_get_aperture(struct agp_softc *sc) 945 { 946 struct agp_i810_softc *isc = sc->as_chipc; 947 pcireg_t reg; 948 u_int32_t size; 949 u_int16_t miscc, gcc1, msac; 950 951 size = 0; 952 953 switch (isc->chiptype) { 954 case CHIP_I810: 955 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 956 miscc = (u_int16_t)(reg >> 16); 957 if ((miscc & AGP_I810_MISCC_WINSIZE) == 958 AGP_I810_MISCC_WINSIZE_32) 959 size = 32 * 1024 * 1024; 960 else 961 size = 64 * 1024 * 1024; 962 break; 963 case CHIP_I830: 964 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 965 gcc1 = (u_int16_t)(reg >> 16); 966 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 967 size = 64 * 1024 * 1024; 968 else 969 size = 128 * 1024 * 1024; 970 break; 971 case CHIP_I855: 972 size = 128 * 1024 * 1024; 973 break; 974 case CHIP_I915: 975 case CHIP_G33: 976 case CHIP_G4X: 977 reg = pci_conf_read(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, 978 AGP_I915_MSAC); 979 msac = (u_int16_t)(reg >> 16); 980 if (msac & AGP_I915_MSAC_APER_128M) 981 size = 128 * 1024 * 1024; 982 else 983 size = 256 * 1024 * 1024; 984 break; 985 case CHIP_I965: 986 size = 512 * 1024 * 1024; 987 break; 988 default: 989 aprint_error(": Unknown chipset\n"); 990 } 991 992 return size; 993 } 994 995 static int 996 agp_i810_set_aperture(struct agp_softc *sc, u_int32_t aperture) 997 { 998 struct agp_i810_softc *isc = sc->as_chipc; 999 pcireg_t reg; 1000 u_int16_t miscc, gcc1; 1001 1002 switch (isc->chiptype) { 1003 case CHIP_I810: 1004 /* 1005 * Double check for sanity. 1006 */ 1007 if (aperture != (32 * 1024 * 1024) && 1008 aperture != (64 * 1024 * 1024)) { 1009 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 1010 aperture); 1011 return EINVAL; 1012 } 1013 1014 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 1015 miscc = (u_int16_t)(reg >> 16); 1016 miscc &= ~AGP_I810_MISCC_WINSIZE; 1017 if (aperture == 32 * 1024 * 1024) 1018 miscc |= AGP_I810_MISCC_WINSIZE_32; 1019 else 1020 miscc |= AGP_I810_MISCC_WINSIZE_64; 1021 1022 reg &= 0x0000ffff; 1023 reg |= ((pcireg_t)miscc) << 16; 1024 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I810_SMRAM, reg); 1025 break; 1026 case CHIP_I830: 1027 if (aperture != (64 * 1024 * 1024) && 1028 aperture != (128 * 1024 * 1024)) { 1029 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 1030 aperture); 1031 return EINVAL; 1032 } 1033 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 1034 gcc1 = (u_int16_t)(reg >> 16); 1035 gcc1 &= ~AGP_I830_GCC1_GMASIZE; 1036 if (aperture == 64 * 1024 * 1024) 1037 gcc1 |= AGP_I830_GCC1_GMASIZE_64; 1038 else 1039 gcc1 |= AGP_I830_GCC1_GMASIZE_128; 1040 1041 reg &= 0x0000ffff; 1042 reg |= ((pcireg_t)gcc1) << 16; 1043 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I830_GCC0, reg); 1044 break; 1045 case CHIP_I855: 1046 case CHIP_I915: 1047 if (aperture != agp_i810_get_aperture(sc)) { 1048 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 1049 aperture); 1050 return EINVAL; 1051 } 1052 break; 1053 case CHIP_I965: 1054 if (aperture != 512 * 1024 * 1024) { 1055 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 1056 aperture); 1057 return EINVAL; 1058 } 1059 break; 1060 } 1061 1062 return 0; 1063 } 1064 1065 static int 1066 agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 1067 { 1068 struct agp_i810_softc *isc = sc->as_chipc; 1069 1070 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) { 1071 #ifdef AGP_DEBUG 1072 printf("%s: failed: offset 0x%08x, shift %d, entries %d\n", 1073 device_xname(sc->as_dev), (int)offset, AGP_PAGE_SHIFT, 1074 isc->gatt->ag_entries); 1075 #endif 1076 return EINVAL; 1077 } 1078 1079 if (isc->chiptype != CHIP_I810) { 1080 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1081 #ifdef AGP_DEBUG 1082 printf("%s: trying to bind into stolen memory\n", 1083 device_xname(sc->as_dev)); 1084 #endif 1085 return EINVAL; 1086 } 1087 } 1088 1089 return agp_i810_write_gtt_entry(isc, offset, physical | 1); 1090 } 1091 1092 static int 1093 agp_i810_unbind_page(struct agp_softc *sc, off_t offset) 1094 { 1095 struct agp_i810_softc *isc = sc->as_chipc; 1096 1097 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 1098 return EINVAL; 1099 1100 if (isc->chiptype != CHIP_I810 ) { 1101 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1102 #ifdef AGP_DEBUG 1103 printf("%s: trying to unbind from stolen memory\n", 1104 device_xname(sc->as_dev)); 1105 #endif 1106 return EINVAL; 1107 } 1108 } 1109 1110 return agp_i810_write_gtt_entry(isc, offset, 0); 1111 } 1112 1113 /* 1114 * Writing via memory mapped registers already flushes all TLBs. 1115 */ 1116 static void 1117 agp_i810_flush_tlb(struct agp_softc *sc) 1118 { 1119 } 1120 1121 static int 1122 agp_i810_enable(struct agp_softc *sc, u_int32_t mode) 1123 { 1124 1125 return 0; 1126 } 1127 1128 static struct agp_memory * 1129 agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size) 1130 { 1131 struct agp_i810_softc *isc = sc->as_chipc; 1132 struct agp_memory *mem; 1133 1134 #ifdef AGP_DEBUG 1135 printf("AGP: alloc(%d, 0x%x)\n", type, (int) size); 1136 #endif 1137 1138 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 1139 return 0; 1140 1141 if (sc->as_allocated + size > sc->as_maxmem) 1142 return 0; 1143 1144 if (type == 1) { 1145 /* 1146 * Mapping local DRAM into GATT. 1147 */ 1148 if (isc->chiptype != CHIP_I810 ) 1149 return 0; 1150 if (size != isc->dcache_size) 1151 return 0; 1152 } else if (type == 2) { 1153 /* 1154 * Bogus mapping for the hardware cursor. 1155 */ 1156 if (size != AGP_PAGE_SIZE && size != 4 * AGP_PAGE_SIZE) 1157 return 0; 1158 } 1159 1160 mem = malloc(sizeof *mem, M_AGP, M_WAITOK|M_ZERO); 1161 if (mem == NULL) 1162 return NULL; 1163 mem->am_id = sc->as_nextid++; 1164 mem->am_size = size; 1165 mem->am_type = type; 1166 1167 if (type == 2) { 1168 /* 1169 * Allocate and wire down the memory now so that we can 1170 * get its physical address. 1171 */ 1172 mem->am_dmaseg = malloc(sizeof *mem->am_dmaseg, M_AGP, 1173 M_WAITOK); 1174 if (mem->am_dmaseg == NULL) { 1175 free(mem, M_AGP); 1176 return NULL; 1177 } 1178 if (agp_alloc_dmamem(sc->as_dmat, size, 0, 1179 &mem->am_dmamap, &mem->am_virtual, &mem->am_physical, 1180 mem->am_dmaseg, 1, &mem->am_nseg) != 0) { 1181 free(mem->am_dmaseg, M_AGP); 1182 free(mem, M_AGP); 1183 return NULL; 1184 } 1185 memset(mem->am_virtual, 0, size); 1186 } else if (type != 1) { 1187 if (bus_dmamap_create(sc->as_dmat, size, size / PAGE_SIZE + 1, 1188 size, 0, BUS_DMA_NOWAIT, 1189 &mem->am_dmamap) != 0) { 1190 free(mem, M_AGP); 1191 return NULL; 1192 } 1193 } 1194 1195 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link); 1196 sc->as_allocated += size; 1197 1198 return mem; 1199 } 1200 1201 static int 1202 agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem) 1203 { 1204 if (mem->am_is_bound) 1205 return EBUSY; 1206 1207 if (mem->am_type == 2) { 1208 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap, 1209 mem->am_virtual, mem->am_dmaseg, mem->am_nseg); 1210 free(mem->am_dmaseg, M_AGP); 1211 } 1212 1213 sc->as_allocated -= mem->am_size; 1214 TAILQ_REMOVE(&sc->as_memory, mem, am_link); 1215 free(mem, M_AGP); 1216 return 0; 1217 } 1218 1219 static int 1220 agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem, 1221 off_t offset) 1222 { 1223 struct agp_i810_softc *isc = sc->as_chipc; 1224 u_int32_t regval, i; 1225 1226 if (mem->am_is_bound != 0) 1227 return EINVAL; 1228 1229 /* 1230 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 1231 * X server for mysterious reasons which leads to crashes if we write 1232 * to the GTT through the MMIO window. 1233 * Until the issue is solved, simply restore it. 1234 */ 1235 regval = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL); 1236 if (regval != (isc->gatt->ag_physical | 1)) { 1237 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%x - fixing\n", 1238 regval); 1239 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 1240 isc->gatt->ag_physical | 1); 1241 } 1242 1243 if (mem->am_type == 2) { 1244 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1245 agp_i810_bind_page(sc, offset + i, 1246 mem->am_physical + i); 1247 mem->am_offset = offset; 1248 mem->am_is_bound = 1; 1249 return 0; 1250 } 1251 1252 if (mem->am_type != 1) 1253 return agp_generic_bind_memory(sc, mem, offset); 1254 1255 if (isc->chiptype != CHIP_I810) 1256 return EINVAL; 1257 1258 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1259 agp_i810_write_gtt_entry(isc, i, i | 3); 1260 mem->am_is_bound = 1; 1261 return 0; 1262 } 1263 1264 static int 1265 agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem) 1266 { 1267 struct agp_i810_softc *isc = sc->as_chipc; 1268 u_int32_t i; 1269 1270 if (mem->am_is_bound == 0) 1271 return EINVAL; 1272 1273 if (mem->am_type == 2) { 1274 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1275 agp_i810_unbind_page(sc, mem->am_offset + i); 1276 mem->am_offset = 0; 1277 mem->am_is_bound = 0; 1278 return 0; 1279 } 1280 1281 if (mem->am_type != 1) 1282 return agp_generic_unbind_memory(sc, mem); 1283 1284 if (isc->chiptype != CHIP_I810) 1285 return EINVAL; 1286 1287 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1288 agp_i810_write_gtt_entry(isc, i, 0); 1289 mem->am_is_bound = 0; 1290 return 0; 1291 } 1292 1293 static bool 1294 agp_i810_resume(device_t dv, const pmf_qual_t *qual) 1295 { 1296 struct agp_softc *sc = device_private(dv); 1297 struct agp_i810_softc *isc = sc->as_chipc; 1298 1299 /* 1300 * XXX Nothing uses isc->pgtblctl! Save on suspend, restore on 1301 * resume? 1302 */ 1303 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 1304 agp_flush_cache(); 1305 1306 return true; 1307 } 1308
Indexes created Wed Sep 24 05:09:52 GMT 2025