agp_i810.c revision 1.80
1 /* $NetBSD: agp_i810.c,v 1.80 2014/05/27 12:51:04 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.80 2014/05/27 12:51:04 riastradh Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/proc.h> 40 #include <sys/device.h> 41 #include <sys/conf.h> 42 #include <sys/xcall.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcidevs.h> 47 #include <dev/pci/agpvar.h> 48 #include <dev/pci/agpreg.h> 49 #include <dev/pci/agp_i810var.h> 50 51 #include <sys/agpio.h> 52 53 #include <sys/bus.h> 54 55 #include "agp_intel.h" 56 57 struct agp_softc *agp_i810_sc = NULL; 58 59 #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off) 60 #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off) 61 #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v) 62 63 #define CHIP_I810 0 /* i810/i815 */ 64 #define CHIP_I830 1 /* 830M/845G */ 65 #define CHIP_I855 2 /* 852GM/855GM/865G */ 66 #define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */ 67 #define CHIP_I965 4 /* 965Q/965PM */ 68 #define CHIP_G33 5 /* G33/Q33/Q35 */ 69 #define CHIP_G4X 6 /* G45/Q45 */ 70 71 /* XXX hack, see below */ 72 static bus_addr_t agp_i810_vga_regbase; 73 static bus_space_handle_t agp_i810_vga_bsh; 74 75 static u_int32_t agp_i810_get_aperture(struct agp_softc *); 76 static int agp_i810_set_aperture(struct agp_softc *, u_int32_t); 77 static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t); 78 static int agp_i810_unbind_page(struct agp_softc *, off_t); 79 static void agp_i810_flush_tlb(struct agp_softc *); 80 static int agp_i810_enable(struct agp_softc *, u_int32_t mode); 81 static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int, 82 vsize_t); 83 static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *); 84 static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, off_t); 85 static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *); 86 87 static bool agp_i810_resume(device_t, const pmf_qual_t *); 88 static int agp_i810_init(struct agp_softc *); 89 90 static int agp_i810_setup_chipset_flush_page(struct agp_softc *); 91 static void agp_i810_teardown_chipset_flush_page(struct agp_softc *); 92 static int agp_i810_init(struct agp_softc *); 93 94 static struct agp_methods agp_i810_methods = { 95 agp_i810_get_aperture, 96 agp_i810_set_aperture, 97 agp_i810_bind_page, 98 agp_i810_unbind_page, 99 agp_i810_flush_tlb, 100 agp_i810_enable, 101 agp_i810_alloc_memory, 102 agp_i810_free_memory, 103 agp_i810_bind_memory, 104 agp_i810_unbind_memory, 105 }; 106 107 int 108 agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, bus_addr_t v) 109 { 110 u_int32_t pte; 111 112 /* Bits 11:4 (physical start address extension) should be zero. */ 113 if ((v & 0xff0) != 0) 114 return EINVAL; 115 116 pte = (u_int32_t)v; 117 /* 118 * We need to massage the pte if bus_addr_t is wider than 32 bits. 119 * The compiler isn't smart enough, hence the casts to uintmax_t. 120 */ 121 if (sizeof(bus_addr_t) > sizeof(u_int32_t)) { 122 /* 965+ can do 36-bit addressing, add in the extra bits. */ 123 if (isc->chiptype == CHIP_I965 || 124 isc->chiptype == CHIP_G33 || 125 isc->chiptype == CHIP_G4X) { 126 if (((uintmax_t)v >> 36) != 0) 127 return EINVAL; 128 pte |= (v >> 28) & 0xf0; 129 } else { 130 if (((uintmax_t)v >> 32) != 0) 131 return EINVAL; 132 } 133 } 134 135 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, 136 4*(off >> AGP_PAGE_SHIFT), pte); 137 138 return 0; 139 } 140 141 void 142 agp_i810_post_gtt_entry(struct agp_i810_softc *isc, off_t off) 143 { 144 145 (void)bus_space_read_4(isc->gtt_bst, isc->gtt_bsh, 146 4*(off >> AGP_PAGE_SHIFT)); 147 } 148 149 static void 150 agp_flush_cache_xc(void *a __unused, void *b __unused) 151 { 152 153 agp_flush_cache(); 154 } 155 156 void 157 agp_i810_chipset_flush(struct agp_i810_softc *isc) 158 { 159 unsigned int timo = 20000; /* * 50 us = 1 s */ 160 161 switch (isc->chiptype) { 162 case CHIP_I810: 163 break; 164 case CHIP_I830: 165 case CHIP_I855: 166 /* 167 * Flush all CPU caches. If we're cold, we can't run 168 * xcalls, but there should be only one CPU up, so 169 * flushing only the local CPU's cache should suffice. 170 * 171 * XXX Come to think of it, do these chipsets appear in 172 * any multi-CPU systems? 173 */ 174 if (cold) 175 agp_flush_cache(); 176 else 177 xc_wait(xc_broadcast(0, &agp_flush_cache_xc, 178 NULL, NULL)); 179 WRITE4(AGP_I830_HIC, READ4(AGP_I830_HIC) | __BIT(31)); 180 while (ISSET(READ4(AGP_I830_HIC), __BIT(31))) { 181 if (timo-- == 0) 182 break; 183 DELAY(50); 184 } 185 break; 186 case CHIP_I915: 187 case CHIP_I965: 188 case CHIP_G33: 189 case CHIP_G4X: 190 bus_space_write_4(isc->flush_bst, isc->flush_bsh, 0, 1); 191 break; 192 } 193 } 194 195 /* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */ 196 static int 197 agp_i810_vgamatch(const struct pci_attach_args *pa) 198 { 199 200 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 201 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 202 return (0); 203 204 switch (PCI_PRODUCT(pa->pa_id)) { 205 case PCI_PRODUCT_INTEL_82810_GC: 206 case PCI_PRODUCT_INTEL_82810_DC100_GC: 207 case PCI_PRODUCT_INTEL_82810E_GC: 208 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 209 case PCI_PRODUCT_INTEL_82830MP_IV: 210 case PCI_PRODUCT_INTEL_82845G_IGD: 211 case PCI_PRODUCT_INTEL_82855GM_IGD: 212 case PCI_PRODUCT_INTEL_82865_IGD: 213 case PCI_PRODUCT_INTEL_82915G_IGD: 214 case PCI_PRODUCT_INTEL_82915GM_IGD: 215 case PCI_PRODUCT_INTEL_82945P_IGD: 216 case PCI_PRODUCT_INTEL_82945GM_IGD: 217 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 218 case PCI_PRODUCT_INTEL_82945GME_IGD: 219 case PCI_PRODUCT_INTEL_E7221_IGD: 220 case PCI_PRODUCT_INTEL_82965Q_IGD: 221 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 222 case PCI_PRODUCT_INTEL_82965PM_IGD: 223 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 224 case PCI_PRODUCT_INTEL_82G33_IGD: 225 case PCI_PRODUCT_INTEL_82G33_IGD_1: 226 case PCI_PRODUCT_INTEL_82965G_IGD: 227 case PCI_PRODUCT_INTEL_82965G_IGD_1: 228 case PCI_PRODUCT_INTEL_82965GME_IGD: 229 case PCI_PRODUCT_INTEL_82Q35_IGD: 230 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 231 case PCI_PRODUCT_INTEL_82Q33_IGD: 232 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 233 case PCI_PRODUCT_INTEL_82G35_IGD: 234 case PCI_PRODUCT_INTEL_82G35_IGD_1: 235 case PCI_PRODUCT_INTEL_82946GZ_IGD: 236 case PCI_PRODUCT_INTEL_82GM45_IGD: 237 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 238 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 239 case PCI_PRODUCT_INTEL_82Q45_IGD: 240 case PCI_PRODUCT_INTEL_82G45_IGD: 241 case PCI_PRODUCT_INTEL_82G41_IGD: 242 case PCI_PRODUCT_INTEL_82B43_IGD: 243 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 244 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 245 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 246 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 247 return (1); 248 } 249 250 return (0); 251 } 252 253 static int 254 agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg) 255 { 256 /* 257 * Find the aperture. Don't map it (yet), this would 258 * eat KVA. 259 */ 260 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 261 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize, 262 &sc->as_apflags) != 0) 263 return ENXIO; 264 265 sc->as_apt = pa->pa_memt; 266 267 return 0; 268 } 269 270 int 271 agp_i810_attach(device_t parent, device_t self, void *aux) 272 { 273 struct agp_softc *sc = device_private(self); 274 struct agp_i810_softc *isc; 275 struct agp_gatt *gatt; 276 int apbase, mmadr_bar, gtt_bar; 277 int mmadr_type, mmadr_flags; 278 bus_addr_t mmadr, gtt_off; 279 bus_size_t mmadr_size; 280 int error; 281 282 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 283 if (isc == NULL) { 284 aprint_error(": can't allocate chipset-specific softc\n"); 285 error = ENOMEM; 286 goto fail0; 287 } 288 sc->as_chipc = isc; 289 sc->as_methods = &agp_i810_methods; 290 291 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) { 292 #if NAGP_INTEL > 0 293 const struct pci_attach_args *pa = aux; 294 295 switch (PCI_PRODUCT(pa->pa_id)) { 296 case PCI_PRODUCT_INTEL_82840_HB: 297 case PCI_PRODUCT_INTEL_82865_HB: 298 case PCI_PRODUCT_INTEL_82845G_DRAM: 299 case PCI_PRODUCT_INTEL_82815_FULL_HUB: 300 case PCI_PRODUCT_INTEL_82855GM_MCH: 301 free(isc, M_AGP); 302 return agp_intel_attach(parent, self, aux); 303 } 304 #endif 305 aprint_error(": can't find internal VGA device config space\n"); 306 error = ENOENT; 307 goto fail1; 308 } 309 310 /* XXXfvdl */ 311 sc->as_dmat = isc->vga_pa.pa_dmat; 312 313 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 314 case PCI_PRODUCT_INTEL_82810_GC: 315 case PCI_PRODUCT_INTEL_82810_DC100_GC: 316 case PCI_PRODUCT_INTEL_82810E_GC: 317 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 318 isc->chiptype = CHIP_I810; 319 break; 320 case PCI_PRODUCT_INTEL_82830MP_IV: 321 case PCI_PRODUCT_INTEL_82845G_IGD: 322 isc->chiptype = CHIP_I830; 323 break; 324 case PCI_PRODUCT_INTEL_82855GM_IGD: 325 case PCI_PRODUCT_INTEL_82865_IGD: 326 isc->chiptype = CHIP_I855; 327 break; 328 case PCI_PRODUCT_INTEL_82915G_IGD: 329 case PCI_PRODUCT_INTEL_82915GM_IGD: 330 case PCI_PRODUCT_INTEL_82945P_IGD: 331 case PCI_PRODUCT_INTEL_82945GM_IGD: 332 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 333 case PCI_PRODUCT_INTEL_82945GME_IGD: 334 case PCI_PRODUCT_INTEL_E7221_IGD: 335 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 336 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 337 isc->chiptype = CHIP_I915; 338 break; 339 case PCI_PRODUCT_INTEL_82965Q_IGD: 340 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 341 case PCI_PRODUCT_INTEL_82965PM_IGD: 342 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 343 case PCI_PRODUCT_INTEL_82965G_IGD: 344 case PCI_PRODUCT_INTEL_82965G_IGD_1: 345 case PCI_PRODUCT_INTEL_82965GME_IGD: 346 case PCI_PRODUCT_INTEL_82946GZ_IGD: 347 case PCI_PRODUCT_INTEL_82G35_IGD: 348 case PCI_PRODUCT_INTEL_82G35_IGD_1: 349 isc->chiptype = CHIP_I965; 350 break; 351 case PCI_PRODUCT_INTEL_82Q35_IGD: 352 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 353 case PCI_PRODUCT_INTEL_82G33_IGD: 354 case PCI_PRODUCT_INTEL_82G33_IGD_1: 355 case PCI_PRODUCT_INTEL_82Q33_IGD: 356 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 357 isc->chiptype = CHIP_G33; 358 break; 359 case PCI_PRODUCT_INTEL_82GM45_IGD: 360 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 361 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 362 case PCI_PRODUCT_INTEL_82Q45_IGD: 363 case PCI_PRODUCT_INTEL_82G45_IGD: 364 case PCI_PRODUCT_INTEL_82G41_IGD: 365 case PCI_PRODUCT_INTEL_82B43_IGD: 366 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 367 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 368 isc->chiptype = CHIP_G4X; 369 break; 370 } 371 372 mmadr_type = PCI_MAPREG_TYPE_MEM; 373 switch (isc->chiptype) { 374 case CHIP_I915: 375 case CHIP_G33: 376 apbase = AGP_I915_GMADR; 377 mmadr_bar = AGP_I915_MMADR; 378 gtt_bar = AGP_I915_GTTADR; 379 gtt_off = ~(bus_addr_t)0; /* XXXGCC */ 380 break; 381 case CHIP_I965: 382 apbase = AGP_I965_GMADR; 383 mmadr_bar = AGP_I965_MMADR; 384 mmadr_type |= PCI_MAPREG_MEM_TYPE_64BIT; 385 gtt_bar = 0; 386 gtt_off = AGP_I965_GTT; 387 break; 388 case CHIP_G4X: 389 apbase = AGP_I965_GMADR; 390 mmadr_bar = AGP_I965_MMADR; 391 mmadr_type |= PCI_MAPREG_MEM_TYPE_64BIT; 392 gtt_bar = 0; 393 gtt_off = AGP_G4X_GTT; 394 break; 395 default: 396 apbase = AGP_I810_GMADR; 397 mmadr_bar = AGP_I810_MMADR; 398 gtt_bar = 0; 399 gtt_off = AGP_I810_GTT; 400 break; 401 } 402 403 /* Map (or, rather, find the address and size of) the aperture. */ 404 if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) 405 error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase); 406 else 407 error = agp_map_aperture(&isc->vga_pa, sc, apbase); 408 if (error) { 409 aprint_error(": can't map aperture\n"); 410 goto fail1; 411 } 412 413 /* Map the memory-mapped I/O registers, or the non-GTT part. */ 414 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, mmadr_bar, 415 mmadr_type, &mmadr, &mmadr_size, &mmadr_flags)) { 416 aprint_error_dev(self, "can't find MMIO registers\n"); 417 error = ENXIO; 418 goto fail1; 419 } 420 if (gtt_bar == 0) { 421 if (mmadr_size < gtt_off) { 422 aprint_error_dev(self, "MMIO registers too small" 423 ": %"PRIuMAX" < %"PRIuMAX"\n", 424 (uintmax_t)mmadr_size, (uintmax_t)gtt_off); 425 error = ENXIO; 426 goto fail1; 427 } 428 isc->size = gtt_off; 429 } else { 430 isc->size = mmadr_size; 431 } 432 isc->bst = isc->vga_pa.pa_memt; 433 error = bus_space_map(isc->bst, mmadr, isc->size, mmadr_flags, 434 &isc->bsh); 435 if (error) { 436 aprint_error_dev(self, "can't map MMIO registers: %d\n", 437 error); 438 error = ENXIO; 439 goto fail1; 440 } 441 442 /* Map the GTT, from either part of the MMIO region or its own BAR. */ 443 if (gtt_bar == 0) { 444 isc->gtt_bst = isc->bst; 445 isc->gtt_size = (mmadr_size - gtt_off); 446 error = bus_space_map(isc->gtt_bst, gtt_off, isc->gtt_size, 447 mmadr_flags, &isc->gtt_bsh); 448 if (error) { 449 aprint_error_dev(self, "can't map GTT: %d\n", error); 450 error = ENXIO; 451 goto fail2; 452 } 453 } else { 454 /* 455 * All chipsets with a separate BAR for the GTT, namely 456 * the i915 and G33 families, have 32-bit GTT BARs. 457 * 458 * XXX [citation needed] 459 */ 460 if (pci_mapreg_map(&isc->vga_pa, gtt_bar, PCI_MAPREG_TYPE_MEM, 461 0, 462 &isc->gtt_bst, &isc->gtt_bsh, NULL, &isc->gtt_size)) { 463 aprint_error_dev(self, "can't map GTT\n"); 464 error = ENXIO; 465 goto fail2; 466 } 467 } 468 469 /* Set up a chipset flush page if necessary. */ 470 switch (isc->chiptype) { 471 case CHIP_I915: 472 case CHIP_I965: 473 case CHIP_G33: 474 case CHIP_G4X: 475 error = agp_i810_setup_chipset_flush_page(sc); 476 if (error) { 477 aprint_error_dev(self, 478 "failed to set up chipset flush page: %d\n", 479 error); 480 goto fail3; 481 } 482 break; 483 } 484 485 /* Set up the generic AGP GATT record. */ 486 isc->initial_aperture = AGP_GET_APERTURE(sc); 487 gatt = malloc(sizeof(struct agp_gatt), M_AGP, M_NOWAIT); 488 if (!gatt) { 489 error = ENOMEM; 490 goto fail4; 491 } 492 isc->gatt = gatt; 493 gatt->ag_entries = AGP_GET_APERTURE(sc) >> AGP_PAGE_SHIFT; 494 495 /* Power management. (XXX Nothing to save on suspend? Fishy...) */ 496 if (!pmf_device_register(self, NULL, agp_i810_resume)) 497 aprint_error_dev(self, "couldn't establish power handler\n"); 498 499 /* 500 * XXX horrible hack to allow drm code to use our mapping 501 * of VGA chip registers 502 */ 503 agp_i810_vga_regbase = mmadr; 504 agp_i810_vga_bsh = isc->bsh; 505 506 /* Initialize the chipset. */ 507 error = agp_i810_init(sc); 508 if (error) 509 goto fail5; 510 511 /* Success! */ 512 return 0; 513 514 #if notyet 515 fail6: __unused 516 agp_i810_fini(sc); 517 #endif 518 fail5: pmf_device_deregister(self); 519 free(gatt, M_AGP); 520 isc->gatt = NULL; 521 fail4: switch (isc->chiptype) { 522 case CHIP_I915: 523 case CHIP_I965: 524 case CHIP_G33: 525 case CHIP_G4X: 526 agp_i810_teardown_chipset_flush_page(sc); 527 break; 528 } 529 fail3: bus_space_unmap(isc->gtt_bst, isc->gtt_bsh, isc->gtt_size); 530 isc->gtt_size = 0; 531 fail2: bus_space_unmap(isc->bst, isc->bsh, isc->size); 532 isc->size = 0; 533 fail1: free(isc, M_AGP); 534 sc->as_chipc = NULL; 535 fail0: agp_generic_detach(sc); 536 KASSERT(error); 537 return error; 538 } 539 540 static int 541 agp_i810_setup_chipset_flush_page(struct agp_softc *sc) 542 { 543 struct agp_i810_softc *const isc = sc->as_chipc; 544 pcireg_t reg, lo, hi; 545 bus_addr_t addr, minaddr, maxaddr; 546 int error; 547 548 /* We always use memory-mapped I/O. */ 549 isc->flush_bst = isc->vga_pa.pa_memt; 550 551 /* No page allocated yet. */ 552 isc->flush_addr = 0; 553 554 /* Read the PCI config register: 4-byte on gen3, 8-byte on gen>=4. */ 555 if (isc->chiptype == CHIP_I915) { 556 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR); 557 addr = reg; 558 minaddr = PAGE_SIZE; /* XXX PCIBIOS_MIN_MEM? */ 559 maxaddr = UINT32_MAX; 560 } else { 561 hi = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I965_IFPADDR+4); 562 lo = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I965_IFPADDR); 563 /* 564 * Convert to uint64_t, rather than bus_addr_t which 565 * may be 32-bit, to avoid undefined behaviour with a 566 * too-wide shift. Since the BIOS doesn't know whether 567 * the OS will run 64-bit or with PAE, it ought to 568 * configure at most a 32-bit physical address, so 569 * let's print a warning in case that happens. 570 */ 571 addr = ((uint64_t)hi << 32) | lo; 572 if (hi) { 573 aprint_error_dev(sc->as_dev, 574 "BIOS configured >32-bit flush page address" 575 ": %"PRIx64"\n", ((uint64_t)hi << 32) | lo); 576 #if __i386__ && !PAE 577 return EIO; 578 #endif 579 } 580 minaddr = PAGE_SIZE; /* XXX PCIBIOS_MIN_MEM? */ 581 maxaddr = MIN(UINT64_MAX, ~(bus_addr_t)0); 582 } 583 584 /* Allocate or map a pre-allocated a page for it. */ 585 if (ISSET(addr, 1)) { 586 /* BIOS allocated it for us. Use that. */ 587 error = bus_space_map(isc->flush_bst, addr & ~1, PAGE_SIZE, 0, 588 &isc->flush_bsh); 589 if (error) 590 return error; 591 } else { 592 /* None allocated. Allocate one. */ 593 error = bus_space_alloc(isc->flush_bst, minaddr, maxaddr, 594 PAGE_SIZE, PAGE_SIZE, 0, 0, 595 &isc->flush_addr, &isc->flush_bsh); 596 if (error) 597 return error; 598 KASSERT(isc->flush_addr != 0); 599 /* Write it into the PCI config register. */ 600 addr = isc->flush_addr | 1; 601 if (isc->chiptype == CHIP_I915) { 602 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR, 603 addr); 604 } else { 605 pci_conf_write(sc->as_pc, sc->as_tag, 606 AGP_I965_IFPADDR + 4, 607 __SHIFTOUT(addr, __BITS(63, 32))); 608 pci_conf_write(sc->as_pc, sc->as_tag, 609 AGP_I965_IFPADDR, 610 __SHIFTOUT(addr, __BITS(31, 0))); 611 } 612 } 613 614 /* Success! */ 615 return 0; 616 } 617 618 static void 619 agp_i810_teardown_chipset_flush_page(struct agp_softc *sc) 620 { 621 struct agp_i810_softc *const isc = sc->as_chipc; 622 623 if (isc->flush_addr) { 624 /* If we allocated a page, clear it. */ 625 if (isc->chiptype == CHIP_I915) { 626 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR, 627 0); 628 } else { 629 pci_conf_write(sc->as_pc, sc->as_tag, 630 AGP_I965_IFPADDR, 0); 631 pci_conf_write(sc->as_pc, sc->as_tag, 632 AGP_I965_IFPADDR + 4, 0); 633 } 634 isc->flush_addr = 0; 635 bus_space_free(isc->flush_bst, isc->flush_bsh, 636 PAGE_SIZE); 637 } else { 638 /* Otherwise, just unmap the pre-allocated page. */ 639 bus_space_unmap(isc->flush_bst, isc->flush_bsh, PAGE_SIZE); 640 } 641 } 642 643 /* 644 * XXX horrible hack to allow drm code to use our mapping 645 * of VGA chip registers 646 */ 647 int 648 agp_i810_borrow(bus_addr_t base, bus_space_handle_t *hdlp) 649 { 650 651 if (!agp_i810_vga_regbase || base != agp_i810_vga_regbase) 652 return 0; 653 *hdlp = agp_i810_vga_bsh; 654 return 1; 655 } 656 657 static int agp_i810_init(struct agp_softc *sc) 658 { 659 struct agp_i810_softc *isc; 660 struct agp_gatt *gatt; 661 662 isc = sc->as_chipc; 663 gatt = isc->gatt; 664 665 if (isc->chiptype == CHIP_I810) { 666 void *virtual; 667 int dummyseg; 668 669 /* Some i810s have on-chip memory called dcache */ 670 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 671 isc->dcache_size = 4 * 1024 * 1024; 672 else 673 isc->dcache_size = 0; 674 675 /* According to the specs the gatt on the i810 must be 64k */ 676 if (agp_alloc_dmamem(sc->as_dmat, 64 * 1024, 677 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical, 678 &gatt->ag_dmaseg, 1, &dummyseg) != 0) { 679 free(gatt, M_AGP); 680 agp_generic_detach(sc); 681 return ENOMEM; 682 } 683 gatt->ag_virtual = (uint32_t *)virtual; 684 gatt->ag_size = gatt->ag_entries * sizeof(u_int32_t); 685 memset(gatt->ag_virtual, 0, gatt->ag_size); 686 687 agp_flush_cache(); 688 /* Install the GATT. */ 689 WRITE4(AGP_I810_PGTBL_CTL, gatt->ag_physical | 1); 690 } else if (isc->chiptype == CHIP_I830) { 691 /* The i830 automatically initializes the 128k gatt on boot. */ 692 pcireg_t reg; 693 u_int32_t pgtblctl; 694 u_int16_t gcc1; 695 696 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 697 gcc1 = (u_int16_t)(reg >> 16); 698 switch (gcc1 & AGP_I830_GCC1_GMS) { 699 case AGP_I830_GCC1_GMS_STOLEN_512: 700 isc->stolen = (512 - 132) * 1024 / 4096; 701 break; 702 case AGP_I830_GCC1_GMS_STOLEN_1024: 703 isc->stolen = (1024 - 132) * 1024 / 4096; 704 break; 705 case AGP_I830_GCC1_GMS_STOLEN_8192: 706 isc->stolen = (8192 - 132) * 1024 / 4096; 707 break; 708 default: 709 isc->stolen = 0; 710 aprint_error( 711 ": unknown memory configuration, disabling\n"); 712 agp_generic_detach(sc); 713 return EINVAL; 714 } 715 716 if (isc->stolen > 0) { 717 aprint_normal(": detected %dk stolen memory\n%s", 718 isc->stolen * 4, device_xname(sc->as_dev)); 719 } 720 721 /* GATT address is already in there, make sure it's enabled */ 722 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 723 pgtblctl |= 1; 724 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 725 726 gatt->ag_physical = pgtblctl & ~1; 727 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 728 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 || 729 isc->chiptype == CHIP_G4X) { 730 pcireg_t reg; 731 u_int32_t pgtblctl, gtt_size, stolen; 732 u_int16_t gcc1; 733 734 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1); 735 gcc1 = (u_int16_t)(reg >> 16); 736 737 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 738 739 /* Stolen memory is set up at the beginning of the aperture by 740 * the BIOS, consisting of the GATT followed by 4kb for the 741 * BIOS display. 742 */ 743 switch (isc->chiptype) { 744 case CHIP_I855: 745 gtt_size = 128; 746 break; 747 case CHIP_I915: 748 gtt_size = 256; 749 break; 750 case CHIP_I965: 751 switch (pgtblctl & AGP_I810_PGTBL_SIZE_MASK) { 752 case AGP_I810_PGTBL_SIZE_128KB: 753 case AGP_I810_PGTBL_SIZE_512KB: 754 gtt_size = 512; 755 break; 756 case AGP_I965_PGTBL_SIZE_1MB: 757 gtt_size = 1024; 758 break; 759 case AGP_I965_PGTBL_SIZE_2MB: 760 gtt_size = 2048; 761 break; 762 case AGP_I965_PGTBL_SIZE_1_5MB: 763 gtt_size = 1024 + 512; 764 break; 765 default: 766 aprint_error("Bad PGTBL size\n"); 767 agp_generic_detach(sc); 768 return EINVAL; 769 } 770 break; 771 case CHIP_G33: 772 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 773 case AGP_G33_PGTBL_SIZE_1M: 774 gtt_size = 1024; 775 break; 776 case AGP_G33_PGTBL_SIZE_2M: 777 gtt_size = 2048; 778 break; 779 default: 780 aprint_error(": Bad PGTBL size\n"); 781 agp_generic_detach(sc); 782 return EINVAL; 783 } 784 break; 785 case CHIP_G4X: 786 gtt_size = 0; 787 break; 788 default: 789 aprint_error(": bad chiptype\n"); 790 agp_generic_detach(sc); 791 return EINVAL; 792 } 793 794 switch (gcc1 & AGP_I855_GCC1_GMS) { 795 case AGP_I855_GCC1_GMS_STOLEN_1M: 796 stolen = 1024; 797 break; 798 case AGP_I855_GCC1_GMS_STOLEN_4M: 799 stolen = 4 * 1024; 800 break; 801 case AGP_I855_GCC1_GMS_STOLEN_8M: 802 stolen = 8 * 1024; 803 break; 804 case AGP_I855_GCC1_GMS_STOLEN_16M: 805 stolen = 16 * 1024; 806 break; 807 case AGP_I855_GCC1_GMS_STOLEN_32M: 808 stolen = 32 * 1024; 809 break; 810 case AGP_I915_GCC1_GMS_STOLEN_48M: 811 stolen = 48 * 1024; 812 break; 813 case AGP_I915_GCC1_GMS_STOLEN_64M: 814 stolen = 64 * 1024; 815 break; 816 case AGP_G33_GCC1_GMS_STOLEN_128M: 817 stolen = 128 * 1024; 818 break; 819 case AGP_G33_GCC1_GMS_STOLEN_256M: 820 stolen = 256 * 1024; 821 break; 822 case AGP_G4X_GCC1_GMS_STOLEN_96M: 823 stolen = 96 * 1024; 824 break; 825 case AGP_G4X_GCC1_GMS_STOLEN_160M: 826 stolen = 160 * 1024; 827 break; 828 case AGP_G4X_GCC1_GMS_STOLEN_224M: 829 stolen = 224 * 1024; 830 break; 831 case AGP_G4X_GCC1_GMS_STOLEN_352M: 832 stolen = 352 * 1024; 833 break; 834 default: 835 aprint_error( 836 ": unknown memory configuration, disabling\n"); 837 agp_generic_detach(sc); 838 return EINVAL; 839 } 840 841 switch (gcc1 & AGP_I855_GCC1_GMS) { 842 case AGP_I915_GCC1_GMS_STOLEN_48M: 843 case AGP_I915_GCC1_GMS_STOLEN_64M: 844 if (isc->chiptype != CHIP_I915 && 845 isc->chiptype != CHIP_I965 && 846 isc->chiptype != CHIP_G33 && 847 isc->chiptype != CHIP_G4X) 848 stolen = 0; 849 break; 850 case AGP_G33_GCC1_GMS_STOLEN_128M: 851 case AGP_G33_GCC1_GMS_STOLEN_256M: 852 if (isc->chiptype != CHIP_I965 && 853 isc->chiptype != CHIP_G33 && 854 isc->chiptype != CHIP_G4X) 855 stolen = 0; 856 break; 857 case AGP_G4X_GCC1_GMS_STOLEN_96M: 858 case AGP_G4X_GCC1_GMS_STOLEN_160M: 859 case AGP_G4X_GCC1_GMS_STOLEN_224M: 860 case AGP_G4X_GCC1_GMS_STOLEN_352M: 861 if (isc->chiptype != CHIP_I965 && 862 isc->chiptype != CHIP_G4X) 863 stolen = 0; 864 break; 865 } 866 867 /* BIOS space */ 868 gtt_size += 4; 869 870 isc->stolen = (stolen - gtt_size) * 1024 / 4096; 871 872 if (isc->stolen > 0) { 873 aprint_normal(": detected %dk stolen memory\n%s", 874 isc->stolen * 4, device_xname(sc->as_dev)); 875 } 876 877 /* GATT address is already in there, make sure it's enabled */ 878 pgtblctl |= 1; 879 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 880 881 gatt->ag_physical = pgtblctl & ~1; 882 } 883 884 /* 885 * Make sure the chipset can see everything. 886 */ 887 agp_flush_cache(); 888 889 /* 890 * Publish what we found for kludgey drivers (I'm looking at 891 * you, drm). 892 */ 893 if (agp_i810_sc == NULL) 894 agp_i810_sc = sc; 895 else 896 aprint_error_dev(sc->as_dev, "i810 agp already attached\n"); 897 898 return 0; 899 } 900 901 #if 0 902 static int 903 agp_i810_detach(struct agp_softc *sc) 904 { 905 int error; 906 struct agp_i810_softc *isc = sc->as_chipc; 907 908 error = agp_generic_detach(sc); 909 if (error) 910 return error; 911 912 switch (isc->chiptype) { 913 case CHIP_I915: 914 case CHIP_I965: 915 case CHIP_G33: 916 case CHIP_G4X: 917 agp_i810_teardown_chipset_flush_page(sc); 918 break; 919 } 920 921 /* Clear the GATT base. */ 922 if (sc->chiptype == CHIP_I810) { 923 WRITE4(AGP_I810_PGTBL_CTL, 0); 924 } else { 925 unsigned int pgtblctl; 926 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 927 pgtblctl &= ~1; 928 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 929 } 930 931 /* Put the aperture back the way it started. */ 932 AGP_SET_APERTURE(sc, isc->initial_aperture); 933 934 if (sc->chiptype == CHIP_I810) { 935 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap, 936 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 937 } 938 free(sc->gatt, M_AGP); 939 940 return 0; 941 } 942 #endif 943 944 static u_int32_t 945 agp_i810_get_aperture(struct agp_softc *sc) 946 { 947 struct agp_i810_softc *isc = sc->as_chipc; 948 pcireg_t reg; 949 u_int32_t size; 950 u_int16_t miscc, gcc1, msac; 951 952 size = 0; 953 954 switch (isc->chiptype) { 955 case CHIP_I810: 956 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 957 miscc = (u_int16_t)(reg >> 16); 958 if ((miscc & AGP_I810_MISCC_WINSIZE) == 959 AGP_I810_MISCC_WINSIZE_32) 960 size = 32 * 1024 * 1024; 961 else 962 size = 64 * 1024 * 1024; 963 break; 964 case CHIP_I830: 965 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 966 gcc1 = (u_int16_t)(reg >> 16); 967 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 968 size = 64 * 1024 * 1024; 969 else 970 size = 128 * 1024 * 1024; 971 break; 972 case CHIP_I855: 973 size = 128 * 1024 * 1024; 974 break; 975 case CHIP_I915: 976 case CHIP_G33: 977 case CHIP_G4X: 978 reg = pci_conf_read(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, 979 AGP_I915_MSAC); 980 msac = (u_int16_t)(reg >> 16); 981 if (msac & AGP_I915_MSAC_APER_128M) 982 size = 128 * 1024 * 1024; 983 else 984 size = 256 * 1024 * 1024; 985 break; 986 case CHIP_I965: 987 size = 512 * 1024 * 1024; 988 break; 989 default: 990 aprint_error(": Unknown chipset\n"); 991 } 992 993 return size; 994 } 995 996 static int 997 agp_i810_set_aperture(struct agp_softc *sc, u_int32_t aperture) 998 { 999 struct agp_i810_softc *isc = sc->as_chipc; 1000 pcireg_t reg; 1001 u_int16_t miscc, gcc1; 1002 1003 switch (isc->chiptype) { 1004 case CHIP_I810: 1005 /* 1006 * Double check for sanity. 1007 */ 1008 if (aperture != (32 * 1024 * 1024) && 1009 aperture != (64 * 1024 * 1024)) { 1010 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 1011 aperture); 1012 return EINVAL; 1013 } 1014 1015 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 1016 miscc = (u_int16_t)(reg >> 16); 1017 miscc &= ~AGP_I810_MISCC_WINSIZE; 1018 if (aperture == 32 * 1024 * 1024) 1019 miscc |= AGP_I810_MISCC_WINSIZE_32; 1020 else 1021 miscc |= AGP_I810_MISCC_WINSIZE_64; 1022 1023 reg &= 0x0000ffff; 1024 reg |= ((pcireg_t)miscc) << 16; 1025 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I810_SMRAM, reg); 1026 break; 1027 case CHIP_I830: 1028 if (aperture != (64 * 1024 * 1024) && 1029 aperture != (128 * 1024 * 1024)) { 1030 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 1031 aperture); 1032 return EINVAL; 1033 } 1034 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 1035 gcc1 = (u_int16_t)(reg >> 16); 1036 gcc1 &= ~AGP_I830_GCC1_GMASIZE; 1037 if (aperture == 64 * 1024 * 1024) 1038 gcc1 |= AGP_I830_GCC1_GMASIZE_64; 1039 else 1040 gcc1 |= AGP_I830_GCC1_GMASIZE_128; 1041 1042 reg &= 0x0000ffff; 1043 reg |= ((pcireg_t)gcc1) << 16; 1044 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I830_GCC0, reg); 1045 break; 1046 case CHIP_I855: 1047 case CHIP_I915: 1048 if (aperture != agp_i810_get_aperture(sc)) { 1049 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 1050 aperture); 1051 return EINVAL; 1052 } 1053 break; 1054 case CHIP_I965: 1055 if (aperture != 512 * 1024 * 1024) { 1056 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 1057 aperture); 1058 return EINVAL; 1059 } 1060 break; 1061 } 1062 1063 return 0; 1064 } 1065 1066 static int 1067 agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 1068 { 1069 struct agp_i810_softc *isc = sc->as_chipc; 1070 1071 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) { 1072 #ifdef AGP_DEBUG 1073 printf("%s: failed: offset 0x%08x, shift %d, entries %d\n", 1074 device_xname(sc->as_dev), (int)offset, AGP_PAGE_SHIFT, 1075 isc->gatt->ag_entries); 1076 #endif 1077 return EINVAL; 1078 } 1079 1080 if (isc->chiptype != CHIP_I810) { 1081 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1082 #ifdef AGP_DEBUG 1083 printf("%s: trying to bind into stolen memory\n", 1084 device_xname(sc->as_dev)); 1085 #endif 1086 return EINVAL; 1087 } 1088 } 1089 1090 return agp_i810_write_gtt_entry(isc, offset, physical | 1); 1091 } 1092 1093 static int 1094 agp_i810_unbind_page(struct agp_softc *sc, off_t offset) 1095 { 1096 struct agp_i810_softc *isc = sc->as_chipc; 1097 1098 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 1099 return EINVAL; 1100 1101 if (isc->chiptype != CHIP_I810 ) { 1102 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1103 #ifdef AGP_DEBUG 1104 printf("%s: trying to unbind from stolen memory\n", 1105 device_xname(sc->as_dev)); 1106 #endif 1107 return EINVAL; 1108 } 1109 } 1110 1111 return agp_i810_write_gtt_entry(isc, offset, 0); 1112 } 1113 1114 /* 1115 * Writing via memory mapped registers already flushes all TLBs. 1116 */ 1117 static void 1118 agp_i810_flush_tlb(struct agp_softc *sc) 1119 { 1120 } 1121 1122 static int 1123 agp_i810_enable(struct agp_softc *sc, u_int32_t mode) 1124 { 1125 1126 return 0; 1127 } 1128 1129 static struct agp_memory * 1130 agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size) 1131 { 1132 struct agp_i810_softc *isc = sc->as_chipc; 1133 struct agp_memory *mem; 1134 1135 #ifdef AGP_DEBUG 1136 printf("AGP: alloc(%d, 0x%x)\n", type, (int) size); 1137 #endif 1138 1139 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 1140 return 0; 1141 1142 if (sc->as_allocated + size > sc->as_maxmem) 1143 return 0; 1144 1145 if (type == 1) { 1146 /* 1147 * Mapping local DRAM into GATT. 1148 */ 1149 if (isc->chiptype != CHIP_I810 ) 1150 return 0; 1151 if (size != isc->dcache_size) 1152 return 0; 1153 } else if (type == 2) { 1154 /* 1155 * Bogus mapping for the hardware cursor. 1156 */ 1157 if (size != AGP_PAGE_SIZE && size != 4 * AGP_PAGE_SIZE) 1158 return 0; 1159 } 1160 1161 mem = malloc(sizeof *mem, M_AGP, M_WAITOK|M_ZERO); 1162 if (mem == NULL) 1163 return NULL; 1164 mem->am_id = sc->as_nextid++; 1165 mem->am_size = size; 1166 mem->am_type = type; 1167 1168 if (type == 2) { 1169 /* 1170 * Allocate and wire down the memory now so that we can 1171 * get its physical address. 1172 */ 1173 mem->am_dmaseg = malloc(sizeof *mem->am_dmaseg, M_AGP, 1174 M_WAITOK); 1175 if (mem->am_dmaseg == NULL) { 1176 free(mem, M_AGP); 1177 return NULL; 1178 } 1179 if (agp_alloc_dmamem(sc->as_dmat, size, 0, 1180 &mem->am_dmamap, &mem->am_virtual, &mem->am_physical, 1181 mem->am_dmaseg, 1, &mem->am_nseg) != 0) { 1182 free(mem->am_dmaseg, M_AGP); 1183 free(mem, M_AGP); 1184 return NULL; 1185 } 1186 memset(mem->am_virtual, 0, size); 1187 } else if (type != 1) { 1188 if (bus_dmamap_create(sc->as_dmat, size, size / PAGE_SIZE + 1, 1189 size, 0, BUS_DMA_NOWAIT, 1190 &mem->am_dmamap) != 0) { 1191 free(mem, M_AGP); 1192 return NULL; 1193 } 1194 } 1195 1196 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link); 1197 sc->as_allocated += size; 1198 1199 return mem; 1200 } 1201 1202 static int 1203 agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem) 1204 { 1205 if (mem->am_is_bound) 1206 return EBUSY; 1207 1208 if (mem->am_type == 2) { 1209 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap, 1210 mem->am_virtual, mem->am_dmaseg, mem->am_nseg); 1211 free(mem->am_dmaseg, M_AGP); 1212 } 1213 1214 sc->as_allocated -= mem->am_size; 1215 TAILQ_REMOVE(&sc->as_memory, mem, am_link); 1216 free(mem, M_AGP); 1217 return 0; 1218 } 1219 1220 static int 1221 agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem, 1222 off_t offset) 1223 { 1224 struct agp_i810_softc *isc = sc->as_chipc; 1225 u_int32_t regval, i; 1226 1227 if (mem->am_is_bound != 0) 1228 return EINVAL; 1229 1230 /* 1231 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 1232 * X server for mysterious reasons which leads to crashes if we write 1233 * to the GTT through the MMIO window. 1234 * Until the issue is solved, simply restore it. 1235 */ 1236 regval = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL); 1237 if (regval != (isc->gatt->ag_physical | 1)) { 1238 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%x - fixing\n", 1239 regval); 1240 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 1241 isc->gatt->ag_physical | 1); 1242 } 1243 1244 if (mem->am_type == 2) { 1245 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1246 agp_i810_bind_page(sc, offset + i, 1247 mem->am_physical + i); 1248 mem->am_offset = offset; 1249 mem->am_is_bound = 1; 1250 return 0; 1251 } 1252 1253 if (mem->am_type != 1) 1254 return agp_generic_bind_memory(sc, mem, offset); 1255 1256 if (isc->chiptype != CHIP_I810) 1257 return EINVAL; 1258 1259 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1260 agp_i810_write_gtt_entry(isc, i, i | 3); 1261 mem->am_is_bound = 1; 1262 return 0; 1263 } 1264 1265 static int 1266 agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem) 1267 { 1268 struct agp_i810_softc *isc = sc->as_chipc; 1269 u_int32_t i; 1270 1271 if (mem->am_is_bound == 0) 1272 return EINVAL; 1273 1274 if (mem->am_type == 2) { 1275 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1276 agp_i810_unbind_page(sc, mem->am_offset + i); 1277 mem->am_offset = 0; 1278 mem->am_is_bound = 0; 1279 return 0; 1280 } 1281 1282 if (mem->am_type != 1) 1283 return agp_generic_unbind_memory(sc, mem); 1284 1285 if (isc->chiptype != CHIP_I810) 1286 return EINVAL; 1287 1288 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1289 agp_i810_write_gtt_entry(isc, i, 0); 1290 mem->am_is_bound = 0; 1291 return 0; 1292 } 1293 1294 static bool 1295 agp_i810_resume(device_t dv, const pmf_qual_t *qual) 1296 { 1297 struct agp_softc *sc = device_private(dv); 1298 struct agp_i810_softc *isc = sc->as_chipc; 1299 1300 /* 1301 * XXX Nothing uses isc->pgtblctl! Save on suspend, restore on 1302 * resume? 1303 */ 1304 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 1305 agp_flush_cache(); 1306 1307 return true; 1308 } 1309
Indexes created Wed Sep 24 15:09:51 GMT 2025