agp_i810.c revision 1.83
1 /* $NetBSD: agp_i810.c,v 1.83 2014/05/28 15:34:32 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.83 2014/05/28 15:34:32 riastradh Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/proc.h> 40 #include <sys/device.h> 41 #include <sys/conf.h> 42 #include <sys/xcall.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcidevs.h> 47 #include <dev/pci/agpvar.h> 48 #include <dev/pci/agpreg.h> 49 #include <dev/pci/agp_i810var.h> 50 51 #include <sys/agpio.h> 52 53 #include <sys/bus.h> 54 55 #include "agp_intel.h" 56 57 struct agp_softc *agp_i810_sc = NULL; 58 59 #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off) 60 #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off) 61 #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v) 62 63 #define CHIP_I810 0 /* i810/i815 */ 64 #define CHIP_I830 1 /* 830M/845G */ 65 #define CHIP_I855 2 /* 852GM/855GM/865G */ 66 #define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */ 67 #define CHIP_I965 4 /* 965Q/965PM */ 68 #define CHIP_G33 5 /* G33/Q33/Q35 */ 69 #define CHIP_G4X 6 /* G45/Q45 */ 70 71 /* XXX hack, see below */ 72 static bus_addr_t agp_i810_vga_regbase; 73 static bus_space_handle_t agp_i810_vga_bsh; 74 75 static u_int32_t agp_i810_get_aperture(struct agp_softc *); 76 static int agp_i810_set_aperture(struct agp_softc *, u_int32_t); 77 static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t); 78 static int agp_i810_unbind_page(struct agp_softc *, off_t); 79 static void agp_i810_flush_tlb(struct agp_softc *); 80 static int agp_i810_enable(struct agp_softc *, u_int32_t mode); 81 static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int, 82 vsize_t); 83 static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *); 84 static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, off_t); 85 static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *); 86 87 static bool agp_i810_resume(device_t, const pmf_qual_t *); 88 static int agp_i810_init(struct agp_softc *); 89 90 static int agp_i810_setup_chipset_flush_page(struct agp_softc *); 91 static void agp_i810_teardown_chipset_flush_page(struct agp_softc *); 92 static int agp_i810_init(struct agp_softc *); 93 94 static struct agp_methods agp_i810_methods = { 95 agp_i810_get_aperture, 96 agp_i810_set_aperture, 97 agp_i810_bind_page, 98 agp_i810_unbind_page, 99 agp_i810_flush_tlb, 100 agp_i810_enable, 101 agp_i810_alloc_memory, 102 agp_i810_free_memory, 103 agp_i810_bind_memory, 104 agp_i810_unbind_memory, 105 }; 106 107 int 108 agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, bus_addr_t v) 109 { 110 u_int32_t pte; 111 112 /* Bits 11:4 (physical start address extension) should be zero. */ 113 if ((v & 0xff0) != 0) 114 return EINVAL; 115 116 pte = (u_int32_t)v; 117 /* 118 * We need to massage the pte if bus_addr_t is wider than 32 bits. 119 * The compiler isn't smart enough, hence the casts to uintmax_t. 120 */ 121 if (sizeof(bus_addr_t) > sizeof(u_int32_t)) { 122 /* 965+ can do 36-bit addressing, add in the extra bits. */ 123 if (isc->chiptype == CHIP_I965 || 124 isc->chiptype == CHIP_G33 || 125 isc->chiptype == CHIP_G4X) { 126 if (((uintmax_t)v >> 36) != 0) 127 return EINVAL; 128 pte |= (v >> 28) & 0xf0; 129 } else { 130 if (((uintmax_t)v >> 32) != 0) 131 return EINVAL; 132 } 133 } 134 135 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, 136 4*(off >> AGP_PAGE_SHIFT), pte); 137 138 return 0; 139 } 140 141 void 142 agp_i810_post_gtt_entry(struct agp_i810_softc *isc, off_t off) 143 { 144 145 (void)bus_space_read_4(isc->gtt_bst, isc->gtt_bsh, 146 4*(off >> AGP_PAGE_SHIFT)); 147 } 148 149 static void 150 agp_flush_cache_xc(void *a __unused, void *b __unused) 151 { 152 153 agp_flush_cache(); 154 } 155 156 void 157 agp_i810_chipset_flush(struct agp_i810_softc *isc) 158 { 159 unsigned int timo = 20000; /* * 50 us = 1 s */ 160 161 switch (isc->chiptype) { 162 case CHIP_I810: 163 break; 164 case CHIP_I830: 165 case CHIP_I855: 166 /* 167 * Flush all CPU caches. If we're cold, we can't run 168 * xcalls, but there should be only one CPU up, so 169 * flushing only the local CPU's cache should suffice. 170 * 171 * XXX Come to think of it, do these chipsets appear in 172 * any multi-CPU systems? 173 */ 174 if (cold) 175 agp_flush_cache(); 176 else 177 xc_wait(xc_broadcast(0, &agp_flush_cache_xc, 178 NULL, NULL)); 179 WRITE4(AGP_I830_HIC, READ4(AGP_I830_HIC) | __BIT(31)); 180 while (ISSET(READ4(AGP_I830_HIC), __BIT(31))) { 181 if (timo-- == 0) 182 break; 183 DELAY(50); 184 } 185 break; 186 case CHIP_I915: 187 case CHIP_I965: 188 case CHIP_G33: 189 case CHIP_G4X: 190 bus_space_write_4(isc->flush_bst, isc->flush_bsh, 0, 1); 191 break; 192 } 193 } 194 195 /* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */ 196 static int 197 agp_i810_vgamatch(const struct pci_attach_args *pa) 198 { 199 200 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 201 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 202 return (0); 203 204 switch (PCI_PRODUCT(pa->pa_id)) { 205 case PCI_PRODUCT_INTEL_82810_GC: 206 case PCI_PRODUCT_INTEL_82810_DC100_GC: 207 case PCI_PRODUCT_INTEL_82810E_GC: 208 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 209 case PCI_PRODUCT_INTEL_82830MP_IV: 210 case PCI_PRODUCT_INTEL_82845G_IGD: 211 case PCI_PRODUCT_INTEL_82855GM_IGD: 212 case PCI_PRODUCT_INTEL_82865_IGD: 213 case PCI_PRODUCT_INTEL_82915G_IGD: 214 case PCI_PRODUCT_INTEL_82915GM_IGD: 215 case PCI_PRODUCT_INTEL_82945P_IGD: 216 case PCI_PRODUCT_INTEL_82945GM_IGD: 217 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 218 case PCI_PRODUCT_INTEL_82945GME_IGD: 219 case PCI_PRODUCT_INTEL_E7221_IGD: 220 case PCI_PRODUCT_INTEL_82965Q_IGD: 221 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 222 case PCI_PRODUCT_INTEL_82965PM_IGD: 223 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 224 case PCI_PRODUCT_INTEL_82G33_IGD: 225 case PCI_PRODUCT_INTEL_82G33_IGD_1: 226 case PCI_PRODUCT_INTEL_82965G_IGD: 227 case PCI_PRODUCT_INTEL_82965G_IGD_1: 228 case PCI_PRODUCT_INTEL_82965GME_IGD: 229 case PCI_PRODUCT_INTEL_82Q35_IGD: 230 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 231 case PCI_PRODUCT_INTEL_82Q33_IGD: 232 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 233 case PCI_PRODUCT_INTEL_82G35_IGD: 234 case PCI_PRODUCT_INTEL_82G35_IGD_1: 235 case PCI_PRODUCT_INTEL_82946GZ_IGD: 236 case PCI_PRODUCT_INTEL_82GM45_IGD: 237 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 238 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 239 case PCI_PRODUCT_INTEL_82Q45_IGD: 240 case PCI_PRODUCT_INTEL_82G45_IGD: 241 case PCI_PRODUCT_INTEL_82G41_IGD: 242 case PCI_PRODUCT_INTEL_82B43_IGD: 243 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 244 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 245 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 246 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 247 return (1); 248 } 249 250 return (0); 251 } 252 253 static int 254 agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg) 255 { 256 /* 257 * Find the aperture. Don't map it (yet), this would 258 * eat KVA. 259 */ 260 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 261 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize, 262 &sc->as_apflags) != 0) 263 return ENXIO; 264 265 sc->as_apt = pa->pa_memt; 266 267 return 0; 268 } 269 270 int 271 agp_i810_attach(device_t parent, device_t self, void *aux) 272 { 273 struct agp_softc *sc = device_private(self); 274 struct agp_i810_softc *isc; 275 struct agp_gatt *gatt; 276 int apbase, mmadr_bar, gtt_bar; 277 int mmadr_type, mmadr_flags; 278 bus_addr_t mmadr, gtt_off; 279 bus_size_t mmadr_size; 280 int error; 281 282 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 283 if (isc == NULL) { 284 aprint_error(": can't allocate chipset-specific softc\n"); 285 error = ENOMEM; 286 goto fail0; 287 } 288 sc->as_chipc = isc; 289 sc->as_methods = &agp_i810_methods; 290 291 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) { 292 #if NAGP_INTEL > 0 293 const struct pci_attach_args *pa = aux; 294 295 switch (PCI_PRODUCT(pa->pa_id)) { 296 case PCI_PRODUCT_INTEL_82840_HB: 297 case PCI_PRODUCT_INTEL_82865_HB: 298 case PCI_PRODUCT_INTEL_82845G_DRAM: 299 case PCI_PRODUCT_INTEL_82815_FULL_HUB: 300 case PCI_PRODUCT_INTEL_82855GM_MCH: 301 free(isc, M_AGP); 302 return agp_intel_attach(parent, self, aux); 303 } 304 #endif 305 aprint_error(": can't find internal VGA" 306 " config space\n"); 307 error = ENOENT; 308 goto fail1; 309 } 310 311 /* XXXfvdl */ 312 sc->as_dmat = isc->vga_pa.pa_dmat; 313 314 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 315 case PCI_PRODUCT_INTEL_82810_GC: 316 case PCI_PRODUCT_INTEL_82810_DC100_GC: 317 case PCI_PRODUCT_INTEL_82810E_GC: 318 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 319 isc->chiptype = CHIP_I810; 320 aprint_normal(": i810-family chipset\n"); 321 break; 322 case PCI_PRODUCT_INTEL_82830MP_IV: 323 case PCI_PRODUCT_INTEL_82845G_IGD: 324 isc->chiptype = CHIP_I830; 325 aprint_normal(": i830-family chipset\n"); 326 break; 327 case PCI_PRODUCT_INTEL_82855GM_IGD: 328 case PCI_PRODUCT_INTEL_82865_IGD: 329 isc->chiptype = CHIP_I855; 330 aprint_normal(": i855-family chipset\n"); 331 break; 332 case PCI_PRODUCT_INTEL_82915G_IGD: 333 case PCI_PRODUCT_INTEL_82915GM_IGD: 334 case PCI_PRODUCT_INTEL_82945P_IGD: 335 case PCI_PRODUCT_INTEL_82945GM_IGD: 336 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 337 case PCI_PRODUCT_INTEL_82945GME_IGD: 338 case PCI_PRODUCT_INTEL_E7221_IGD: 339 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 340 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 341 isc->chiptype = CHIP_I915; 342 aprint_normal(": i915-family chipset\n"); 343 break; 344 case PCI_PRODUCT_INTEL_82965Q_IGD: 345 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 346 case PCI_PRODUCT_INTEL_82965PM_IGD: 347 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 348 case PCI_PRODUCT_INTEL_82965G_IGD: 349 case PCI_PRODUCT_INTEL_82965G_IGD_1: 350 case PCI_PRODUCT_INTEL_82965GME_IGD: 351 case PCI_PRODUCT_INTEL_82946GZ_IGD: 352 case PCI_PRODUCT_INTEL_82G35_IGD: 353 case PCI_PRODUCT_INTEL_82G35_IGD_1: 354 isc->chiptype = CHIP_I965; 355 aprint_normal(": i965-family chipset\n"); 356 break; 357 case PCI_PRODUCT_INTEL_82Q35_IGD: 358 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 359 case PCI_PRODUCT_INTEL_82G33_IGD: 360 case PCI_PRODUCT_INTEL_82G33_IGD_1: 361 case PCI_PRODUCT_INTEL_82Q33_IGD: 362 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 363 isc->chiptype = CHIP_G33; 364 aprint_normal(": G33-family chipset\n"); 365 break; 366 case PCI_PRODUCT_INTEL_82GM45_IGD: 367 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 368 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 369 case PCI_PRODUCT_INTEL_82Q45_IGD: 370 case PCI_PRODUCT_INTEL_82G45_IGD: 371 case PCI_PRODUCT_INTEL_82G41_IGD: 372 case PCI_PRODUCT_INTEL_82B43_IGD: 373 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 374 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 375 isc->chiptype = CHIP_G4X; 376 aprint_normal(": G4X-family chipset\n"); 377 break; 378 } 379 aprint_naive("\n"); 380 381 mmadr_type = PCI_MAPREG_TYPE_MEM; 382 switch (isc->chiptype) { 383 case CHIP_I915: 384 case CHIP_G33: 385 apbase = AGP_I915_GMADR; 386 mmadr_bar = AGP_I915_MMADR; 387 gtt_bar = AGP_I915_GTTADR; 388 gtt_off = ~(bus_addr_t)0; /* XXXGCC */ 389 break; 390 case CHIP_I965: 391 apbase = AGP_I965_GMADR; 392 mmadr_bar = AGP_I965_MMADR; 393 mmadr_type |= PCI_MAPREG_MEM_TYPE_64BIT; 394 gtt_bar = 0; 395 gtt_off = AGP_I965_GTT; 396 break; 397 case CHIP_G4X: 398 apbase = AGP_I965_GMADR; 399 mmadr_bar = AGP_I965_MMADR; 400 mmadr_type |= PCI_MAPREG_MEM_TYPE_64BIT; 401 gtt_bar = 0; 402 gtt_off = AGP_G4X_GTT; 403 break; 404 default: 405 apbase = AGP_I810_GMADR; 406 mmadr_bar = AGP_I810_MMADR; 407 gtt_bar = 0; 408 gtt_off = AGP_I810_GTT; 409 break; 410 } 411 412 /* Map (or, rather, find the address and size of) the aperture. */ 413 if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) 414 error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase); 415 else 416 error = agp_map_aperture(&isc->vga_pa, sc, apbase); 417 if (error) { 418 aprint_error_dev(self, "can't map aperture: %d\n", error); 419 goto fail1; 420 } 421 422 /* Map the memory-mapped I/O registers, or the non-GTT part. */ 423 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, mmadr_bar, 424 mmadr_type, &mmadr, &mmadr_size, &mmadr_flags)) { 425 aprint_error_dev(self, "can't find MMIO registers\n"); 426 error = ENXIO; 427 goto fail1; 428 } 429 if (gtt_bar == 0) { 430 if (mmadr_size < gtt_off) { 431 aprint_error_dev(self, "MMIO registers too small" 432 ": %"PRIuMAX" < %"PRIuMAX"\n", 433 (uintmax_t)mmadr_size, (uintmax_t)gtt_off); 434 error = ENXIO; 435 goto fail1; 436 } 437 isc->size = gtt_off; 438 } else { 439 isc->size = mmadr_size; 440 } 441 isc->bst = isc->vga_pa.pa_memt; 442 error = bus_space_map(isc->bst, mmadr, isc->size, mmadr_flags, 443 &isc->bsh); 444 if (error) { 445 aprint_error_dev(self, "can't map MMIO registers: %d\n", 446 error); 447 error = ENXIO; 448 goto fail1; 449 } 450 451 /* Map the GTT, from either part of the MMIO region or its own BAR. */ 452 if (gtt_bar == 0) { 453 isc->gtt_bst = isc->bst; 454 isc->gtt_size = (mmadr_size - gtt_off); 455 error = bus_space_map(isc->gtt_bst, (mmadr + gtt_off), 456 isc->gtt_size, mmadr_flags, &isc->gtt_bsh); 457 if (error) { 458 aprint_error_dev(self, "can't map GTT: %d\n", error); 459 error = ENXIO; 460 goto fail2; 461 } 462 } else { 463 /* 464 * All chipsets with a separate BAR for the GTT, namely 465 * the i915 and G33 families, have 32-bit GTT BARs. 466 * 467 * XXX [citation needed] 468 */ 469 if (pci_mapreg_map(&isc->vga_pa, gtt_bar, PCI_MAPREG_TYPE_MEM, 470 0, 471 &isc->gtt_bst, &isc->gtt_bsh, NULL, &isc->gtt_size)) { 472 aprint_error_dev(self, "can't map GTT\n"); 473 error = ENXIO; 474 goto fail2; 475 } 476 } 477 478 /* Set up a chipset flush page if necessary. */ 479 switch (isc->chiptype) { 480 case CHIP_I915: 481 case CHIP_I965: 482 case CHIP_G33: 483 case CHIP_G4X: 484 error = agp_i810_setup_chipset_flush_page(sc); 485 if (error) { 486 aprint_error_dev(self, 487 "can't set up chipset flush page: %d\n", error); 488 goto fail3; 489 } 490 break; 491 } 492 493 /* Set up the generic AGP GATT record. */ 494 isc->initial_aperture = AGP_GET_APERTURE(sc); 495 gatt = malloc(sizeof(struct agp_gatt), M_AGP, M_NOWAIT); 496 if (!gatt) { 497 error = ENOMEM; 498 goto fail4; 499 } 500 isc->gatt = gatt; 501 gatt->ag_entries = AGP_GET_APERTURE(sc) >> AGP_PAGE_SHIFT; 502 503 /* Power management. (XXX Nothing to save on suspend? Fishy...) */ 504 if (!pmf_device_register(self, NULL, agp_i810_resume)) 505 aprint_error_dev(self, "can't establish power handler\n"); 506 507 /* 508 * XXX horrible hack to allow drm code to use our mapping 509 * of VGA chip registers 510 */ 511 agp_i810_vga_regbase = mmadr; 512 agp_i810_vga_bsh = isc->bsh; 513 514 /* Initialize the chipset. */ 515 error = agp_i810_init(sc); 516 if (error) 517 goto fail5; 518 519 /* Match the generic AGP code's autoconf output format. */ 520 aprint_normal("%s", device_xname(self)); 521 522 /* Success! */ 523 return 0; 524 525 #if notyet 526 fail6: __unused 527 agp_i810_fini(sc); 528 #endif 529 fail5: pmf_device_deregister(self); 530 free(gatt, M_AGP); 531 isc->gatt = NULL; 532 fail4: switch (isc->chiptype) { 533 case CHIP_I915: 534 case CHIP_I965: 535 case CHIP_G33: 536 case CHIP_G4X: 537 agp_i810_teardown_chipset_flush_page(sc); 538 break; 539 } 540 fail3: bus_space_unmap(isc->gtt_bst, isc->gtt_bsh, isc->gtt_size); 541 isc->gtt_size = 0; 542 fail2: bus_space_unmap(isc->bst, isc->bsh, isc->size); 543 isc->size = 0; 544 fail1: free(isc, M_AGP); 545 sc->as_chipc = NULL; 546 fail0: agp_generic_detach(sc); 547 KASSERT(error); 548 return error; 549 } 550 551 static int 552 agp_i810_setup_chipset_flush_page(struct agp_softc *sc) 553 { 554 struct agp_i810_softc *const isc = sc->as_chipc; 555 const pci_chipset_tag_t pc = isc->as_pc; 556 const pcitag_t tag = isc->as_tag; 557 pcireg_t lo, hi; 558 bus_addr_t addr, minaddr, maxaddr; 559 int error; 560 561 /* We always use memory-mapped I/O. */ 562 isc->flush_bst = isc->vga_pa.pa_memt; 563 564 /* No page allocated yet. */ 565 isc->flush_addr = 0; 566 567 /* Read the PCI config register: 4-byte on gen3, 8-byte on gen>=4. */ 568 if (isc->chiptype == CHIP_I915) { 569 addr = pci_conf_read(pc, tag, AGP_I915_IFPADDR); 570 minaddr = PAGE_SIZE; /* XXX PCIBIOS_MIN_MEM? */ 571 maxaddr = UINT32_MAX; 572 } else { 573 hi = pci_conf_read(pc, tag, AGP_I965_IFPADDR+4); 574 lo = pci_conf_read(pc, tag, AGP_I965_IFPADDR); 575 /* 576 * Convert to uint64_t, rather than bus_addr_t which 577 * may be 32-bit, to avoid undefined behaviour with a 578 * too-wide shift. Since the BIOS doesn't know whether 579 * the OS will run 64-bit or with PAE, it ought to 580 * configure at most a 32-bit physical address, so 581 * let's print a warning in case that happens. 582 */ 583 addr = ((uint64_t)hi << 32) | lo; 584 if (hi) { 585 aprint_error_dev(sc->as_dev, 586 "BIOS configured >32-bit flush page address" 587 ": %"PRIx64"\n", ((uint64_t)hi << 32) | lo); 588 #if __i386__ && !PAE 589 return EIO; 590 #endif 591 } 592 minaddr = PAGE_SIZE; /* XXX PCIBIOS_MIN_MEM? */ 593 maxaddr = MIN(UINT64_MAX, ~(bus_addr_t)0); 594 } 595 596 /* Allocate or map a pre-allocated a page for it. */ 597 if (ISSET(addr, 1)) { 598 /* BIOS allocated it for us. Use that. */ 599 error = bus_space_map(isc->flush_bst, addr & ~1, PAGE_SIZE, 0, 600 &isc->flush_bsh); 601 if (error) 602 return error; 603 } else { 604 /* None allocated. Allocate one. */ 605 error = bus_space_alloc(isc->flush_bst, minaddr, maxaddr, 606 PAGE_SIZE, PAGE_SIZE, 0, 0, 607 &isc->flush_addr, &isc->flush_bsh); 608 if (error) 609 return error; 610 KASSERT(isc->flush_addr != 0); 611 /* Write it into the PCI config register. */ 612 addr = isc->flush_addr | 1; 613 if (isc->chiptype == CHIP_I915) { 614 pci_conf_write(pc, tag, AGP_I915_IFPADDR, addr); 615 } else { 616 hi = __SHIFTOUT(addr, __BITS(63, 32)); 617 lo = __SHIFTOUT(addr, __BITS(31, 0)) 618 pci_conf_write(pc, tag, AGP_I965_IFPADDR+4, hi); 619 pci_conf_write(pc, tag, AGP_I965_IFPADDR, lo); 620 } 621 } 622 623 /* Success! */ 624 return 0; 625 } 626 627 static void 628 agp_i810_teardown_chipset_flush_page(struct agp_softc *sc) 629 { 630 struct agp_i810_softc *const isc = sc->as_chipc; 631 632 if (isc->flush_addr) { 633 /* If we allocated a page, clear it. */ 634 if (isc->chiptype == CHIP_I915) { 635 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR, 636 0); 637 } else { 638 pci_conf_write(sc->as_pc, sc->as_tag, 639 AGP_I965_IFPADDR, 0); 640 pci_conf_write(sc->as_pc, sc->as_tag, 641 AGP_I965_IFPADDR + 4, 0); 642 } 643 isc->flush_addr = 0; 644 bus_space_free(isc->flush_bst, isc->flush_bsh, 645 PAGE_SIZE); 646 } else { 647 /* Otherwise, just unmap the pre-allocated page. */ 648 bus_space_unmap(isc->flush_bst, isc->flush_bsh, PAGE_SIZE); 649 } 650 } 651 652 /* 653 * XXX horrible hack to allow drm code to use our mapping 654 * of VGA chip registers 655 */ 656 int 657 agp_i810_borrow(bus_addr_t base, bus_space_handle_t *hdlp) 658 { 659 660 if (!agp_i810_vga_regbase || base != agp_i810_vga_regbase) 661 return 0; 662 *hdlp = agp_i810_vga_bsh; 663 return 1; 664 } 665 666 static int 667 agp_i810_init(struct agp_softc *sc) 668 { 669 struct agp_i810_softc *isc; 670 struct agp_gatt *gatt; 671 int error; 672 673 isc = sc->as_chipc; 674 gatt = isc->gatt; 675 676 if (isc->chiptype == CHIP_I810) { 677 void *virtual; 678 int dummyseg; 679 680 /* Some i810s have on-chip memory called dcache */ 681 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 682 isc->dcache_size = 4 * 1024 * 1024; 683 else 684 isc->dcache_size = 0; 685 686 /* According to the specs the gatt on the i810 must be 64k */ 687 error = agp_alloc_dmamem(sc->as_dmat, 64 * 1024, 688 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical, 689 &gatt->ag_dmaseg, 1, &dummyseg); 690 if (error) { 691 aprint_error_dev(sc->as_dev, 692 "can't allocate memory for GTT: %d\n", error); 693 goto fail0; 694 } 695 696 gatt->ag_virtual = (uint32_t *)virtual; 697 gatt->ag_size = gatt->ag_entries * sizeof(u_int32_t); 698 memset(gatt->ag_virtual, 0, gatt->ag_size); 699 700 agp_flush_cache(); 701 /* Install the GATT. */ 702 WRITE4(AGP_I810_PGTBL_CTL, gatt->ag_physical | 1); 703 } else if (isc->chiptype == CHIP_I830) { 704 /* The i830 automatically initializes the 128k gatt on boot. */ 705 pcireg_t reg; 706 u_int32_t pgtblctl; 707 u_int16_t gcc1; 708 709 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 710 gcc1 = (u_int16_t)(reg >> 16); 711 switch (gcc1 & AGP_I830_GCC1_GMS) { 712 case AGP_I830_GCC1_GMS_STOLEN_512: 713 isc->stolen = (512 - 132) * 1024 / 4096; 714 break; 715 case AGP_I830_GCC1_GMS_STOLEN_1024: 716 isc->stolen = (1024 - 132) * 1024 / 4096; 717 break; 718 case AGP_I830_GCC1_GMS_STOLEN_8192: 719 isc->stolen = (8192 - 132) * 1024 / 4096; 720 break; 721 default: 722 isc->stolen = 0; 723 aprint_error_dev(sc->as_dev, 724 "unknown memory configuration, disabling\n"); 725 error = ENXIO; 726 goto fail0; 727 } 728 729 if (isc->stolen > 0) { 730 aprint_normal_dev(sc->as_dev, 731 "detected %dk stolen memory\n", 732 isc->stolen * 4); 733 } 734 735 /* GATT address is already in there, make sure it's enabled */ 736 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 737 pgtblctl |= 1; 738 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 739 740 gatt->ag_physical = pgtblctl & ~1; 741 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 742 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 || 743 isc->chiptype == CHIP_G4X) { 744 pcireg_t reg; 745 u_int32_t pgtblctl, gtt_size, stolen; 746 u_int16_t gcc1; 747 748 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1); 749 gcc1 = (u_int16_t)(reg >> 16); 750 751 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 752 753 /* Stolen memory is set up at the beginning of the aperture by 754 * the BIOS, consisting of the GATT followed by 4kb for the 755 * BIOS display. 756 */ 757 switch (isc->chiptype) { 758 case CHIP_I855: 759 gtt_size = 128; 760 break; 761 case CHIP_I915: 762 gtt_size = 256; 763 break; 764 case CHIP_I965: 765 switch (pgtblctl & AGP_I810_PGTBL_SIZE_MASK) { 766 case AGP_I810_PGTBL_SIZE_128KB: 767 case AGP_I810_PGTBL_SIZE_512KB: 768 gtt_size = 512; 769 break; 770 case AGP_I965_PGTBL_SIZE_1MB: 771 gtt_size = 1024; 772 break; 773 case AGP_I965_PGTBL_SIZE_2MB: 774 gtt_size = 2048; 775 break; 776 case AGP_I965_PGTBL_SIZE_1_5MB: 777 gtt_size = 1024 + 512; 778 break; 779 default: 780 aprint_error_dev(sc->as_dev, 781 "bad PGTBL size\n"); 782 error = ENXIO; 783 goto fail0; 784 } 785 break; 786 case CHIP_G33: 787 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 788 case AGP_G33_PGTBL_SIZE_1M: 789 gtt_size = 1024; 790 break; 791 case AGP_G33_PGTBL_SIZE_2M: 792 gtt_size = 2048; 793 break; 794 default: 795 aprint_error_dev(sc->as_dev, 796 "bad PGTBL size\n"); 797 error = ENXIO; 798 goto fail0; 799 } 800 break; 801 case CHIP_G4X: 802 gtt_size = 0; 803 break; 804 default: 805 panic("impossible chiptype %d", isc->chiptype); 806 } 807 808 switch (gcc1 & AGP_I855_GCC1_GMS) { 809 case AGP_I855_GCC1_GMS_STOLEN_1M: 810 stolen = 1024; 811 break; 812 case AGP_I855_GCC1_GMS_STOLEN_4M: 813 stolen = 4 * 1024; 814 break; 815 case AGP_I855_GCC1_GMS_STOLEN_8M: 816 stolen = 8 * 1024; 817 break; 818 case AGP_I855_GCC1_GMS_STOLEN_16M: 819 stolen = 16 * 1024; 820 break; 821 case AGP_I855_GCC1_GMS_STOLEN_32M: 822 stolen = 32 * 1024; 823 break; 824 case AGP_I915_GCC1_GMS_STOLEN_48M: 825 stolen = 48 * 1024; 826 break; 827 case AGP_I915_GCC1_GMS_STOLEN_64M: 828 stolen = 64 * 1024; 829 break; 830 case AGP_G33_GCC1_GMS_STOLEN_128M: 831 stolen = 128 * 1024; 832 break; 833 case AGP_G33_GCC1_GMS_STOLEN_256M: 834 stolen = 256 * 1024; 835 break; 836 case AGP_G4X_GCC1_GMS_STOLEN_96M: 837 stolen = 96 * 1024; 838 break; 839 case AGP_G4X_GCC1_GMS_STOLEN_160M: 840 stolen = 160 * 1024; 841 break; 842 case AGP_G4X_GCC1_GMS_STOLEN_224M: 843 stolen = 224 * 1024; 844 break; 845 case AGP_G4X_GCC1_GMS_STOLEN_352M: 846 stolen = 352 * 1024; 847 break; 848 default: 849 aprint_error_dev(sc->as_dev, 850 "unknown memory configuration, disabling\n"); 851 error = ENXIO; 852 goto fail0; 853 } 854 855 switch (gcc1 & AGP_I855_GCC1_GMS) { 856 case AGP_I915_GCC1_GMS_STOLEN_48M: 857 case AGP_I915_GCC1_GMS_STOLEN_64M: 858 if (isc->chiptype != CHIP_I915 && 859 isc->chiptype != CHIP_I965 && 860 isc->chiptype != CHIP_G33 && 861 isc->chiptype != CHIP_G4X) 862 stolen = 0; 863 break; 864 case AGP_G33_GCC1_GMS_STOLEN_128M: 865 case AGP_G33_GCC1_GMS_STOLEN_256M: 866 if (isc->chiptype != CHIP_I965 && 867 isc->chiptype != CHIP_G33 && 868 isc->chiptype != CHIP_G4X) 869 stolen = 0; 870 break; 871 case AGP_G4X_GCC1_GMS_STOLEN_96M: 872 case AGP_G4X_GCC1_GMS_STOLEN_160M: 873 case AGP_G4X_GCC1_GMS_STOLEN_224M: 874 case AGP_G4X_GCC1_GMS_STOLEN_352M: 875 if (isc->chiptype != CHIP_I965 && 876 isc->chiptype != CHIP_G4X) 877 stolen = 0; 878 break; 879 } 880 881 /* BIOS space */ 882 gtt_size += 4; 883 884 isc->stolen = (stolen - gtt_size) * 1024 / 4096; 885 886 if (isc->stolen > 0) { 887 aprint_normal_dev(sc->as_dev, 888 "detected %dk stolen memory\n", 889 isc->stolen * 4); 890 } 891 892 /* GATT address is already in there, make sure it's enabled */ 893 pgtblctl |= 1; 894 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 895 896 gatt->ag_physical = pgtblctl & ~1; 897 } 898 899 /* 900 * Make sure the chipset can see everything. 901 */ 902 agp_flush_cache(); 903 904 /* 905 * Publish what we found for kludgey drivers (I'm looking at 906 * you, drm). 907 */ 908 if (agp_i810_sc == NULL) 909 agp_i810_sc = sc; 910 else 911 aprint_error_dev(sc->as_dev, "agp already attached\n"); 912 913 /* Success! */ 914 return 0; 915 916 fail0: KASSERT(error); 917 return error; 918 } 919 920 #if 0 921 static int 922 agp_i810_detach(struct agp_softc *sc) 923 { 924 int error; 925 struct agp_i810_softc *isc = sc->as_chipc; 926 927 error = agp_generic_detach(sc); 928 if (error) 929 return error; 930 931 switch (isc->chiptype) { 932 case CHIP_I915: 933 case CHIP_I965: 934 case CHIP_G33: 935 case CHIP_G4X: 936 agp_i810_teardown_chipset_flush_page(sc); 937 break; 938 } 939 940 /* Clear the GATT base. */ 941 if (sc->chiptype == CHIP_I810) { 942 WRITE4(AGP_I810_PGTBL_CTL, 0); 943 } else { 944 unsigned int pgtblctl; 945 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 946 pgtblctl &= ~1; 947 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 948 } 949 950 /* Put the aperture back the way it started. */ 951 AGP_SET_APERTURE(sc, isc->initial_aperture); 952 953 if (sc->chiptype == CHIP_I810) { 954 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap, 955 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 956 } 957 free(sc->gatt, M_AGP); 958 959 return 0; 960 } 961 #endif 962 963 static u_int32_t 964 agp_i810_get_aperture(struct agp_softc *sc) 965 { 966 struct agp_i810_softc *isc = sc->as_chipc; 967 pcireg_t reg; 968 u_int32_t size; 969 u_int16_t miscc, gcc1, msac; 970 971 size = 0; 972 973 switch (isc->chiptype) { 974 case CHIP_I810: 975 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 976 miscc = (u_int16_t)(reg >> 16); 977 if ((miscc & AGP_I810_MISCC_WINSIZE) == 978 AGP_I810_MISCC_WINSIZE_32) 979 size = 32 * 1024 * 1024; 980 else 981 size = 64 * 1024 * 1024; 982 break; 983 case CHIP_I830: 984 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 985 gcc1 = (u_int16_t)(reg >> 16); 986 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 987 size = 64 * 1024 * 1024; 988 else 989 size = 128 * 1024 * 1024; 990 break; 991 case CHIP_I855: 992 size = 128 * 1024 * 1024; 993 break; 994 case CHIP_I915: 995 case CHIP_G33: 996 case CHIP_G4X: 997 reg = pci_conf_read(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, 998 AGP_I915_MSAC); 999 msac = (u_int16_t)(reg >> 16); 1000 if (msac & AGP_I915_MSAC_APER_128M) 1001 size = 128 * 1024 * 1024; 1002 else 1003 size = 256 * 1024 * 1024; 1004 break; 1005 case CHIP_I965: 1006 size = 512 * 1024 * 1024; 1007 break; 1008 default: 1009 aprint_error(": Unknown chipset\n"); 1010 } 1011 1012 return size; 1013 } 1014 1015 static int 1016 agp_i810_set_aperture(struct agp_softc *sc, u_int32_t aperture) 1017 { 1018 struct agp_i810_softc *isc = sc->as_chipc; 1019 pcireg_t reg; 1020 u_int16_t miscc, gcc1; 1021 1022 switch (isc->chiptype) { 1023 case CHIP_I810: 1024 /* 1025 * Double check for sanity. 1026 */ 1027 if (aperture != (32 * 1024 * 1024) && 1028 aperture != (64 * 1024 * 1024)) { 1029 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 1030 aperture); 1031 return EINVAL; 1032 } 1033 1034 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 1035 miscc = (u_int16_t)(reg >> 16); 1036 miscc &= ~AGP_I810_MISCC_WINSIZE; 1037 if (aperture == 32 * 1024 * 1024) 1038 miscc |= AGP_I810_MISCC_WINSIZE_32; 1039 else 1040 miscc |= AGP_I810_MISCC_WINSIZE_64; 1041 1042 reg &= 0x0000ffff; 1043 reg |= ((pcireg_t)miscc) << 16; 1044 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I810_SMRAM, reg); 1045 break; 1046 case CHIP_I830: 1047 if (aperture != (64 * 1024 * 1024) && 1048 aperture != (128 * 1024 * 1024)) { 1049 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 1050 aperture); 1051 return EINVAL; 1052 } 1053 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 1054 gcc1 = (u_int16_t)(reg >> 16); 1055 gcc1 &= ~AGP_I830_GCC1_GMASIZE; 1056 if (aperture == 64 * 1024 * 1024) 1057 gcc1 |= AGP_I830_GCC1_GMASIZE_64; 1058 else 1059 gcc1 |= AGP_I830_GCC1_GMASIZE_128; 1060 1061 reg &= 0x0000ffff; 1062 reg |= ((pcireg_t)gcc1) << 16; 1063 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I830_GCC0, reg); 1064 break; 1065 case CHIP_I855: 1066 case CHIP_I915: 1067 if (aperture != agp_i810_get_aperture(sc)) { 1068 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 1069 aperture); 1070 return EINVAL; 1071 } 1072 break; 1073 case CHIP_I965: 1074 if (aperture != 512 * 1024 * 1024) { 1075 aprint_error_dev(sc->as_dev, "bad aperture size %d\n", 1076 aperture); 1077 return EINVAL; 1078 } 1079 break; 1080 } 1081 1082 return 0; 1083 } 1084 1085 static int 1086 agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 1087 { 1088 struct agp_i810_softc *isc = sc->as_chipc; 1089 1090 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) { 1091 #ifdef AGP_DEBUG 1092 printf("%s: failed: offset 0x%08x, shift %d, entries %d\n", 1093 device_xname(sc->as_dev), (int)offset, AGP_PAGE_SHIFT, 1094 isc->gatt->ag_entries); 1095 #endif 1096 return EINVAL; 1097 } 1098 1099 if (isc->chiptype != CHIP_I810) { 1100 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1101 #ifdef AGP_DEBUG 1102 printf("%s: trying to bind into stolen memory\n", 1103 device_xname(sc->as_dev)); 1104 #endif 1105 return EINVAL; 1106 } 1107 } 1108 1109 return agp_i810_write_gtt_entry(isc, offset, physical | 1); 1110 } 1111 1112 static int 1113 agp_i810_unbind_page(struct agp_softc *sc, off_t offset) 1114 { 1115 struct agp_i810_softc *isc = sc->as_chipc; 1116 1117 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 1118 return EINVAL; 1119 1120 if (isc->chiptype != CHIP_I810 ) { 1121 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1122 #ifdef AGP_DEBUG 1123 printf("%s: trying to unbind from stolen memory\n", 1124 device_xname(sc->as_dev)); 1125 #endif 1126 return EINVAL; 1127 } 1128 } 1129 1130 return agp_i810_write_gtt_entry(isc, offset, 0); 1131 } 1132 1133 /* 1134 * Writing via memory mapped registers already flushes all TLBs. 1135 */ 1136 static void 1137 agp_i810_flush_tlb(struct agp_softc *sc) 1138 { 1139 } 1140 1141 static int 1142 agp_i810_enable(struct agp_softc *sc, u_int32_t mode) 1143 { 1144 1145 return 0; 1146 } 1147 1148 static struct agp_memory * 1149 agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size) 1150 { 1151 struct agp_i810_softc *isc = sc->as_chipc; 1152 struct agp_memory *mem; 1153 1154 #ifdef AGP_DEBUG 1155 printf("AGP: alloc(%d, 0x%x)\n", type, (int) size); 1156 #endif 1157 1158 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 1159 return 0; 1160 1161 if (sc->as_allocated + size > sc->as_maxmem) 1162 return 0; 1163 1164 if (type == 1) { 1165 /* 1166 * Mapping local DRAM into GATT. 1167 */ 1168 if (isc->chiptype != CHIP_I810 ) 1169 return 0; 1170 if (size != isc->dcache_size) 1171 return 0; 1172 } else if (type == 2) { 1173 /* 1174 * Bogus mapping for the hardware cursor. 1175 */ 1176 if (size != AGP_PAGE_SIZE && size != 4 * AGP_PAGE_SIZE) 1177 return 0; 1178 } 1179 1180 mem = malloc(sizeof *mem, M_AGP, M_WAITOK|M_ZERO); 1181 if (mem == NULL) 1182 return NULL; 1183 mem->am_id = sc->as_nextid++; 1184 mem->am_size = size; 1185 mem->am_type = type; 1186 1187 if (type == 2) { 1188 /* 1189 * Allocate and wire down the memory now so that we can 1190 * get its physical address. 1191 */ 1192 mem->am_dmaseg = malloc(sizeof *mem->am_dmaseg, M_AGP, 1193 M_WAITOK); 1194 if (mem->am_dmaseg == NULL) { 1195 free(mem, M_AGP); 1196 return NULL; 1197 } 1198 if (agp_alloc_dmamem(sc->as_dmat, size, 0, 1199 &mem->am_dmamap, &mem->am_virtual, &mem->am_physical, 1200 mem->am_dmaseg, 1, &mem->am_nseg) != 0) { 1201 free(mem->am_dmaseg, M_AGP); 1202 free(mem, M_AGP); 1203 return NULL; 1204 } 1205 memset(mem->am_virtual, 0, size); 1206 } else if (type != 1) { 1207 if (bus_dmamap_create(sc->as_dmat, size, size / PAGE_SIZE + 1, 1208 size, 0, BUS_DMA_NOWAIT, 1209 &mem->am_dmamap) != 0) { 1210 free(mem, M_AGP); 1211 return NULL; 1212 } 1213 } 1214 1215 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link); 1216 sc->as_allocated += size; 1217 1218 return mem; 1219 } 1220 1221 static int 1222 agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem) 1223 { 1224 if (mem->am_is_bound) 1225 return EBUSY; 1226 1227 if (mem->am_type == 2) { 1228 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap, 1229 mem->am_virtual, mem->am_dmaseg, mem->am_nseg); 1230 free(mem->am_dmaseg, M_AGP); 1231 } 1232 1233 sc->as_allocated -= mem->am_size; 1234 TAILQ_REMOVE(&sc->as_memory, mem, am_link); 1235 free(mem, M_AGP); 1236 return 0; 1237 } 1238 1239 static int 1240 agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem, 1241 off_t offset) 1242 { 1243 struct agp_i810_softc *isc = sc->as_chipc; 1244 u_int32_t regval, i; 1245 1246 if (mem->am_is_bound != 0) 1247 return EINVAL; 1248 1249 /* 1250 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 1251 * X server for mysterious reasons which leads to crashes if we write 1252 * to the GTT through the MMIO window. 1253 * Until the issue is solved, simply restore it. 1254 */ 1255 regval = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL); 1256 if (regval != (isc->gatt->ag_physical | 1)) { 1257 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%x - fixing\n", 1258 regval); 1259 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 1260 isc->gatt->ag_physical | 1); 1261 } 1262 1263 if (mem->am_type == 2) { 1264 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1265 agp_i810_bind_page(sc, offset + i, 1266 mem->am_physical + i); 1267 mem->am_offset = offset; 1268 mem->am_is_bound = 1; 1269 return 0; 1270 } 1271 1272 if (mem->am_type != 1) 1273 return agp_generic_bind_memory(sc, mem, offset); 1274 1275 if (isc->chiptype != CHIP_I810) 1276 return EINVAL; 1277 1278 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1279 agp_i810_write_gtt_entry(isc, i, i | 3); 1280 mem->am_is_bound = 1; 1281 return 0; 1282 } 1283 1284 static int 1285 agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem) 1286 { 1287 struct agp_i810_softc *isc = sc->as_chipc; 1288 u_int32_t i; 1289 1290 if (mem->am_is_bound == 0) 1291 return EINVAL; 1292 1293 if (mem->am_type == 2) { 1294 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1295 agp_i810_unbind_page(sc, mem->am_offset + i); 1296 mem->am_offset = 0; 1297 mem->am_is_bound = 0; 1298 return 0; 1299 } 1300 1301 if (mem->am_type != 1) 1302 return agp_generic_unbind_memory(sc, mem); 1303 1304 if (isc->chiptype != CHIP_I810) 1305 return EINVAL; 1306 1307 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1308 agp_i810_write_gtt_entry(isc, i, 0); 1309 mem->am_is_bound = 0; 1310 return 0; 1311 } 1312 1313 static bool 1314 agp_i810_resume(device_t dv, const pmf_qual_t *qual) 1315 { 1316 struct agp_softc *sc = device_private(dv); 1317 struct agp_i810_softc *isc = sc->as_chipc; 1318 1319 /* 1320 * XXX Nothing uses isc->pgtblctl! Save on suspend, restore on 1321 * resume? 1322 */ 1323 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 1324 agp_flush_cache(); 1325 1326 return true; 1327 } 1328
Indexes created Thu Sep 25 16:09:42 GMT 2025