agp_i810.c revision 1.94
1 /* $NetBSD: agp_i810.c,v 1.94 2014/06/11 17:15:18 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.94 2014/06/11 17:15:18 riastradh Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/proc.h> 40 #include <sys/device.h> 41 #include <sys/conf.h> 42 #include <sys/xcall.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcidevs.h> 47 #include <dev/pci/agpvar.h> 48 #include <dev/pci/agpreg.h> 49 #include <dev/pci/agp_i810var.h> 50 51 #include <sys/agpio.h> 52 53 #include <sys/bus.h> 54 55 #include "agp_intel.h" 56 57 struct agp_softc *agp_i810_sc = NULL; 58 59 #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off) 60 #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off) 61 #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v) 62 63 #define CHIP_I810 0 /* i810/i815 */ 64 #define CHIP_I830 1 /* 830M/845G */ 65 #define CHIP_I855 2 /* 852GM/855GM/865G */ 66 #define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */ 67 #define CHIP_I965 4 /* 965Q/965PM */ 68 #define CHIP_G33 5 /* G33/Q33/Q35 */ 69 #define CHIP_G4X 6 /* G45/Q45 */ 70 71 /* XXX hack, see below */ 72 static bus_addr_t agp_i810_vga_regbase; 73 static bus_space_handle_t agp_i810_vga_bsh; 74 75 static u_int32_t agp_i810_get_aperture(struct agp_softc *); 76 static int agp_i810_set_aperture(struct agp_softc *, u_int32_t); 77 static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t); 78 static int agp_i810_unbind_page(struct agp_softc *, off_t); 79 static void agp_i810_flush_tlb(struct agp_softc *); 80 static int agp_i810_enable(struct agp_softc *, u_int32_t mode); 81 static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int, 82 vsize_t); 83 static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *); 84 static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, 85 off_t); 86 static int agp_i810_bind_memory_main(struct agp_softc *, struct agp_memory *, 87 off_t); 88 static int agp_i810_bind_memory_dcache(struct agp_softc *, struct agp_memory *, 89 off_t); 90 static int agp_i810_bind_memory_hwcursor(struct agp_softc *, 91 struct agp_memory *, off_t); 92 static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *); 93 94 static bool agp_i810_resume(device_t, const pmf_qual_t *); 95 static int agp_i810_init(struct agp_softc *); 96 97 static int agp_i810_setup_chipset_flush_page(struct agp_softc *); 98 static void agp_i810_teardown_chipset_flush_page(struct agp_softc *); 99 static int agp_i810_init(struct agp_softc *); 100 101 static struct agp_methods agp_i810_methods = { 102 agp_i810_get_aperture, 103 agp_i810_set_aperture, 104 agp_i810_bind_page, 105 agp_i810_unbind_page, 106 agp_i810_flush_tlb, 107 agp_i810_enable, 108 agp_i810_alloc_memory, 109 agp_i810_free_memory, 110 agp_i810_bind_memory, 111 agp_i810_unbind_memory, 112 }; 113 114 int 115 agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, bus_addr_t v) 116 { 117 u_int32_t pte; 118 119 /* Bits 11:4 (physical start address extension) should be zero. */ 120 if ((v & 0xff0) != 0) 121 return EINVAL; 122 123 pte = (u_int32_t)v; 124 /* 125 * We need to massage the pte if bus_addr_t is wider than 32 bits. 126 * The compiler isn't smart enough, hence the casts to uintmax_t. 127 */ 128 if (sizeof(bus_addr_t) > sizeof(u_int32_t)) { 129 /* 965+ can do 36-bit addressing, add in the extra bits. */ 130 if (isc->chiptype == CHIP_I965 || 131 isc->chiptype == CHIP_G33 || 132 isc->chiptype == CHIP_G4X) { 133 if (((uintmax_t)v >> 36) != 0) 134 return EINVAL; 135 pte |= (v >> 28) & 0xf0; 136 } else { 137 if (((uintmax_t)v >> 32) != 0) 138 return EINVAL; 139 } 140 } 141 142 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, 143 4*(off >> AGP_PAGE_SHIFT), pte); 144 145 return 0; 146 } 147 148 void 149 agp_i810_post_gtt_entry(struct agp_i810_softc *isc, off_t off) 150 { 151 152 (void)bus_space_read_4(isc->gtt_bst, isc->gtt_bsh, 153 4*(off >> AGP_PAGE_SHIFT)); 154 } 155 156 static void 157 agp_flush_cache_xc(void *a __unused, void *b __unused) 158 { 159 160 agp_flush_cache(); 161 } 162 163 void 164 agp_i810_chipset_flush(struct agp_i810_softc *isc) 165 { 166 unsigned int timo = 20000; /* * 50 us = 1 s */ 167 168 switch (isc->chiptype) { 169 case CHIP_I810: 170 break; 171 case CHIP_I830: 172 case CHIP_I855: 173 /* 174 * Flush all CPU caches. If we're cold, we can't run 175 * xcalls, but there should be only one CPU up, so 176 * flushing only the local CPU's cache should suffice. 177 * 178 * XXX Come to think of it, do these chipsets appear in 179 * any multi-CPU systems? 180 */ 181 if (cold) 182 agp_flush_cache(); 183 else 184 xc_wait(xc_broadcast(0, &agp_flush_cache_xc, 185 NULL, NULL)); 186 WRITE4(AGP_I830_HIC, READ4(AGP_I830_HIC) | __BIT(31)); 187 while (ISSET(READ4(AGP_I830_HIC), __BIT(31))) { 188 if (timo-- == 0) 189 break; 190 DELAY(50); 191 } 192 break; 193 case CHIP_I915: 194 case CHIP_I965: 195 case CHIP_G33: 196 case CHIP_G4X: 197 bus_space_write_4(isc->flush_bst, isc->flush_bsh, 0, 1); 198 break; 199 } 200 } 201 202 /* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */ 203 static int 204 agp_i810_vgamatch(const struct pci_attach_args *pa) 205 { 206 207 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 208 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 209 return (0); 210 211 switch (PCI_PRODUCT(pa->pa_id)) { 212 case PCI_PRODUCT_INTEL_82810_GC: 213 case PCI_PRODUCT_INTEL_82810_DC100_GC: 214 case PCI_PRODUCT_INTEL_82810E_GC: 215 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 216 case PCI_PRODUCT_INTEL_82830MP_IV: 217 case PCI_PRODUCT_INTEL_82845G_IGD: 218 case PCI_PRODUCT_INTEL_82855GM_IGD: 219 case PCI_PRODUCT_INTEL_82865_IGD: 220 case PCI_PRODUCT_INTEL_82915G_IGD: 221 case PCI_PRODUCT_INTEL_82915GM_IGD: 222 case PCI_PRODUCT_INTEL_82945P_IGD: 223 case PCI_PRODUCT_INTEL_82945GM_IGD: 224 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 225 case PCI_PRODUCT_INTEL_82945GME_IGD: 226 case PCI_PRODUCT_INTEL_E7221_IGD: 227 case PCI_PRODUCT_INTEL_82965Q_IGD: 228 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 229 case PCI_PRODUCT_INTEL_82965PM_IGD: 230 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 231 case PCI_PRODUCT_INTEL_82G33_IGD: 232 case PCI_PRODUCT_INTEL_82G33_IGD_1: 233 case PCI_PRODUCT_INTEL_82965G_IGD: 234 case PCI_PRODUCT_INTEL_82965G_IGD_1: 235 case PCI_PRODUCT_INTEL_82965GME_IGD: 236 case PCI_PRODUCT_INTEL_82Q35_IGD: 237 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 238 case PCI_PRODUCT_INTEL_82Q33_IGD: 239 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 240 case PCI_PRODUCT_INTEL_82G35_IGD: 241 case PCI_PRODUCT_INTEL_82G35_IGD_1: 242 case PCI_PRODUCT_INTEL_82946GZ_IGD: 243 case PCI_PRODUCT_INTEL_82GM45_IGD: 244 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 245 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 246 case PCI_PRODUCT_INTEL_82Q45_IGD: 247 case PCI_PRODUCT_INTEL_82G45_IGD: 248 case PCI_PRODUCT_INTEL_82G41_IGD: 249 case PCI_PRODUCT_INTEL_82B43_IGD: 250 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 251 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 252 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 253 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 254 return (1); 255 } 256 257 return (0); 258 } 259 260 static int 261 agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg) 262 { 263 /* 264 * Find the aperture. Don't map it (yet), this would 265 * eat KVA. 266 */ 267 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 268 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize, 269 &sc->as_apflags) != 0) 270 return ENXIO; 271 272 sc->as_apt = pa->pa_memt; 273 274 return 0; 275 } 276 277 int 278 agp_i810_attach(device_t parent, device_t self, void *aux) 279 { 280 struct agp_softc *sc = device_private(self); 281 struct agp_i810_softc *isc; 282 int apbase, mmadr_bar, gtt_bar; 283 int mmadr_type, mmadr_flags; 284 bus_addr_t mmadr, gtt_off; 285 bus_size_t mmadr_size; 286 int error; 287 288 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 289 if (isc == NULL) { 290 aprint_error(": can't allocate chipset-specific softc\n"); 291 error = ENOMEM; 292 goto fail0; 293 } 294 sc->as_chipc = isc; 295 sc->as_methods = &agp_i810_methods; 296 297 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) { 298 #if NAGP_INTEL > 0 299 const struct pci_attach_args *pa = aux; 300 301 switch (PCI_PRODUCT(pa->pa_id)) { 302 case PCI_PRODUCT_INTEL_82840_HB: 303 case PCI_PRODUCT_INTEL_82865_HB: 304 case PCI_PRODUCT_INTEL_82845G_DRAM: 305 case PCI_PRODUCT_INTEL_82815_FULL_HUB: 306 case PCI_PRODUCT_INTEL_82855GM_MCH: 307 free(isc, M_AGP); 308 return agp_intel_attach(parent, self, aux); 309 } 310 #endif 311 aprint_error(": can't find internal VGA" 312 " config space\n"); 313 error = ENOENT; 314 goto fail1; 315 } 316 317 /* XXXfvdl */ 318 sc->as_dmat = isc->vga_pa.pa_dmat; 319 320 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 321 case PCI_PRODUCT_INTEL_82810_GC: 322 case PCI_PRODUCT_INTEL_82810_DC100_GC: 323 case PCI_PRODUCT_INTEL_82810E_GC: 324 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 325 isc->chiptype = CHIP_I810; 326 aprint_normal(": i810-family chipset\n"); 327 break; 328 case PCI_PRODUCT_INTEL_82830MP_IV: 329 case PCI_PRODUCT_INTEL_82845G_IGD: 330 isc->chiptype = CHIP_I830; 331 aprint_normal(": i830-family chipset\n"); 332 break; 333 case PCI_PRODUCT_INTEL_82855GM_IGD: 334 case PCI_PRODUCT_INTEL_82865_IGD: 335 isc->chiptype = CHIP_I855; 336 aprint_normal(": i855-family chipset\n"); 337 break; 338 case PCI_PRODUCT_INTEL_82915G_IGD: 339 case PCI_PRODUCT_INTEL_82915GM_IGD: 340 case PCI_PRODUCT_INTEL_82945P_IGD: 341 case PCI_PRODUCT_INTEL_82945GM_IGD: 342 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 343 case PCI_PRODUCT_INTEL_82945GME_IGD: 344 case PCI_PRODUCT_INTEL_E7221_IGD: 345 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 346 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 347 isc->chiptype = CHIP_I915; 348 aprint_normal(": i915-family chipset\n"); 349 break; 350 case PCI_PRODUCT_INTEL_82965Q_IGD: 351 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 352 case PCI_PRODUCT_INTEL_82965PM_IGD: 353 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 354 case PCI_PRODUCT_INTEL_82965G_IGD: 355 case PCI_PRODUCT_INTEL_82965G_IGD_1: 356 case PCI_PRODUCT_INTEL_82965GME_IGD: 357 case PCI_PRODUCT_INTEL_82946GZ_IGD: 358 case PCI_PRODUCT_INTEL_82G35_IGD: 359 case PCI_PRODUCT_INTEL_82G35_IGD_1: 360 isc->chiptype = CHIP_I965; 361 aprint_normal(": i965-family chipset\n"); 362 break; 363 case PCI_PRODUCT_INTEL_82Q35_IGD: 364 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 365 case PCI_PRODUCT_INTEL_82G33_IGD: 366 case PCI_PRODUCT_INTEL_82G33_IGD_1: 367 case PCI_PRODUCT_INTEL_82Q33_IGD: 368 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 369 isc->chiptype = CHIP_G33; 370 aprint_normal(": G33-family chipset\n"); 371 break; 372 case PCI_PRODUCT_INTEL_82GM45_IGD: 373 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 374 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 375 case PCI_PRODUCT_INTEL_82Q45_IGD: 376 case PCI_PRODUCT_INTEL_82G45_IGD: 377 case PCI_PRODUCT_INTEL_82G41_IGD: 378 case PCI_PRODUCT_INTEL_82B43_IGD: 379 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 380 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 381 isc->chiptype = CHIP_G4X; 382 aprint_normal(": G4X-family chipset\n"); 383 break; 384 } 385 aprint_naive("\n"); 386 387 mmadr_type = PCI_MAPREG_TYPE_MEM; 388 switch (isc->chiptype) { 389 case CHIP_I915: 390 case CHIP_G33: 391 apbase = AGP_I915_GMADR; 392 mmadr_bar = AGP_I915_MMADR; 393 gtt_bar = AGP_I915_GTTADR; 394 gtt_off = ~(bus_addr_t)0; /* XXXGCC */ 395 break; 396 case CHIP_I965: 397 apbase = AGP_I965_GMADR; 398 mmadr_bar = AGP_I965_MMADR; 399 mmadr_type |= PCI_MAPREG_MEM_TYPE_64BIT; 400 gtt_bar = 0; 401 gtt_off = AGP_I965_GTT; 402 break; 403 case CHIP_G4X: 404 apbase = AGP_I965_GMADR; 405 mmadr_bar = AGP_I965_MMADR; 406 mmadr_type |= PCI_MAPREG_MEM_TYPE_64BIT; 407 gtt_bar = 0; 408 gtt_off = AGP_G4X_GTT; 409 break; 410 default: 411 apbase = AGP_I810_GMADR; 412 mmadr_bar = AGP_I810_MMADR; 413 gtt_bar = 0; 414 gtt_off = AGP_I810_GTT; 415 break; 416 } 417 418 /* Map (or, rather, find the address and size of) the aperture. */ 419 if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) 420 error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase); 421 else 422 error = agp_map_aperture(&isc->vga_pa, sc, apbase); 423 if (error) { 424 aprint_error_dev(self, "can't map aperture: %d\n", error); 425 goto fail1; 426 } 427 428 /* Map the memory-mapped I/O registers, or the non-GTT part. */ 429 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, mmadr_bar, 430 mmadr_type, &mmadr, &mmadr_size, &mmadr_flags)) { 431 aprint_error_dev(self, "can't find MMIO registers\n"); 432 error = ENXIO; 433 goto fail1; 434 } 435 if (gtt_bar == 0) { 436 if (mmadr_size < gtt_off) { 437 aprint_error_dev(self, "MMIO registers too small" 438 ": %"PRIuMAX" < %"PRIuMAX"\n", 439 (uintmax_t)mmadr_size, (uintmax_t)gtt_off); 440 error = ENXIO; 441 goto fail1; 442 } 443 isc->size = gtt_off; 444 } else { 445 isc->size = mmadr_size; 446 } 447 isc->bst = isc->vga_pa.pa_memt; 448 error = bus_space_map(isc->bst, mmadr, isc->size, mmadr_flags, 449 &isc->bsh); 450 if (error) { 451 aprint_error_dev(self, "can't map MMIO registers: %d\n", 452 error); 453 error = ENXIO; 454 goto fail1; 455 } 456 457 /* Set up a chipset flush page if necessary. */ 458 switch (isc->chiptype) { 459 case CHIP_I915: 460 case CHIP_I965: 461 case CHIP_G33: 462 case CHIP_G4X: 463 error = agp_i810_setup_chipset_flush_page(sc); 464 if (error) { 465 aprint_error_dev(self, 466 "can't set up chipset flush page: %d\n", error); 467 goto fail2; 468 } 469 break; 470 } 471 472 /* 473 * XXX horrible hack to allow drm code to use our mapping 474 * of VGA chip registers 475 */ 476 agp_i810_vga_regbase = mmadr; 477 agp_i810_vga_bsh = isc->bsh; 478 479 /* Initialize the chipset. */ 480 error = agp_i810_init(sc); 481 if (error) 482 goto fail3; 483 484 /* Map the GTT, from either part of the MMIO region or its own BAR. */ 485 if (gtt_bar == 0) { 486 isc->gtt_bst = isc->bst; 487 if ((mmadr_size - gtt_off) < isc->gtt_size) { 488 aprint_error_dev(self, "GTTMMADR too small for GTT" 489 ": (%"PRIxMAX" - %"PRIxMAX") < %"PRIxMAX"\n", 490 (uintmax_t)mmadr_size, 491 (uintmax_t)gtt_off, 492 (uintmax_t)isc->gtt_size); 493 error = ENXIO; 494 goto fail4; 495 } 496 error = bus_space_map(isc->gtt_bst, (mmadr + gtt_off), 497 isc->gtt_size, mmadr_flags, &isc->gtt_bsh); 498 if (error) { 499 aprint_error_dev(self, "can't map GTT: %d\n", error); 500 error = ENXIO; 501 goto fail4; 502 } 503 } else { 504 bus_size_t gtt_bar_size; 505 /* 506 * All chipsets with a separate BAR for the GTT, namely 507 * the i915 and G33 families, have 32-bit GTT BARs. 508 * 509 * XXX [citation needed] 510 */ 511 if (pci_mapreg_map(&isc->vga_pa, gtt_bar, PCI_MAPREG_TYPE_MEM, 512 0, 513 &isc->gtt_bst, &isc->gtt_bsh, NULL, >t_bar_size)) { 514 aprint_error_dev(self, "can't map GTT\n"); 515 error = ENXIO; 516 goto fail4; 517 } 518 if (gtt_bar_size != isc->gtt_size) { 519 aprint_error_dev(self, 520 "BAR size %"PRIxMAX 521 " mismatches detected GTT size %"PRIxMAX 522 "; trusting BAR\n", 523 (uintmax_t)gtt_bar_size, 524 (uintmax_t)isc->gtt_size); 525 isc->gtt_size = gtt_bar_size; 526 } 527 } 528 529 /* Power management. (XXX Nothing to save on suspend? Fishy...) */ 530 if (!pmf_device_register(self, NULL, agp_i810_resume)) 531 aprint_error_dev(self, "can't establish power handler\n"); 532 533 /* Match the generic AGP code's autoconf output format. */ 534 aprint_normal("%s", device_xname(self)); 535 536 /* Success! */ 537 return 0; 538 539 fail5: __unused 540 pmf_device_deregister(self); 541 bus_space_unmap(isc->gtt_bst, isc->gtt_bsh, isc->gtt_size); 542 isc->gtt_size = 0; 543 fail4: 544 #if notyet 545 agp_i810_fini(sc); 546 #endif 547 fail3: switch (isc->chiptype) { 548 case CHIP_I915: 549 case CHIP_I965: 550 case CHIP_G33: 551 case CHIP_G4X: 552 agp_i810_teardown_chipset_flush_page(sc); 553 break; 554 } 555 fail2: bus_space_unmap(isc->bst, isc->bsh, isc->size); 556 isc->size = 0; 557 fail1: free(isc, M_AGP); 558 sc->as_chipc = NULL; 559 fail0: agp_generic_detach(sc); 560 KASSERT(error); 561 return error; 562 } 563 564 static int 565 agp_i810_setup_chipset_flush_page(struct agp_softc *sc) 566 { 567 struct agp_i810_softc *const isc = sc->as_chipc; 568 const pci_chipset_tag_t pc = sc->as_pc; 569 const pcitag_t tag = sc->as_tag; 570 pcireg_t lo, hi; 571 bus_addr_t addr, minaddr, maxaddr; 572 int error; 573 574 /* We always use memory-mapped I/O. */ 575 isc->flush_bst = isc->vga_pa.pa_memt; 576 577 /* No page allocated yet. */ 578 isc->flush_addr = 0; 579 580 /* Read the PCI config register: 4-byte on gen3, 8-byte on gen>=4. */ 581 if (isc->chiptype == CHIP_I915) { 582 addr = pci_conf_read(pc, tag, AGP_I915_IFPADDR); 583 minaddr = PAGE_SIZE; /* XXX PCIBIOS_MIN_MEM? */ 584 maxaddr = UINT32_MAX; 585 } else { 586 hi = pci_conf_read(pc, tag, AGP_I965_IFPADDR+4); 587 lo = pci_conf_read(pc, tag, AGP_I965_IFPADDR); 588 /* 589 * Convert to uint64_t, rather than bus_addr_t which 590 * may be 32-bit, to avoid undefined behaviour with a 591 * too-wide shift. Since the BIOS doesn't know whether 592 * the OS will run 64-bit or with PAE, it ought to 593 * configure at most a 32-bit physical address, so 594 * let's print a warning in case that happens. 595 */ 596 addr = ((uint64_t)hi << 32) | lo; 597 if (hi) { 598 aprint_error_dev(sc->as_dev, 599 "BIOS configured >32-bit flush page address" 600 ": %"PRIx64"\n", ((uint64_t)hi << 32) | lo); 601 #if __i386__ && !PAE 602 return EIO; 603 #endif 604 } 605 minaddr = PAGE_SIZE; /* XXX PCIBIOS_MIN_MEM? */ 606 maxaddr = MIN(UINT64_MAX, ~(bus_addr_t)0); 607 } 608 609 /* Allocate or map a pre-allocated a page for it. */ 610 if (ISSET(addr, 1)) { 611 /* BIOS allocated it for us. Use that. */ 612 error = bus_space_map(isc->flush_bst, addr & ~1, PAGE_SIZE, 0, 613 &isc->flush_bsh); 614 if (error) 615 return error; 616 } else { 617 /* None allocated. Allocate one. */ 618 error = bus_space_alloc(isc->flush_bst, minaddr, maxaddr, 619 PAGE_SIZE, PAGE_SIZE, 0, 0, 620 &isc->flush_addr, &isc->flush_bsh); 621 if (error) 622 return error; 623 KASSERT(isc->flush_addr != 0); 624 /* Write it into the PCI config register. */ 625 addr = isc->flush_addr | 1; 626 if (isc->chiptype == CHIP_I915) { 627 pci_conf_write(pc, tag, AGP_I915_IFPADDR, addr); 628 } else { 629 hi = __SHIFTOUT(addr, __BITS(63, 32)); 630 lo = __SHIFTOUT(addr, __BITS(31, 0)); 631 pci_conf_write(pc, tag, AGP_I965_IFPADDR+4, hi); 632 pci_conf_write(pc, tag, AGP_I965_IFPADDR, lo); 633 } 634 } 635 636 /* Success! */ 637 return 0; 638 } 639 640 static void 641 agp_i810_teardown_chipset_flush_page(struct agp_softc *sc) 642 { 643 struct agp_i810_softc *const isc = sc->as_chipc; 644 645 if (isc->flush_addr) { 646 /* If we allocated a page, clear it. */ 647 if (isc->chiptype == CHIP_I915) { 648 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR, 649 0); 650 } else { 651 pci_conf_write(sc->as_pc, sc->as_tag, 652 AGP_I965_IFPADDR, 0); 653 pci_conf_write(sc->as_pc, sc->as_tag, 654 AGP_I965_IFPADDR + 4, 0); 655 } 656 isc->flush_addr = 0; 657 bus_space_free(isc->flush_bst, isc->flush_bsh, 658 PAGE_SIZE); 659 } else { 660 /* Otherwise, just unmap the pre-allocated page. */ 661 bus_space_unmap(isc->flush_bst, isc->flush_bsh, PAGE_SIZE); 662 } 663 } 664 665 /* 666 * XXX horrible hack to allow drm code to use our mapping 667 * of VGA chip registers 668 */ 669 int 670 agp_i810_borrow(bus_addr_t base, bus_space_handle_t *hdlp) 671 { 672 673 if (!agp_i810_vga_regbase || base != agp_i810_vga_regbase) 674 return 0; 675 *hdlp = agp_i810_vga_bsh; 676 return 1; 677 } 678 679 static int 680 agp_i810_init(struct agp_softc *sc) 681 { 682 struct agp_i810_softc *isc; 683 int error; 684 685 isc = sc->as_chipc; 686 687 if (isc->chiptype == CHIP_I810) { 688 struct agp_gatt *gatt; 689 void *virtual; 690 int dummyseg; 691 692 /* Some i810s have on-chip memory called dcache */ 693 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 694 isc->dcache_size = 4 * 1024 * 1024; 695 else 696 isc->dcache_size = 0; 697 698 /* According to the specs the gatt on the i810 must be 64k */ 699 isc->gtt_size = 64 * 1024; 700 gatt = malloc(sizeof(*gatt), M_AGP, M_NOWAIT); 701 if (gatt == NULL) { 702 aprint_error_dev(sc->as_dev, 703 "can't malloc GATT record\n"); 704 error = ENOMEM; 705 goto fail0; 706 } 707 gatt->ag_entries = isc->gtt_size / sizeof(uint32_t); 708 error = agp_alloc_dmamem(sc->as_dmat, isc->gtt_size, 709 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical, 710 &gatt->ag_dmaseg, 1, &dummyseg); 711 if (error) { 712 aprint_error_dev(sc->as_dev, 713 "can't allocate memory for GTT: %d\n", error); 714 free(gatt, M_AGP); 715 goto fail0; 716 } 717 718 gatt->ag_virtual = (uint32_t *)virtual; 719 gatt->ag_size = gatt->ag_entries * sizeof(uint32_t); 720 memset(gatt->ag_virtual, 0, gatt->ag_size); 721 agp_flush_cache(); 722 723 /* Install the GATT. */ 724 isc->pgtblctl = gatt->ag_physical | 1; 725 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 726 isc->gatt = gatt; 727 } else if (isc->chiptype == CHIP_I830) { 728 /* The i830 automatically initializes the 128k gatt on boot. */ 729 /* XXX [citation needed] */ 730 pcireg_t reg; 731 u_int16_t gcc1; 732 733 isc->gtt_size = 128 * 1024; 734 735 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 736 gcc1 = (u_int16_t)(reg >> 16); 737 switch (gcc1 & AGP_I830_GCC1_GMS) { 738 case AGP_I830_GCC1_GMS_STOLEN_512: 739 isc->stolen = (512 - 132) * 1024 / 4096; 740 break; 741 case AGP_I830_GCC1_GMS_STOLEN_1024: 742 isc->stolen = (1024 - 132) * 1024 / 4096; 743 break; 744 case AGP_I830_GCC1_GMS_STOLEN_8192: 745 isc->stolen = (8192 - 132) * 1024 / 4096; 746 break; 747 default: 748 isc->stolen = 0; 749 aprint_error_dev(sc->as_dev, 750 "unknown memory configuration, disabling\n"); 751 error = ENXIO; 752 goto fail0; 753 } 754 755 if (isc->stolen > 0) { 756 aprint_normal_dev(sc->as_dev, 757 "detected %dk stolen memory\n", 758 isc->stolen * 4); 759 } 760 761 /* GATT address is already in there, make sure it's enabled */ 762 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 763 isc->pgtblctl |= 1; 764 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 765 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 766 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 || 767 isc->chiptype == CHIP_G4X) { 768 pcireg_t reg; 769 u_int32_t gtt_size, stolen; /* XXX kilobytes */ 770 u_int16_t gcc1; 771 772 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1); 773 gcc1 = (u_int16_t)(reg >> 16); 774 775 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 776 777 /* Stolen memory is set up at the beginning of the aperture by 778 * the BIOS, consisting of the GATT followed by 4kb for the 779 * BIOS display. 780 */ 781 switch (isc->chiptype) { 782 case CHIP_I855: 783 gtt_size = 128; 784 break; 785 case CHIP_I915: 786 gtt_size = 256; 787 break; 788 case CHIP_I965: 789 switch (isc->pgtblctl & AGP_I810_PGTBL_SIZE_MASK) { 790 case AGP_I810_PGTBL_SIZE_128KB: 791 case AGP_I810_PGTBL_SIZE_512KB: 792 gtt_size = 512; 793 break; 794 case AGP_I965_PGTBL_SIZE_1MB: 795 gtt_size = 1024; 796 break; 797 case AGP_I965_PGTBL_SIZE_2MB: 798 gtt_size = 2048; 799 break; 800 case AGP_I965_PGTBL_SIZE_1_5MB: 801 gtt_size = 1024 + 512; 802 break; 803 default: 804 aprint_error_dev(sc->as_dev, 805 "bad PGTBL size\n"); 806 error = ENXIO; 807 goto fail0; 808 } 809 break; 810 case CHIP_G33: 811 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 812 case AGP_G33_PGTBL_SIZE_1M: 813 gtt_size = 1024; 814 break; 815 case AGP_G33_PGTBL_SIZE_2M: 816 gtt_size = 2048; 817 break; 818 default: 819 aprint_error_dev(sc->as_dev, 820 "bad PGTBL size\n"); 821 error = ENXIO; 822 goto fail0; 823 } 824 break; 825 case CHIP_G4X: 826 gtt_size = 0; 827 break; 828 default: 829 panic("impossible chiptype %d", isc->chiptype); 830 } 831 832 /* 833 * XXX If I'm reading the datasheets right, this stolen 834 * memory detection logic is totally wrong. 835 */ 836 switch (gcc1 & AGP_I855_GCC1_GMS) { 837 case AGP_I855_GCC1_GMS_STOLEN_1M: 838 stolen = 1024; 839 break; 840 case AGP_I855_GCC1_GMS_STOLEN_4M: 841 stolen = 4 * 1024; 842 break; 843 case AGP_I855_GCC1_GMS_STOLEN_8M: 844 stolen = 8 * 1024; 845 break; 846 case AGP_I855_GCC1_GMS_STOLEN_16M: 847 stolen = 16 * 1024; 848 break; 849 case AGP_I855_GCC1_GMS_STOLEN_32M: 850 stolen = 32 * 1024; 851 break; 852 case AGP_I915_GCC1_GMS_STOLEN_48M: 853 stolen = 48 * 1024; 854 break; 855 case AGP_I915_GCC1_GMS_STOLEN_64M: 856 stolen = 64 * 1024; 857 break; 858 case AGP_G33_GCC1_GMS_STOLEN_128M: 859 stolen = 128 * 1024; 860 break; 861 case AGP_G33_GCC1_GMS_STOLEN_256M: 862 stolen = 256 * 1024; 863 break; 864 case AGP_G4X_GCC1_GMS_STOLEN_96M: 865 stolen = 96 * 1024; 866 break; 867 case AGP_G4X_GCC1_GMS_STOLEN_160M: 868 stolen = 160 * 1024; 869 break; 870 case AGP_G4X_GCC1_GMS_STOLEN_224M: 871 stolen = 224 * 1024; 872 break; 873 case AGP_G4X_GCC1_GMS_STOLEN_352M: 874 stolen = 352 * 1024; 875 break; 876 default: 877 aprint_error_dev(sc->as_dev, 878 "unknown memory configuration, disabling\n"); 879 error = ENXIO; 880 goto fail0; 881 } 882 883 switch (gcc1 & AGP_I855_GCC1_GMS) { 884 case AGP_I915_GCC1_GMS_STOLEN_48M: 885 case AGP_I915_GCC1_GMS_STOLEN_64M: 886 if (isc->chiptype != CHIP_I915 && 887 isc->chiptype != CHIP_I965 && 888 isc->chiptype != CHIP_G33 && 889 isc->chiptype != CHIP_G4X) 890 stolen = 0; 891 break; 892 case AGP_G33_GCC1_GMS_STOLEN_128M: 893 case AGP_G33_GCC1_GMS_STOLEN_256M: 894 if (isc->chiptype != CHIP_I965 && 895 isc->chiptype != CHIP_G33 && 896 isc->chiptype != CHIP_G4X) 897 stolen = 0; 898 break; 899 case AGP_G4X_GCC1_GMS_STOLEN_96M: 900 case AGP_G4X_GCC1_GMS_STOLEN_160M: 901 case AGP_G4X_GCC1_GMS_STOLEN_224M: 902 case AGP_G4X_GCC1_GMS_STOLEN_352M: 903 if (isc->chiptype != CHIP_I965 && 904 isc->chiptype != CHIP_G4X) 905 stolen = 0; 906 break; 907 } 908 909 isc->gtt_size = gtt_size * 1024; 910 911 /* BIOS space */ 912 /* XXX [citation needed] */ 913 gtt_size += 4; 914 915 /* XXX [citation needed] for this subtraction */ 916 isc->stolen = (stolen - gtt_size) * 1024 / 4096; 917 918 if (isc->stolen > 0) { 919 aprint_normal_dev(sc->as_dev, 920 "detected %dk stolen memory\n", 921 isc->stolen * 4); 922 } 923 924 /* GATT address is already in there, make sure it's enabled */ 925 isc->pgtblctl |= 1; 926 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 927 } 928 929 /* 930 * Make sure the chipset can see everything. 931 */ 932 agp_flush_cache(); 933 934 /* 935 * Publish what we found for kludgey drivers (I'm looking at 936 * you, drm). 937 */ 938 if (agp_i810_sc == NULL) 939 agp_i810_sc = sc; 940 else 941 aprint_error_dev(sc->as_dev, "agp already attached\n"); 942 943 /* Success! */ 944 return 0; 945 946 fail0: KASSERT(error); 947 return error; 948 } 949 950 #if 0 951 static int 952 agp_i810_detach(struct agp_softc *sc) 953 { 954 int error; 955 struct agp_i810_softc *isc = sc->as_chipc; 956 957 error = agp_generic_detach(sc); 958 if (error) 959 return error; 960 961 switch (isc->chiptype) { 962 case CHIP_I915: 963 case CHIP_I965: 964 case CHIP_G33: 965 case CHIP_G4X: 966 agp_i810_teardown_chipset_flush_page(sc); 967 break; 968 } 969 970 /* Clear the GATT base. */ 971 if (sc->chiptype == CHIP_I810) { 972 WRITE4(AGP_I810_PGTBL_CTL, 0); 973 } else { 974 unsigned int pgtblctl; 975 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 976 pgtblctl &= ~1; 977 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 978 } 979 980 if (sc->chiptype == CHIP_I810) { 981 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap, 982 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 983 free(isc->gatt, M_AGP); 984 } 985 986 return 0; 987 } 988 #endif 989 990 static u_int32_t 991 agp_i810_get_aperture(struct agp_softc *sc) 992 { 993 struct agp_i810_softc *isc = sc->as_chipc; 994 pcireg_t reg; 995 u_int32_t size; 996 u_int16_t miscc, gcc1; 997 998 size = 0; 999 1000 switch (isc->chiptype) { 1001 case CHIP_I810: 1002 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 1003 miscc = (u_int16_t)(reg >> 16); 1004 if ((miscc & AGP_I810_MISCC_WINSIZE) == 1005 AGP_I810_MISCC_WINSIZE_32) 1006 size = 32 * 1024 * 1024; 1007 else 1008 size = 64 * 1024 * 1024; 1009 break; 1010 case CHIP_I830: 1011 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 1012 gcc1 = (u_int16_t)(reg >> 16); 1013 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 1014 size = 64 * 1024 * 1024; 1015 else 1016 size = 128 * 1024 * 1024; 1017 break; 1018 case CHIP_I855: 1019 size = 128 * 1024 * 1024; 1020 break; 1021 case CHIP_I915: 1022 case CHIP_G33: 1023 case CHIP_G4X: 1024 size = sc->as_apsize; 1025 break; 1026 case CHIP_I965: 1027 size = 512 * 1024 * 1024; 1028 break; 1029 default: 1030 aprint_error(": Unknown chipset\n"); 1031 } 1032 1033 return size; 1034 } 1035 1036 static int 1037 agp_i810_set_aperture(struct agp_softc *sc __unused, 1038 uint32_t aperture __unused) 1039 { 1040 1041 return ENOSYS; 1042 } 1043 1044 static int 1045 agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 1046 { 1047 struct agp_i810_softc *isc = sc->as_chipc; 1048 1049 if (offset < 0 || offset >= ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) { 1050 #ifdef AGP_DEBUG 1051 printf("%s: failed: offset 0x%08x, shift %d, entries %d\n", 1052 device_xname(sc->as_dev), (int)offset, AGP_PAGE_SHIFT, 1053 isc->gtt_size/4); 1054 #endif 1055 return EINVAL; 1056 } 1057 1058 if (isc->chiptype != CHIP_I810) { 1059 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1060 #ifdef AGP_DEBUG 1061 printf("%s: trying to bind into stolen memory\n", 1062 device_xname(sc->as_dev)); 1063 #endif 1064 return EINVAL; 1065 } 1066 } 1067 1068 return agp_i810_write_gtt_entry(isc, offset, physical | 1); 1069 } 1070 1071 static int 1072 agp_i810_unbind_page(struct agp_softc *sc, off_t offset) 1073 { 1074 struct agp_i810_softc *isc = sc->as_chipc; 1075 1076 if (offset < 0 || offset >= ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) 1077 return EINVAL; 1078 1079 if (isc->chiptype != CHIP_I810 ) { 1080 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1081 #ifdef AGP_DEBUG 1082 printf("%s: trying to unbind from stolen memory\n", 1083 device_xname(sc->as_dev)); 1084 #endif 1085 return EINVAL; 1086 } 1087 } 1088 1089 return agp_i810_write_gtt_entry(isc, offset, 0); 1090 } 1091 1092 /* 1093 * Writing via memory mapped registers already flushes all TLBs. 1094 */ 1095 static void 1096 agp_i810_flush_tlb(struct agp_softc *sc) 1097 { 1098 } 1099 1100 static int 1101 agp_i810_enable(struct agp_softc *sc, u_int32_t mode) 1102 { 1103 1104 return 0; 1105 } 1106 1107 #define AGP_I810_MEMTYPE_MAIN 0 1108 #define AGP_I810_MEMTYPE_DCACHE 1 1109 #define AGP_I810_MEMTYPE_HWCURSOR 2 1110 1111 static struct agp_memory * 1112 agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size) 1113 { 1114 struct agp_i810_softc *isc = sc->as_chipc; 1115 struct agp_memory *mem; 1116 int error; 1117 1118 #ifdef AGP_DEBUG 1119 printf("AGP: alloc(%d, 0x%x)\n", type, (int) size); 1120 #endif 1121 1122 if (size <= 0) 1123 return NULL; 1124 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 1125 return NULL; 1126 KASSERT(sc->as_allocated <= sc->as_maxmem); 1127 if (size > (sc->as_maxmem - sc->as_allocated)) 1128 return NULL; 1129 switch (type) { 1130 case AGP_I810_MEMTYPE_MAIN: 1131 break; 1132 case AGP_I810_MEMTYPE_DCACHE: 1133 if (isc->chiptype != CHIP_I810) 1134 return NULL; 1135 if (size != isc->dcache_size) 1136 return NULL; 1137 break; 1138 case AGP_I810_MEMTYPE_HWCURSOR: 1139 if ((size != AGP_PAGE_SIZE) && 1140 (size != AGP_PAGE_SIZE*4)) 1141 return NULL; 1142 break; 1143 default: 1144 return NULL; 1145 } 1146 1147 mem = malloc(sizeof(*mem), M_AGP, M_WAITOK|M_ZERO); 1148 if (mem == NULL) 1149 goto fail0; 1150 mem->am_id = sc->as_nextid++; 1151 mem->am_size = size; 1152 mem->am_type = type; 1153 1154 switch (type) { 1155 case AGP_I810_MEMTYPE_MAIN: 1156 error = bus_dmamap_create(sc->as_dmat, size, 1157 (size >> AGP_PAGE_SHIFT) + 1, size, 0, BUS_DMA_WAITOK, 1158 &mem->am_dmamap); 1159 if (error) 1160 goto fail1; 1161 break; 1162 case AGP_I810_MEMTYPE_DCACHE: 1163 break; 1164 case AGP_I810_MEMTYPE_HWCURSOR: 1165 mem->am_dmaseg = malloc(sizeof(*mem->am_dmaseg), M_AGP, 1166 M_WAITOK); 1167 error = agp_alloc_dmamem(sc->as_dmat, size, 0, &mem->am_dmamap, 1168 &mem->am_virtual, &mem->am_physical, mem->am_dmaseg, 1, 1169 &mem->am_nseg); 1170 if (error) { 1171 free(mem->am_dmaseg, M_AGP); 1172 goto fail1; 1173 } 1174 (void)memset(mem->am_virtual, 0, size); 1175 break; 1176 default: 1177 panic("invalid agp memory type: %d", type); 1178 } 1179 1180 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link); 1181 sc->as_allocated += size; 1182 1183 return mem; 1184 1185 fail1: free(mem, M_AGP); 1186 fail0: return NULL; 1187 } 1188 1189 static int 1190 agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem) 1191 { 1192 1193 if (mem->am_is_bound) 1194 return EBUSY; 1195 1196 switch (mem->am_type) { 1197 case AGP_I810_MEMTYPE_MAIN: 1198 bus_dmamap_destroy(sc->as_dmat, mem->am_dmamap); 1199 break; 1200 case AGP_I810_MEMTYPE_DCACHE: 1201 break; 1202 case AGP_I810_MEMTYPE_HWCURSOR: 1203 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap, 1204 mem->am_virtual, mem->am_dmaseg, mem->am_nseg); 1205 free(mem->am_dmaseg, M_AGP); 1206 break; 1207 default: 1208 panic("invalid agp i810 memory type: %d", mem->am_type); 1209 } 1210 1211 sc->as_allocated -= mem->am_size; 1212 TAILQ_REMOVE(&sc->as_memory, mem, am_link); 1213 free(mem, M_AGP); 1214 1215 return 0; 1216 } 1217 1218 static int 1219 agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem, 1220 off_t offset) 1221 { 1222 struct agp_i810_softc *isc = sc->as_chipc; 1223 uint32_t pgtblctl; 1224 int error; 1225 1226 if (mem->am_is_bound) 1227 return EINVAL; 1228 1229 /* 1230 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 1231 * X server for mysterious reasons which leads to crashes if we write 1232 * to the GTT through the MMIO window. 1233 * Until the issue is solved, simply restore it. 1234 */ 1235 pgtblctl = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL); 1236 if (pgtblctl != isc->pgtblctl) { 1237 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%"PRIx32 1238 " - fixing\n", pgtblctl); 1239 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 1240 isc->pgtblctl); 1241 } 1242 1243 switch (mem->am_type) { 1244 case AGP_I810_MEMTYPE_MAIN: 1245 error = agp_i810_bind_memory_main(sc, mem, offset); 1246 break; 1247 case AGP_I810_MEMTYPE_DCACHE: 1248 error = agp_i810_bind_memory_dcache(sc, mem, offset); 1249 break; 1250 case AGP_I810_MEMTYPE_HWCURSOR: 1251 error = agp_i810_bind_memory_hwcursor(sc, mem, offset); 1252 break; 1253 default: 1254 panic("invalid agp i810 memory type: %d", mem->am_type); 1255 } 1256 if (error) 1257 return error; 1258 1259 /* Success! */ 1260 mem->am_is_bound = 1; 1261 return 0; 1262 } 1263 1264 static int 1265 agp_i810_bind_memory_main(struct agp_softc *sc, struct agp_memory *mem, 1266 off_t offset) 1267 { 1268 struct agp_i810_softc *const isc = sc->as_chipc; 1269 int nseg; 1270 uint32_t i, j; 1271 unsigned seg; 1272 bus_addr_t addr; 1273 bus_size_t len; 1274 int error; 1275 1276 /* Ensure we have a sane size/offset that will fit. */ 1277 if (offset < 0) 1278 return EINVAL; 1279 if (offset & (AGP_PAGE_SIZE - 1)) 1280 return EINVAL; 1281 if (mem->am_size > ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) 1282 return EINVAL; 1283 if (offset > (((isc->gtt_size/4) << AGP_PAGE_SHIFT) - 1284 mem->am_size)) 1285 return EINVAL; 1286 1287 /* Allocate an array of DMA segments. */ 1288 nseg = (mem->am_size >> AGP_PAGE_SHIFT); 1289 if (nseg > (SIZE_MAX / sizeof(*mem->am_dmaseg))) { 1290 error = ENOMEM; 1291 goto fail0; 1292 } 1293 mem->am_dmaseg = malloc(nseg*sizeof(*mem->am_dmaseg), M_AGP, M_WAITOK); 1294 1295 /* Allocate DMA-safe physical segments. */ 1296 error = bus_dmamem_alloc(sc->as_dmat, mem->am_size, PAGE_SIZE, 1297 0, mem->am_dmaseg, nseg, &mem->am_nseg, BUS_DMA_WAITOK); 1298 if (error) 1299 goto fail1; 1300 KASSERT(mem->am_nseg <= nseg); 1301 1302 /* Shrink the array of DMA segments if we can. */ 1303 if (mem->am_nseg < nseg) { 1304 mem->am_dmaseg = realloc(mem->am_dmaseg, mem->am_nseg, M_AGP, 1305 M_WAITOK); 1306 nseg = mem->am_nseg; 1307 } 1308 1309 /* Load the DMA map. */ 1310 error = bus_dmamap_load_raw(sc->as_dmat, mem->am_dmamap, 1311 mem->am_dmaseg, mem->am_nseg, mem->am_size, BUS_DMA_WAITOK); 1312 if (error) 1313 goto fail2; 1314 1315 /* Bind the pages in the GTT. */ 1316 i = 0; 1317 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0); 1318 for (seg = 0; seg < mem->am_dmamap->dm_nsegs; seg++) { 1319 KASSERT((offset + i) < mem->am_size); 1320 addr = mem->am_dmamap->dm_segs[seg].ds_addr; 1321 len = MIN(mem->am_dmamap->dm_segs[seg].ds_len, 1322 (mem->am_size - (offset + i))); 1323 do { 1324 KASSERT(0 < len); 1325 KASSERT((len & (AGP_PAGE_SIZE - 1)) == 0); 1326 KASSERT((offset + i) < (mem->am_size - len)); 1327 error = agp_i810_bind_page(sc, offset + i, addr); 1328 if (error) 1329 goto fail3; 1330 i += AGP_PAGE_SIZE; 1331 addr += AGP_PAGE_SIZE; 1332 len -= AGP_PAGE_SIZE; 1333 } while (0 < len); 1334 } 1335 1336 /* Success! */ 1337 mem->am_offset = offset; 1338 return 0; 1339 1340 fail3: for (j = 0; j < i; j += AGP_PAGE_SIZE) 1341 (void)agp_i810_unbind_page(sc, offset + j); 1342 bus_dmamap_unload(sc->as_dmat, mem->am_dmamap); 1343 fail2: bus_dmamem_free(sc->as_dmat, mem->am_dmaseg, mem->am_nseg); 1344 fail1: free(mem->am_dmaseg, M_AGP); 1345 mem->am_dmaseg = NULL; 1346 mem->am_nseg = 0; 1347 fail0: KASSERT(error); 1348 return error; 1349 } 1350 1351 #define I810_GTT_PTE_VALID 0x01 1352 #define I810_GTT_PTE_DCACHE 0x02 1353 1354 static int 1355 agp_i810_bind_memory_dcache(struct agp_softc *sc, struct agp_memory *mem, 1356 off_t offset) 1357 { 1358 struct agp_i810_softc *const isc __diagused = sc->as_chipc; 1359 uint32_t i, j; 1360 int error; 1361 1362 KASSERT(isc->chiptype == CHIP_I810); 1363 1364 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0); 1365 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 1366 /* XXX No offset? */ 1367 error = agp_i810_write_gtt_entry(isc, i, 1368 i | I810_GTT_PTE_VALID | I810_GTT_PTE_DCACHE); 1369 if (error) 1370 goto fail0; 1371 } 1372 1373 /* Success! */ 1374 return 0; 1375 1376 fail0: for (j = 0; j < i; j += AGP_PAGE_SIZE) 1377 (void)agp_i810_unbind_page(sc, offset + j); 1378 return error; 1379 } 1380 1381 static int 1382 agp_i810_bind_memory_hwcursor(struct agp_softc *sc, struct agp_memory *mem, 1383 off_t offset) 1384 { 1385 const bus_addr_t pa = mem->am_physical; 1386 uint32_t i, j; 1387 int error; 1388 1389 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0); 1390 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 1391 error = agp_i810_bind_page(sc, offset + i, pa + i); 1392 if (error) 1393 goto fail0; 1394 } 1395 1396 /* Success! */ 1397 mem->am_offset = offset; 1398 return 0; 1399 1400 fail0: for (j = 0; j < i; j += AGP_PAGE_SIZE) 1401 (void)agp_i810_unbind_page(sc, offset + j); 1402 return error; 1403 } 1404 1405 static int 1406 agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem) 1407 { 1408 struct agp_i810_softc *isc = sc->as_chipc; 1409 u_int32_t i; 1410 1411 if (!mem->am_is_bound) 1412 return EINVAL; 1413 1414 switch (mem->am_type) { 1415 case AGP_I810_MEMTYPE_MAIN: 1416 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1417 (void)agp_i810_unbind_page(sc, mem->am_offset + i); 1418 bus_dmamap_unload(sc->as_dmat, mem->am_dmamap); 1419 bus_dmamem_free(sc->as_dmat, mem->am_dmaseg, mem->am_nseg); 1420 free(mem->am_dmaseg, M_AGP); 1421 mem->am_offset = 0; 1422 break; 1423 case AGP_I810_MEMTYPE_DCACHE: 1424 KASSERT(isc->chiptype == CHIP_I810); 1425 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1426 (void)agp_i810_write_gtt_entry(isc, i, 0); 1427 break; 1428 case AGP_I810_MEMTYPE_HWCURSOR: 1429 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1430 (void)agp_i810_unbind_page(sc, mem->am_offset + i); 1431 mem->am_offset = 0; 1432 break; 1433 default: 1434 panic("invalid agp i810 memory type: %d", mem->am_type); 1435 } 1436 1437 mem->am_is_bound = 0; 1438 return 0; 1439 } 1440 1441 static bool 1442 agp_i810_resume(device_t dv, const pmf_qual_t *qual) 1443 { 1444 struct agp_softc *sc = device_private(dv); 1445 struct agp_i810_softc *isc = sc->as_chipc; 1446 1447 /* 1448 * XXX Nothing uses this! Save on suspend, restore on resume? 1449 */ 1450 isc->pgtblctl_resume_hack = READ4(AGP_I810_PGTBL_CTL); 1451 agp_flush_cache(); 1452 1453 return true; 1454 } 1455
Indexes created Wed Sep 24 02:09:48 GMT 2025