agp_i810.c revision 1.98
1 /* $NetBSD: agp_i810.c,v 1.98 2014/06/12 14:49:02 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.98 2014/06/12 14:49:02 riastradh Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/proc.h> 40 #include <sys/device.h> 41 #include <sys/conf.h> 42 #include <sys/xcall.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcidevs.h> 47 #include <dev/pci/agpvar.h> 48 #include <dev/pci/agpreg.h> 49 #include <dev/pci/agp_i810var.h> 50 51 #include <sys/agpio.h> 52 53 #include <sys/bus.h> 54 55 #include "agp_intel.h" 56 57 struct agp_softc *agp_i810_sc = NULL; 58 59 #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off) 60 #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off) 61 #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v) 62 63 #define CHIP_I810 0 /* i810/i815 */ 64 #define CHIP_I830 1 /* 830M/845G */ 65 #define CHIP_I855 2 /* 852GM/855GM/865G */ 66 #define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */ 67 #define CHIP_I965 4 /* 965Q/965PM */ 68 #define CHIP_G33 5 /* G33/Q33/Q35 */ 69 #define CHIP_G4X 6 /* G45/Q45 */ 70 71 /* XXX hack, see below */ 72 static bus_addr_t agp_i810_vga_regbase; 73 static bus_space_handle_t agp_i810_vga_bsh; 74 75 static u_int32_t agp_i810_get_aperture(struct agp_softc *); 76 static int agp_i810_set_aperture(struct agp_softc *, u_int32_t); 77 static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t); 78 static int agp_i810_unbind_page(struct agp_softc *, off_t); 79 static void agp_i810_flush_tlb(struct agp_softc *); 80 static int agp_i810_enable(struct agp_softc *, u_int32_t mode); 81 static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int, 82 vsize_t); 83 static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *); 84 static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *, 85 off_t); 86 static int agp_i810_bind_memory_main(struct agp_softc *, struct agp_memory *, 87 off_t); 88 static int agp_i810_bind_memory_dcache(struct agp_softc *, struct agp_memory *, 89 off_t); 90 static int agp_i810_bind_memory_hwcursor(struct agp_softc *, 91 struct agp_memory *, off_t); 92 static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *); 93 94 static bool agp_i810_resume(device_t, const pmf_qual_t *); 95 static int agp_i810_init(struct agp_softc *); 96 97 static int agp_i810_setup_chipset_flush_page(struct agp_softc *); 98 static void agp_i810_teardown_chipset_flush_page(struct agp_softc *); 99 static int agp_i810_init(struct agp_softc *); 100 101 static struct agp_methods agp_i810_methods = { 102 agp_i810_get_aperture, 103 agp_i810_set_aperture, 104 agp_i810_bind_page, 105 agp_i810_unbind_page, 106 agp_i810_flush_tlb, 107 agp_i810_enable, 108 agp_i810_alloc_memory, 109 agp_i810_free_memory, 110 agp_i810_bind_memory, 111 agp_i810_unbind_memory, 112 }; 113 114 int 115 agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, bus_addr_t v) 116 { 117 u_int32_t pte; 118 119 /* Bits 11:4 (physical start address extension) should be zero. */ 120 if ((v & 0xff0) != 0) 121 return EINVAL; 122 123 pte = (u_int32_t)v; 124 /* 125 * We need to massage the pte if bus_addr_t is wider than 32 bits. 126 * The compiler isn't smart enough, hence the casts to uintmax_t. 127 */ 128 if (sizeof(bus_addr_t) > sizeof(u_int32_t)) { 129 /* 965+ can do 36-bit addressing, add in the extra bits. */ 130 if (isc->chiptype == CHIP_I965 || 131 isc->chiptype == CHIP_G33 || 132 isc->chiptype == CHIP_G4X) { 133 if (((uintmax_t)v >> 36) != 0) 134 return EINVAL; 135 pte |= (v >> 28) & 0xf0; 136 } else { 137 if (((uintmax_t)v >> 32) != 0) 138 return EINVAL; 139 } 140 } 141 142 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh, 143 4*(off >> AGP_PAGE_SHIFT), pte); 144 145 return 0; 146 } 147 148 void 149 agp_i810_post_gtt_entry(struct agp_i810_softc *isc, off_t off) 150 { 151 152 (void)bus_space_read_4(isc->gtt_bst, isc->gtt_bsh, 153 4*(off >> AGP_PAGE_SHIFT)); 154 } 155 156 static void 157 agp_flush_cache_xc(void *a __unused, void *b __unused) 158 { 159 160 agp_flush_cache(); 161 } 162 163 void 164 agp_i810_chipset_flush(struct agp_i810_softc *isc) 165 { 166 unsigned int timo = 20000; /* * 50 us = 1 s */ 167 168 switch (isc->chiptype) { 169 case CHIP_I810: 170 break; 171 case CHIP_I830: 172 case CHIP_I855: 173 /* 174 * Flush all CPU caches. If we're cold, we can't run 175 * xcalls, but there should be only one CPU up, so 176 * flushing only the local CPU's cache should suffice. 177 * 178 * XXX Come to think of it, do these chipsets appear in 179 * any multi-CPU systems? 180 */ 181 if (cold) 182 agp_flush_cache(); 183 else 184 xc_wait(xc_broadcast(0, &agp_flush_cache_xc, 185 NULL, NULL)); 186 WRITE4(AGP_I830_HIC, READ4(AGP_I830_HIC) | __BIT(31)); 187 while (ISSET(READ4(AGP_I830_HIC), __BIT(31))) { 188 if (timo-- == 0) 189 break; 190 DELAY(50); 191 } 192 break; 193 case CHIP_I915: 194 case CHIP_I965: 195 case CHIP_G33: 196 case CHIP_G4X: 197 bus_space_write_4(isc->flush_bst, isc->flush_bsh, 0, 1); 198 break; 199 } 200 } 201 202 /* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */ 203 static int 204 agp_i810_vgamatch(const struct pci_attach_args *pa) 205 { 206 207 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 208 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 209 return (0); 210 211 switch (PCI_PRODUCT(pa->pa_id)) { 212 case PCI_PRODUCT_INTEL_82810_GC: 213 case PCI_PRODUCT_INTEL_82810_DC100_GC: 214 case PCI_PRODUCT_INTEL_82810E_GC: 215 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 216 case PCI_PRODUCT_INTEL_82830MP_IV: 217 case PCI_PRODUCT_INTEL_82845G_IGD: 218 case PCI_PRODUCT_INTEL_82855GM_IGD: 219 case PCI_PRODUCT_INTEL_82865_IGD: 220 case PCI_PRODUCT_INTEL_82915G_IGD: 221 case PCI_PRODUCT_INTEL_82915GM_IGD: 222 case PCI_PRODUCT_INTEL_82945P_IGD: 223 case PCI_PRODUCT_INTEL_82945GM_IGD: 224 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 225 case PCI_PRODUCT_INTEL_82945GME_IGD: 226 case PCI_PRODUCT_INTEL_E7221_IGD: 227 case PCI_PRODUCT_INTEL_82965Q_IGD: 228 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 229 case PCI_PRODUCT_INTEL_82965PM_IGD: 230 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 231 case PCI_PRODUCT_INTEL_82G33_IGD: 232 case PCI_PRODUCT_INTEL_82G33_IGD_1: 233 case PCI_PRODUCT_INTEL_82965G_IGD: 234 case PCI_PRODUCT_INTEL_82965G_IGD_1: 235 case PCI_PRODUCT_INTEL_82965GME_IGD: 236 case PCI_PRODUCT_INTEL_82Q35_IGD: 237 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 238 case PCI_PRODUCT_INTEL_82Q33_IGD: 239 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 240 case PCI_PRODUCT_INTEL_82G35_IGD: 241 case PCI_PRODUCT_INTEL_82G35_IGD_1: 242 case PCI_PRODUCT_INTEL_82946GZ_IGD: 243 case PCI_PRODUCT_INTEL_82GM45_IGD: 244 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 245 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 246 case PCI_PRODUCT_INTEL_82Q45_IGD: 247 case PCI_PRODUCT_INTEL_82G45_IGD: 248 case PCI_PRODUCT_INTEL_82G41_IGD: 249 case PCI_PRODUCT_INTEL_82B43_IGD: 250 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 251 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 252 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 253 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 254 return (1); 255 } 256 257 return (0); 258 } 259 260 static int 261 agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg) 262 { 263 /* 264 * Find the aperture. Don't map it (yet), this would 265 * eat KVA. 266 */ 267 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg, 268 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize, 269 &sc->as_apflags) != 0) 270 return ENXIO; 271 272 sc->as_apt = pa->pa_memt; 273 274 return 0; 275 } 276 277 int 278 agp_i810_attach(device_t parent, device_t self, void *aux) 279 { 280 struct agp_softc *sc = device_private(self); 281 struct agp_i810_softc *isc; 282 int apbase, mmadr_bar, gtt_bar; 283 int mmadr_type, mmadr_flags; 284 bus_addr_t mmadr; 285 bus_size_t mmadr_size, gtt_off; 286 int error; 287 288 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 289 if (isc == NULL) { 290 aprint_error(": can't allocate chipset-specific softc\n"); 291 error = ENOMEM; 292 goto fail0; 293 } 294 sc->as_chipc = isc; 295 sc->as_methods = &agp_i810_methods; 296 297 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) { 298 #if NAGP_INTEL > 0 299 const struct pci_attach_args *pa = aux; 300 301 switch (PCI_PRODUCT(pa->pa_id)) { 302 case PCI_PRODUCT_INTEL_82840_HB: 303 case PCI_PRODUCT_INTEL_82865_HB: 304 case PCI_PRODUCT_INTEL_82845G_DRAM: 305 case PCI_PRODUCT_INTEL_82815_FULL_HUB: 306 case PCI_PRODUCT_INTEL_82855GM_MCH: 307 free(isc, M_AGP); 308 return agp_intel_attach(parent, self, aux); 309 } 310 #endif 311 aprint_error(": can't find internal VGA" 312 " config space\n"); 313 error = ENOENT; 314 goto fail1; 315 } 316 317 /* XXXfvdl */ 318 sc->as_dmat = isc->vga_pa.pa_dmat; 319 320 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 321 case PCI_PRODUCT_INTEL_82810_GC: 322 case PCI_PRODUCT_INTEL_82810_DC100_GC: 323 case PCI_PRODUCT_INTEL_82810E_GC: 324 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH: 325 isc->chiptype = CHIP_I810; 326 aprint_normal(": i810-family chipset\n"); 327 break; 328 case PCI_PRODUCT_INTEL_82830MP_IV: 329 case PCI_PRODUCT_INTEL_82845G_IGD: 330 isc->chiptype = CHIP_I830; 331 aprint_normal(": i830-family chipset\n"); 332 break; 333 case PCI_PRODUCT_INTEL_82855GM_IGD: 334 case PCI_PRODUCT_INTEL_82865_IGD: 335 isc->chiptype = CHIP_I855; 336 aprint_normal(": i855-family chipset\n"); 337 break; 338 case PCI_PRODUCT_INTEL_82915G_IGD: 339 case PCI_PRODUCT_INTEL_82915GM_IGD: 340 case PCI_PRODUCT_INTEL_82945P_IGD: 341 case PCI_PRODUCT_INTEL_82945GM_IGD: 342 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 343 case PCI_PRODUCT_INTEL_82945GME_IGD: 344 case PCI_PRODUCT_INTEL_E7221_IGD: 345 case PCI_PRODUCT_INTEL_PINEVIEW_IGD: 346 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD: 347 isc->chiptype = CHIP_I915; 348 aprint_normal(": i915-family chipset\n"); 349 break; 350 case PCI_PRODUCT_INTEL_82965Q_IGD: 351 case PCI_PRODUCT_INTEL_82965Q_IGD_1: 352 case PCI_PRODUCT_INTEL_82965PM_IGD: 353 case PCI_PRODUCT_INTEL_82965PM_IGD_1: 354 case PCI_PRODUCT_INTEL_82965G_IGD: 355 case PCI_PRODUCT_INTEL_82965G_IGD_1: 356 case PCI_PRODUCT_INTEL_82965GME_IGD: 357 case PCI_PRODUCT_INTEL_82946GZ_IGD: 358 case PCI_PRODUCT_INTEL_82G35_IGD: 359 case PCI_PRODUCT_INTEL_82G35_IGD_1: 360 isc->chiptype = CHIP_I965; 361 aprint_normal(": i965-family chipset\n"); 362 break; 363 case PCI_PRODUCT_INTEL_82Q35_IGD: 364 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 365 case PCI_PRODUCT_INTEL_82G33_IGD: 366 case PCI_PRODUCT_INTEL_82G33_IGD_1: 367 case PCI_PRODUCT_INTEL_82Q33_IGD: 368 case PCI_PRODUCT_INTEL_82Q33_IGD_1: 369 isc->chiptype = CHIP_G33; 370 aprint_normal(": G33-family chipset\n"); 371 break; 372 case PCI_PRODUCT_INTEL_82GM45_IGD: 373 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 374 case PCI_PRODUCT_INTEL_82IGD_E_IGD: 375 case PCI_PRODUCT_INTEL_82Q45_IGD: 376 case PCI_PRODUCT_INTEL_82G45_IGD: 377 case PCI_PRODUCT_INTEL_82G41_IGD: 378 case PCI_PRODUCT_INTEL_82B43_IGD: 379 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD: 380 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD: 381 isc->chiptype = CHIP_G4X; 382 aprint_normal(": G4X-family chipset\n"); 383 break; 384 } 385 aprint_naive("\n"); 386 387 mmadr_type = PCI_MAPREG_TYPE_MEM; 388 switch (isc->chiptype) { 389 case CHIP_I915: 390 case CHIP_G33: 391 apbase = AGP_I915_GMADR; 392 mmadr_bar = AGP_I915_MMADR; 393 isc->size = 2*1024*1024; 394 gtt_bar = AGP_I915_GTTADR; 395 gtt_off = ~(bus_addr_t)0; /* XXXGCC */ 396 break; 397 case CHIP_I965: 398 apbase = AGP_I965_GMADR; 399 mmadr_bar = AGP_I965_MMADR; 400 mmadr_type |= PCI_MAPREG_MEM_TYPE_64BIT; 401 isc->size = 2*1024*1024; 402 gtt_bar = 0; 403 gtt_off = AGP_I965_GTT; 404 break; 405 case CHIP_G4X: 406 apbase = AGP_I965_GMADR; 407 mmadr_bar = AGP_I965_MMADR; 408 mmadr_type |= PCI_MAPREG_MEM_TYPE_64BIT; 409 isc->size = 2*1024*1024; 410 gtt_bar = 0; 411 gtt_off = AGP_G4X_GTT; 412 break; 413 default: 414 apbase = AGP_I810_GMADR; 415 mmadr_bar = AGP_I810_MMADR; 416 isc->size = 512*1024; 417 gtt_bar = 0; 418 gtt_off = AGP_I810_GTT; 419 break; 420 } 421 422 /* Map (or, rather, find the address and size of) the aperture. */ 423 if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) 424 error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase); 425 else 426 error = agp_map_aperture(&isc->vga_pa, sc, apbase); 427 if (error) { 428 aprint_error_dev(self, "can't map aperture: %d\n", error); 429 goto fail1; 430 } 431 432 /* Map the memory-mapped I/O registers, or the non-GTT part. */ 433 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, mmadr_bar, 434 mmadr_type, &mmadr, &mmadr_size, &mmadr_flags)) { 435 aprint_error_dev(self, "can't find MMIO registers\n"); 436 error = ENXIO; 437 goto fail1; 438 } 439 if (mmadr_size < isc->size) { 440 aprint_error_dev(self, "MMIO registers too small" 441 ": %"PRIuMAX" < %"PRIuMAX"\n", 442 (uintmax_t)mmadr_size, (uintmax_t)isc->size); 443 error = ENXIO; 444 goto fail1; 445 } 446 isc->bst = isc->vga_pa.pa_memt; 447 error = bus_space_map(isc->bst, mmadr, isc->size, mmadr_flags, 448 &isc->bsh); 449 if (error) { 450 aprint_error_dev(self, "can't map MMIO registers: %d\n", 451 error); 452 error = ENXIO; 453 goto fail1; 454 } 455 456 /* Set up a chipset flush page if necessary. */ 457 switch (isc->chiptype) { 458 case CHIP_I915: 459 case CHIP_I965: 460 case CHIP_G33: 461 case CHIP_G4X: 462 error = agp_i810_setup_chipset_flush_page(sc); 463 if (error) { 464 aprint_error_dev(self, 465 "can't set up chipset flush page: %d\n", error); 466 goto fail2; 467 } 468 break; 469 } 470 471 /* 472 * XXX horrible hack to allow drm code to use our mapping 473 * of VGA chip registers 474 */ 475 agp_i810_vga_regbase = mmadr; 476 agp_i810_vga_bsh = isc->bsh; 477 478 /* Initialize the chipset. */ 479 error = agp_i810_init(sc); 480 if (error) 481 goto fail3; 482 483 /* Map the GTT, from either part of the MMIO region or its own BAR. */ 484 if (gtt_bar == 0) { 485 isc->gtt_bst = isc->bst; 486 if ((mmadr_size - gtt_off) < isc->gtt_size) { 487 aprint_error_dev(self, "GTTMMADR too small for GTT" 488 ": (%"PRIxMAX" - %"PRIxMAX") < %"PRIxMAX"\n", 489 (uintmax_t)mmadr_size, 490 (uintmax_t)gtt_off, 491 (uintmax_t)isc->gtt_size); 492 error = ENXIO; 493 goto fail4; 494 } 495 /* 496 * Map the GTT separately if we can, so that we can map 497 * it prefetchable, but in early models, there are MMIO 498 * registers before and after the GTT, so we can only 499 * take a subregion. 500 */ 501 if (isc->size < gtt_off) 502 error = bus_space_map(isc->gtt_bst, (mmadr + gtt_off), 503 isc->gtt_size, mmadr_flags, &isc->gtt_bsh); 504 else 505 error = bus_space_subregion(isc->bst, isc->bsh, 506 gtt_off, isc->gtt_size, &isc->gtt_bsh); 507 if (error) { 508 aprint_error_dev(self, "can't map GTT: %d\n", error); 509 error = ENXIO; 510 goto fail4; 511 } 512 } else { 513 bus_size_t gtt_bar_size; 514 /* 515 * All chipsets with a separate BAR for the GTT, namely 516 * the i915 and G33 families, have 32-bit GTT BARs. 517 * 518 * XXX [citation needed] 519 */ 520 if (pci_mapreg_map(&isc->vga_pa, gtt_bar, PCI_MAPREG_TYPE_MEM, 521 0, 522 &isc->gtt_bst, &isc->gtt_bsh, NULL, >t_bar_size)) { 523 aprint_error_dev(self, "can't map GTT\n"); 524 error = ENXIO; 525 goto fail4; 526 } 527 if (gtt_bar_size != isc->gtt_size) { 528 aprint_error_dev(self, 529 "BAR size %"PRIxMAX 530 " mismatches detected GTT size %"PRIxMAX 531 "; trusting BAR\n", 532 (uintmax_t)gtt_bar_size, 533 (uintmax_t)isc->gtt_size); 534 isc->gtt_size = gtt_bar_size; 535 } 536 } 537 538 /* Power management. (XXX Nothing to save on suspend? Fishy...) */ 539 if (!pmf_device_register(self, NULL, agp_i810_resume)) 540 aprint_error_dev(self, "can't establish power handler\n"); 541 542 /* Match the generic AGP code's autoconf output format. */ 543 aprint_normal("%s", device_xname(self)); 544 545 /* Success! */ 546 return 0; 547 548 fail5: __unused 549 pmf_device_deregister(self); 550 if ((gtt_bar != 0) || (isc->size < gtt_off)) 551 bus_space_unmap(isc->gtt_bst, isc->gtt_bsh, isc->gtt_size); 552 isc->gtt_size = 0; 553 fail4: 554 #if notyet 555 agp_i810_fini(sc); 556 #endif 557 fail3: switch (isc->chiptype) { 558 case CHIP_I915: 559 case CHIP_I965: 560 case CHIP_G33: 561 case CHIP_G4X: 562 agp_i810_teardown_chipset_flush_page(sc); 563 break; 564 } 565 fail2: bus_space_unmap(isc->bst, isc->bsh, isc->size); 566 isc->size = 0; 567 fail1: free(isc, M_AGP); 568 sc->as_chipc = NULL; 569 fail0: agp_generic_detach(sc); 570 KASSERT(error); 571 return error; 572 } 573 574 static int 575 agp_i810_setup_chipset_flush_page(struct agp_softc *sc) 576 { 577 struct agp_i810_softc *const isc = sc->as_chipc; 578 const pci_chipset_tag_t pc = sc->as_pc; 579 const pcitag_t tag = sc->as_tag; 580 pcireg_t lo, hi; 581 bus_addr_t addr, minaddr, maxaddr; 582 int error; 583 584 /* We always use memory-mapped I/O. */ 585 isc->flush_bst = isc->vga_pa.pa_memt; 586 587 /* No page allocated yet. */ 588 isc->flush_addr = 0; 589 590 /* Read the PCI config register: 4-byte on gen3, 8-byte on gen>=4. */ 591 if (isc->chiptype == CHIP_I915) { 592 addr = pci_conf_read(pc, tag, AGP_I915_IFPADDR); 593 minaddr = PAGE_SIZE; /* XXX PCIBIOS_MIN_MEM? */ 594 maxaddr = UINT32_MAX; 595 } else { 596 hi = pci_conf_read(pc, tag, AGP_I965_IFPADDR+4); 597 lo = pci_conf_read(pc, tag, AGP_I965_IFPADDR); 598 /* 599 * Convert to uint64_t, rather than bus_addr_t which 600 * may be 32-bit, to avoid undefined behaviour with a 601 * too-wide shift. Since the BIOS doesn't know whether 602 * the OS will run 64-bit or with PAE, it ought to 603 * configure at most a 32-bit physical address, so 604 * let's print a warning in case that happens. 605 */ 606 addr = ((uint64_t)hi << 32) | lo; 607 if (hi) { 608 aprint_error_dev(sc->as_dev, 609 "BIOS configured >32-bit flush page address" 610 ": %"PRIx64"\n", ((uint64_t)hi << 32) | lo); 611 #if __i386__ && !PAE 612 return EIO; 613 #endif 614 } 615 minaddr = PAGE_SIZE; /* XXX PCIBIOS_MIN_MEM? */ 616 maxaddr = MIN(UINT64_MAX, ~(bus_addr_t)0); 617 } 618 619 /* Allocate or map a pre-allocated a page for it. */ 620 if (ISSET(addr, 1)) { 621 /* BIOS allocated it for us. Use that. */ 622 error = bus_space_map(isc->flush_bst, addr & ~1, PAGE_SIZE, 0, 623 &isc->flush_bsh); 624 if (error) 625 return error; 626 } else { 627 /* None allocated. Allocate one. */ 628 error = bus_space_alloc(isc->flush_bst, minaddr, maxaddr, 629 PAGE_SIZE, PAGE_SIZE, 0, 0, 630 &isc->flush_addr, &isc->flush_bsh); 631 if (error) 632 return error; 633 KASSERT(isc->flush_addr != 0); 634 /* Write it into the PCI config register. */ 635 addr = isc->flush_addr | 1; 636 if (isc->chiptype == CHIP_I915) { 637 pci_conf_write(pc, tag, AGP_I915_IFPADDR, addr); 638 } else { 639 hi = __SHIFTOUT(addr, __BITS(63, 32)); 640 lo = __SHIFTOUT(addr, __BITS(31, 0)); 641 pci_conf_write(pc, tag, AGP_I965_IFPADDR+4, hi); 642 pci_conf_write(pc, tag, AGP_I965_IFPADDR, lo); 643 } 644 } 645 646 /* Success! */ 647 return 0; 648 } 649 650 static void 651 agp_i810_teardown_chipset_flush_page(struct agp_softc *sc) 652 { 653 struct agp_i810_softc *const isc = sc->as_chipc; 654 655 if (isc->flush_addr) { 656 /* If we allocated a page, clear it. */ 657 if (isc->chiptype == CHIP_I915) { 658 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR, 659 0); 660 } else { 661 pci_conf_write(sc->as_pc, sc->as_tag, 662 AGP_I965_IFPADDR, 0); 663 pci_conf_write(sc->as_pc, sc->as_tag, 664 AGP_I965_IFPADDR + 4, 0); 665 } 666 isc->flush_addr = 0; 667 bus_space_free(isc->flush_bst, isc->flush_bsh, 668 PAGE_SIZE); 669 } else { 670 /* Otherwise, just unmap the pre-allocated page. */ 671 bus_space_unmap(isc->flush_bst, isc->flush_bsh, PAGE_SIZE); 672 } 673 } 674 675 /* 676 * XXX horrible hack to allow drm code to use our mapping 677 * of VGA chip registers 678 */ 679 int 680 agp_i810_borrow(bus_addr_t base, bus_space_handle_t *hdlp) 681 { 682 683 if (!agp_i810_vga_regbase || base != agp_i810_vga_regbase) 684 return 0; 685 *hdlp = agp_i810_vga_bsh; 686 return 1; 687 } 688 689 static int 690 agp_i810_init(struct agp_softc *sc) 691 { 692 struct agp_i810_softc *isc; 693 int error; 694 695 isc = sc->as_chipc; 696 697 if (isc->chiptype == CHIP_I810) { 698 struct agp_gatt *gatt; 699 void *virtual; 700 int dummyseg; 701 702 /* Some i810s have on-chip memory called dcache */ 703 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 704 isc->dcache_size = 4 * 1024 * 1024; 705 else 706 isc->dcache_size = 0; 707 708 /* According to the specs the gatt on the i810 must be 64k */ 709 isc->gtt_size = 64 * 1024; 710 gatt = malloc(sizeof(*gatt), M_AGP, M_NOWAIT); 711 if (gatt == NULL) { 712 aprint_error_dev(sc->as_dev, 713 "can't malloc GATT record\n"); 714 error = ENOMEM; 715 goto fail0; 716 } 717 gatt->ag_entries = isc->gtt_size / sizeof(uint32_t); 718 error = agp_alloc_dmamem(sc->as_dmat, isc->gtt_size, 719 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical, 720 &gatt->ag_dmaseg, 1, &dummyseg); 721 if (error) { 722 aprint_error_dev(sc->as_dev, 723 "can't allocate memory for GTT: %d\n", error); 724 free(gatt, M_AGP); 725 goto fail0; 726 } 727 728 gatt->ag_virtual = (uint32_t *)virtual; 729 gatt->ag_size = gatt->ag_entries * sizeof(uint32_t); 730 memset(gatt->ag_virtual, 0, gatt->ag_size); 731 agp_flush_cache(); 732 733 /* Install the GATT. */ 734 isc->pgtblctl = gatt->ag_physical | 1; 735 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 736 isc->gatt = gatt; 737 } else if (isc->chiptype == CHIP_I830) { 738 /* The i830 automatically initializes the 128k gatt on boot. */ 739 /* XXX [citation needed] */ 740 pcireg_t reg; 741 u_int16_t gcc1; 742 743 isc->gtt_size = 128 * 1024; 744 745 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 746 gcc1 = (u_int16_t)(reg >> 16); 747 switch (gcc1 & AGP_I830_GCC1_GMS) { 748 case AGP_I830_GCC1_GMS_STOLEN_512: 749 isc->stolen = (512 - 132) * 1024 / 4096; 750 break; 751 case AGP_I830_GCC1_GMS_STOLEN_1024: 752 isc->stolen = (1024 - 132) * 1024 / 4096; 753 break; 754 case AGP_I830_GCC1_GMS_STOLEN_8192: 755 isc->stolen = (8192 - 132) * 1024 / 4096; 756 break; 757 default: 758 isc->stolen = 0; 759 aprint_error_dev(sc->as_dev, 760 "unknown memory configuration, disabling\n"); 761 error = ENXIO; 762 goto fail0; 763 } 764 765 if (isc->stolen > 0) { 766 aprint_normal_dev(sc->as_dev, 767 "detected %dk stolen memory\n", 768 isc->stolen * 4); 769 } 770 771 /* GATT address is already in there, make sure it's enabled */ 772 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 773 isc->pgtblctl |= 1; 774 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 775 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 776 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 || 777 isc->chiptype == CHIP_G4X) { 778 pcireg_t reg; 779 u_int32_t gtt_size, stolen; /* XXX kilobytes */ 780 u_int16_t gcc1; 781 782 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1); 783 gcc1 = (u_int16_t)(reg >> 16); 784 785 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL); 786 787 /* Stolen memory is set up at the beginning of the aperture by 788 * the BIOS, consisting of the GATT followed by 4kb for the 789 * BIOS display. 790 */ 791 switch (isc->chiptype) { 792 case CHIP_I855: 793 gtt_size = 128; 794 break; 795 case CHIP_I915: 796 gtt_size = 256; 797 break; 798 case CHIP_I965: 799 switch (isc->pgtblctl & AGP_I810_PGTBL_SIZE_MASK) { 800 case AGP_I810_PGTBL_SIZE_128KB: 801 case AGP_I810_PGTBL_SIZE_512KB: 802 gtt_size = 512; 803 break; 804 case AGP_I965_PGTBL_SIZE_1MB: 805 gtt_size = 1024; 806 break; 807 case AGP_I965_PGTBL_SIZE_2MB: 808 gtt_size = 2048; 809 break; 810 case AGP_I965_PGTBL_SIZE_1_5MB: 811 gtt_size = 1024 + 512; 812 break; 813 default: 814 aprint_error_dev(sc->as_dev, 815 "bad PGTBL size\n"); 816 error = ENXIO; 817 goto fail0; 818 } 819 break; 820 case CHIP_G33: 821 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 822 case AGP_G33_PGTBL_SIZE_1M: 823 gtt_size = 1024; 824 break; 825 case AGP_G33_PGTBL_SIZE_2M: 826 gtt_size = 2048; 827 break; 828 default: 829 aprint_error_dev(sc->as_dev, 830 "bad PGTBL size\n"); 831 error = ENXIO; 832 goto fail0; 833 } 834 break; 835 case CHIP_G4X: 836 gtt_size = 256; 837 break; 838 default: 839 panic("impossible chiptype %d", isc->chiptype); 840 } 841 842 /* 843 * XXX If I'm reading the datasheets right, this stolen 844 * memory detection logic is totally wrong. 845 */ 846 switch (gcc1 & AGP_I855_GCC1_GMS) { 847 case AGP_I855_GCC1_GMS_STOLEN_1M: 848 stolen = 1024; 849 break; 850 case AGP_I855_GCC1_GMS_STOLEN_4M: 851 stolen = 4 * 1024; 852 break; 853 case AGP_I855_GCC1_GMS_STOLEN_8M: 854 stolen = 8 * 1024; 855 break; 856 case AGP_I855_GCC1_GMS_STOLEN_16M: 857 stolen = 16 * 1024; 858 break; 859 case AGP_I855_GCC1_GMS_STOLEN_32M: 860 stolen = 32 * 1024; 861 break; 862 case AGP_I915_GCC1_GMS_STOLEN_48M: 863 stolen = 48 * 1024; 864 break; 865 case AGP_I915_GCC1_GMS_STOLEN_64M: 866 stolen = 64 * 1024; 867 break; 868 case AGP_G33_GCC1_GMS_STOLEN_128M: 869 stolen = 128 * 1024; 870 break; 871 case AGP_G33_GCC1_GMS_STOLEN_256M: 872 stolen = 256 * 1024; 873 break; 874 case AGP_G4X_GCC1_GMS_STOLEN_96M: 875 stolen = 96 * 1024; 876 break; 877 case AGP_G4X_GCC1_GMS_STOLEN_160M: 878 stolen = 160 * 1024; 879 break; 880 case AGP_G4X_GCC1_GMS_STOLEN_224M: 881 stolen = 224 * 1024; 882 break; 883 case AGP_G4X_GCC1_GMS_STOLEN_352M: 884 stolen = 352 * 1024; 885 break; 886 default: 887 aprint_error_dev(sc->as_dev, 888 "unknown memory configuration, disabling\n"); 889 error = ENXIO; 890 goto fail0; 891 } 892 893 switch (gcc1 & AGP_I855_GCC1_GMS) { 894 case AGP_I915_GCC1_GMS_STOLEN_48M: 895 case AGP_I915_GCC1_GMS_STOLEN_64M: 896 if (isc->chiptype != CHIP_I915 && 897 isc->chiptype != CHIP_I965 && 898 isc->chiptype != CHIP_G33 && 899 isc->chiptype != CHIP_G4X) 900 stolen = 0; 901 break; 902 case AGP_G33_GCC1_GMS_STOLEN_128M: 903 case AGP_G33_GCC1_GMS_STOLEN_256M: 904 if (isc->chiptype != CHIP_I965 && 905 isc->chiptype != CHIP_G33 && 906 isc->chiptype != CHIP_G4X) 907 stolen = 0; 908 break; 909 case AGP_G4X_GCC1_GMS_STOLEN_96M: 910 case AGP_G4X_GCC1_GMS_STOLEN_160M: 911 case AGP_G4X_GCC1_GMS_STOLEN_224M: 912 case AGP_G4X_GCC1_GMS_STOLEN_352M: 913 if (isc->chiptype != CHIP_I965 && 914 isc->chiptype != CHIP_G4X) 915 stolen = 0; 916 break; 917 } 918 919 isc->gtt_size = gtt_size * 1024; 920 921 /* BIOS space */ 922 /* XXX [citation needed] */ 923 gtt_size += 4; 924 925 /* XXX [citation needed] for this subtraction */ 926 isc->stolen = (stolen - gtt_size) * 1024 / 4096; 927 928 if (isc->stolen > 0) { 929 aprint_normal_dev(sc->as_dev, 930 "detected %dk stolen memory\n", 931 isc->stolen * 4); 932 } 933 934 /* GATT address is already in there, make sure it's enabled */ 935 isc->pgtblctl |= 1; 936 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl); 937 } 938 939 /* 940 * Make sure the chipset can see everything. 941 */ 942 agp_flush_cache(); 943 944 /* 945 * Publish what we found for kludgey drivers (I'm looking at 946 * you, drm). 947 */ 948 if (agp_i810_sc == NULL) 949 agp_i810_sc = sc; 950 else 951 aprint_error_dev(sc->as_dev, "agp already attached\n"); 952 953 /* Success! */ 954 return 0; 955 956 fail0: KASSERT(error); 957 return error; 958 } 959 960 #if 0 961 static int 962 agp_i810_detach(struct agp_softc *sc) 963 { 964 int error; 965 struct agp_i810_softc *isc = sc->as_chipc; 966 967 error = agp_generic_detach(sc); 968 if (error) 969 return error; 970 971 switch (isc->chiptype) { 972 case CHIP_I915: 973 case CHIP_I965: 974 case CHIP_G33: 975 case CHIP_G4X: 976 agp_i810_teardown_chipset_flush_page(sc); 977 break; 978 } 979 980 /* Clear the GATT base. */ 981 if (sc->chiptype == CHIP_I810) { 982 WRITE4(AGP_I810_PGTBL_CTL, 0); 983 } else { 984 unsigned int pgtblctl; 985 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 986 pgtblctl &= ~1; 987 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 988 } 989 990 if (sc->chiptype == CHIP_I810) { 991 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap, 992 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 993 free(isc->gatt, M_AGP); 994 } 995 996 return 0; 997 } 998 #endif 999 1000 static u_int32_t 1001 agp_i810_get_aperture(struct agp_softc *sc) 1002 { 1003 struct agp_i810_softc *isc = sc->as_chipc; 1004 pcireg_t reg; 1005 u_int32_t size; 1006 u_int16_t miscc, gcc1; 1007 1008 size = 0; 1009 1010 switch (isc->chiptype) { 1011 case CHIP_I810: 1012 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM); 1013 miscc = (u_int16_t)(reg >> 16); 1014 if ((miscc & AGP_I810_MISCC_WINSIZE) == 1015 AGP_I810_MISCC_WINSIZE_32) 1016 size = 32 * 1024 * 1024; 1017 else 1018 size = 64 * 1024 * 1024; 1019 break; 1020 case CHIP_I830: 1021 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0); 1022 gcc1 = (u_int16_t)(reg >> 16); 1023 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 1024 size = 64 * 1024 * 1024; 1025 else 1026 size = 128 * 1024 * 1024; 1027 break; 1028 case CHIP_I855: 1029 size = 128 * 1024 * 1024; 1030 break; 1031 case CHIP_I915: 1032 case CHIP_G33: 1033 case CHIP_G4X: 1034 size = sc->as_apsize; 1035 break; 1036 case CHIP_I965: 1037 size = 512 * 1024 * 1024; 1038 break; 1039 default: 1040 aprint_error(": Unknown chipset\n"); 1041 } 1042 1043 return size; 1044 } 1045 1046 static int 1047 agp_i810_set_aperture(struct agp_softc *sc __unused, 1048 uint32_t aperture __unused) 1049 { 1050 1051 return ENOSYS; 1052 } 1053 1054 static int 1055 agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 1056 { 1057 struct agp_i810_softc *isc = sc->as_chipc; 1058 1059 if (offset < 0 || offset >= ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) { 1060 #ifdef AGP_DEBUG 1061 printf("%s: failed: offset 0x%08x, shift %d, entries %d\n", 1062 device_xname(sc->as_dev), (int)offset, AGP_PAGE_SHIFT, 1063 isc->gtt_size/4); 1064 #endif 1065 return EINVAL; 1066 } 1067 1068 if (isc->chiptype != CHIP_I810) { 1069 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1070 #ifdef AGP_DEBUG 1071 printf("%s: trying to bind into stolen memory\n", 1072 device_xname(sc->as_dev)); 1073 #endif 1074 return EINVAL; 1075 } 1076 } 1077 1078 return agp_i810_write_gtt_entry(isc, offset, physical | 1); 1079 } 1080 1081 static int 1082 agp_i810_unbind_page(struct agp_softc *sc, off_t offset) 1083 { 1084 struct agp_i810_softc *isc = sc->as_chipc; 1085 1086 if (offset < 0 || offset >= ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) 1087 return EINVAL; 1088 1089 if (isc->chiptype != CHIP_I810 ) { 1090 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 1091 #ifdef AGP_DEBUG 1092 printf("%s: trying to unbind from stolen memory\n", 1093 device_xname(sc->as_dev)); 1094 #endif 1095 return EINVAL; 1096 } 1097 } 1098 1099 return agp_i810_write_gtt_entry(isc, offset, 0); 1100 } 1101 1102 /* 1103 * Writing via memory mapped registers already flushes all TLBs. 1104 */ 1105 static void 1106 agp_i810_flush_tlb(struct agp_softc *sc) 1107 { 1108 } 1109 1110 static int 1111 agp_i810_enable(struct agp_softc *sc, u_int32_t mode) 1112 { 1113 1114 return 0; 1115 } 1116 1117 #define AGP_I810_MEMTYPE_MAIN 0 1118 #define AGP_I810_MEMTYPE_DCACHE 1 1119 #define AGP_I810_MEMTYPE_HWCURSOR 2 1120 1121 static struct agp_memory * 1122 agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size) 1123 { 1124 struct agp_i810_softc *isc = sc->as_chipc; 1125 struct agp_memory *mem; 1126 int error; 1127 1128 #ifdef AGP_DEBUG 1129 printf("AGP: alloc(%d, 0x%x)\n", type, (int) size); 1130 #endif 1131 1132 if (size <= 0) 1133 return NULL; 1134 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 1135 return NULL; 1136 KASSERT(sc->as_allocated <= sc->as_maxmem); 1137 if (size > (sc->as_maxmem - sc->as_allocated)) 1138 return NULL; 1139 switch (type) { 1140 case AGP_I810_MEMTYPE_MAIN: 1141 break; 1142 case AGP_I810_MEMTYPE_DCACHE: 1143 if (isc->chiptype != CHIP_I810) 1144 return NULL; 1145 if (size != isc->dcache_size) 1146 return NULL; 1147 break; 1148 case AGP_I810_MEMTYPE_HWCURSOR: 1149 if ((size != AGP_PAGE_SIZE) && 1150 (size != AGP_PAGE_SIZE*4)) 1151 return NULL; 1152 break; 1153 default: 1154 return NULL; 1155 } 1156 1157 mem = malloc(sizeof(*mem), M_AGP, M_WAITOK|M_ZERO); 1158 if (mem == NULL) 1159 goto fail0; 1160 mem->am_id = sc->as_nextid++; 1161 mem->am_size = size; 1162 mem->am_type = type; 1163 1164 switch (type) { 1165 case AGP_I810_MEMTYPE_MAIN: 1166 error = bus_dmamap_create(sc->as_dmat, size, 1167 (size >> AGP_PAGE_SHIFT) + 1, size, 0, BUS_DMA_WAITOK, 1168 &mem->am_dmamap); 1169 if (error) 1170 goto fail1; 1171 break; 1172 case AGP_I810_MEMTYPE_DCACHE: 1173 break; 1174 case AGP_I810_MEMTYPE_HWCURSOR: 1175 mem->am_dmaseg = malloc(sizeof(*mem->am_dmaseg), M_AGP, 1176 M_WAITOK); 1177 error = agp_alloc_dmamem(sc->as_dmat, size, 0, &mem->am_dmamap, 1178 &mem->am_virtual, &mem->am_physical, mem->am_dmaseg, 1, 1179 &mem->am_nseg); 1180 if (error) { 1181 free(mem->am_dmaseg, M_AGP); 1182 goto fail1; 1183 } 1184 (void)memset(mem->am_virtual, 0, size); 1185 break; 1186 default: 1187 panic("invalid agp memory type: %d", type); 1188 } 1189 1190 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link); 1191 sc->as_allocated += size; 1192 1193 return mem; 1194 1195 fail1: free(mem, M_AGP); 1196 fail0: return NULL; 1197 } 1198 1199 static int 1200 agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem) 1201 { 1202 1203 if (mem->am_is_bound) 1204 return EBUSY; 1205 1206 switch (mem->am_type) { 1207 case AGP_I810_MEMTYPE_MAIN: 1208 bus_dmamap_destroy(sc->as_dmat, mem->am_dmamap); 1209 break; 1210 case AGP_I810_MEMTYPE_DCACHE: 1211 break; 1212 case AGP_I810_MEMTYPE_HWCURSOR: 1213 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap, 1214 mem->am_virtual, mem->am_dmaseg, mem->am_nseg); 1215 free(mem->am_dmaseg, M_AGP); 1216 break; 1217 default: 1218 panic("invalid agp i810 memory type: %d", mem->am_type); 1219 } 1220 1221 sc->as_allocated -= mem->am_size; 1222 TAILQ_REMOVE(&sc->as_memory, mem, am_link); 1223 free(mem, M_AGP); 1224 1225 return 0; 1226 } 1227 1228 static int 1229 agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem, 1230 off_t offset) 1231 { 1232 struct agp_i810_softc *isc = sc->as_chipc; 1233 uint32_t pgtblctl; 1234 int error; 1235 1236 if (mem->am_is_bound) 1237 return EINVAL; 1238 1239 /* 1240 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 1241 * X server for mysterious reasons which leads to crashes if we write 1242 * to the GTT through the MMIO window. 1243 * Until the issue is solved, simply restore it. 1244 */ 1245 pgtblctl = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL); 1246 if (pgtblctl != isc->pgtblctl) { 1247 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%"PRIx32 1248 " - fixing\n", pgtblctl); 1249 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL, 1250 isc->pgtblctl); 1251 } 1252 1253 switch (mem->am_type) { 1254 case AGP_I810_MEMTYPE_MAIN: 1255 error = agp_i810_bind_memory_main(sc, mem, offset); 1256 break; 1257 case AGP_I810_MEMTYPE_DCACHE: 1258 error = agp_i810_bind_memory_dcache(sc, mem, offset); 1259 break; 1260 case AGP_I810_MEMTYPE_HWCURSOR: 1261 error = agp_i810_bind_memory_hwcursor(sc, mem, offset); 1262 break; 1263 default: 1264 panic("invalid agp i810 memory type: %d", mem->am_type); 1265 } 1266 if (error) 1267 return error; 1268 1269 /* Success! */ 1270 mem->am_is_bound = 1; 1271 return 0; 1272 } 1273 1274 static int 1275 agp_i810_bind_memory_main(struct agp_softc *sc, struct agp_memory *mem, 1276 off_t offset) 1277 { 1278 struct agp_i810_softc *const isc = sc->as_chipc; 1279 int nseg; 1280 uint32_t i, j; 1281 unsigned seg; 1282 bus_addr_t addr; 1283 bus_size_t len; 1284 int error; 1285 1286 /* Ensure we have a sane size/offset that will fit. */ 1287 if (offset < 0) 1288 return EINVAL; 1289 if (offset & (AGP_PAGE_SIZE - 1)) 1290 return EINVAL; 1291 if (mem->am_size > ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) 1292 return EINVAL; 1293 if (offset > (((isc->gtt_size/4) << AGP_PAGE_SHIFT) - 1294 mem->am_size)) 1295 return EINVAL; 1296 1297 /* Allocate an array of DMA segments. */ 1298 nseg = (mem->am_size >> AGP_PAGE_SHIFT); 1299 if (nseg > (SIZE_MAX / sizeof(*mem->am_dmaseg))) { 1300 error = ENOMEM; 1301 goto fail0; 1302 } 1303 mem->am_dmaseg = malloc(nseg*sizeof(*mem->am_dmaseg), M_AGP, M_WAITOK); 1304 1305 /* Allocate DMA-safe physical segments. */ 1306 error = bus_dmamem_alloc(sc->as_dmat, mem->am_size, PAGE_SIZE, 1307 0, mem->am_dmaseg, nseg, &mem->am_nseg, BUS_DMA_WAITOK); 1308 if (error) 1309 goto fail1; 1310 KASSERT(mem->am_nseg <= nseg); 1311 1312 /* Shrink the array of DMA segments if we can. */ 1313 if (mem->am_nseg < nseg) { 1314 mem->am_dmaseg = realloc(mem->am_dmaseg, mem->am_nseg, M_AGP, 1315 M_WAITOK); 1316 nseg = mem->am_nseg; 1317 } 1318 1319 /* Load the DMA map. */ 1320 error = bus_dmamap_load_raw(sc->as_dmat, mem->am_dmamap, 1321 mem->am_dmaseg, mem->am_nseg, mem->am_size, BUS_DMA_WAITOK); 1322 if (error) 1323 goto fail2; 1324 1325 /* Bind the pages in the GTT. */ 1326 i = 0; 1327 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0); 1328 for (seg = 0; seg < mem->am_dmamap->dm_nsegs; seg++) { 1329 KASSERT((offset + i) < mem->am_size); 1330 addr = mem->am_dmamap->dm_segs[seg].ds_addr; 1331 len = MIN(mem->am_dmamap->dm_segs[seg].ds_len, 1332 (mem->am_size - (offset + i))); 1333 do { 1334 KASSERT(0 < len); 1335 KASSERT((len & (AGP_PAGE_SIZE - 1)) == 0); 1336 KASSERT((offset + i) <= (mem->am_size - len)); 1337 error = agp_i810_bind_page(sc, offset + i, addr); 1338 if (error) 1339 goto fail3; 1340 i += AGP_PAGE_SIZE; 1341 addr += AGP_PAGE_SIZE; 1342 len -= AGP_PAGE_SIZE; 1343 } while (0 < len); 1344 } 1345 1346 /* Success! */ 1347 mem->am_offset = offset; 1348 return 0; 1349 1350 fail3: for (j = 0; j < i; j += AGP_PAGE_SIZE) 1351 (void)agp_i810_unbind_page(sc, offset + j); 1352 bus_dmamap_unload(sc->as_dmat, mem->am_dmamap); 1353 fail2: bus_dmamem_free(sc->as_dmat, mem->am_dmaseg, mem->am_nseg); 1354 fail1: free(mem->am_dmaseg, M_AGP); 1355 mem->am_dmaseg = NULL; 1356 mem->am_nseg = 0; 1357 fail0: KASSERT(error); 1358 return error; 1359 } 1360 1361 #define I810_GTT_PTE_VALID 0x01 1362 #define I810_GTT_PTE_DCACHE 0x02 1363 1364 static int 1365 agp_i810_bind_memory_dcache(struct agp_softc *sc, struct agp_memory *mem, 1366 off_t offset) 1367 { 1368 struct agp_i810_softc *const isc __diagused = sc->as_chipc; 1369 uint32_t i, j; 1370 int error; 1371 1372 KASSERT(isc->chiptype == CHIP_I810); 1373 1374 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0); 1375 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 1376 /* XXX No offset? */ 1377 error = agp_i810_write_gtt_entry(isc, i, 1378 i | I810_GTT_PTE_VALID | I810_GTT_PTE_DCACHE); 1379 if (error) 1380 goto fail0; 1381 } 1382 1383 /* Success! */ 1384 return 0; 1385 1386 fail0: for (j = 0; j < i; j += AGP_PAGE_SIZE) 1387 (void)agp_i810_unbind_page(sc, offset + j); 1388 return error; 1389 } 1390 1391 static int 1392 agp_i810_bind_memory_hwcursor(struct agp_softc *sc, struct agp_memory *mem, 1393 off_t offset) 1394 { 1395 const bus_addr_t pa = mem->am_physical; 1396 uint32_t i, j; 1397 int error; 1398 1399 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0); 1400 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 1401 error = agp_i810_bind_page(sc, offset + i, pa + i); 1402 if (error) 1403 goto fail0; 1404 } 1405 1406 /* Success! */ 1407 mem->am_offset = offset; 1408 return 0; 1409 1410 fail0: for (j = 0; j < i; j += AGP_PAGE_SIZE) 1411 (void)agp_i810_unbind_page(sc, offset + j); 1412 return error; 1413 } 1414 1415 static int 1416 agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem) 1417 { 1418 struct agp_i810_softc *isc = sc->as_chipc; 1419 u_int32_t i; 1420 1421 if (!mem->am_is_bound) 1422 return EINVAL; 1423 1424 switch (mem->am_type) { 1425 case AGP_I810_MEMTYPE_MAIN: 1426 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1427 (void)agp_i810_unbind_page(sc, mem->am_offset + i); 1428 bus_dmamap_unload(sc->as_dmat, mem->am_dmamap); 1429 bus_dmamem_free(sc->as_dmat, mem->am_dmaseg, mem->am_nseg); 1430 free(mem->am_dmaseg, M_AGP); 1431 mem->am_offset = 0; 1432 break; 1433 case AGP_I810_MEMTYPE_DCACHE: 1434 KASSERT(isc->chiptype == CHIP_I810); 1435 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1436 (void)agp_i810_write_gtt_entry(isc, i, 0); 1437 break; 1438 case AGP_I810_MEMTYPE_HWCURSOR: 1439 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 1440 (void)agp_i810_unbind_page(sc, mem->am_offset + i); 1441 mem->am_offset = 0; 1442 break; 1443 default: 1444 panic("invalid agp i810 memory type: %d", mem->am_type); 1445 } 1446 1447 mem->am_is_bound = 0; 1448 return 0; 1449 } 1450 1451 static bool 1452 agp_i810_resume(device_t dv, const pmf_qual_t *qual) 1453 { 1454 struct agp_softc *sc = device_private(dv); 1455 struct agp_i810_softc *isc = sc->as_chipc; 1456 1457 /* 1458 * XXX Nothing uses this! Save on suspend, restore on resume? 1459 */ 1460 isc->pgtblctl_resume_hack = READ4(AGP_I810_PGTBL_CTL); 1461 agp_flush_cache(); 1462 1463 return true; 1464 } 1465
Indexes created Fri Sep 26 08:10:20 GMT 2025