agp_intel.c revision 1.10
1 /* $NetBSD: agp_intel.c,v 1.10 2003/06/25 20:33:59 ichiro Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/pci/agp_intel.c,v 1.4 2001/07/05 21:28:47 jhb Exp $ 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: agp_intel.c,v 1.10 2003/06/25 20:33:59 ichiro Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/proc.h> 40 #include <sys/agpio.h> 41 #include <sys/device.h> 42 #include <sys/agpio.h> 43 44 #include <uvm/uvm_extern.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcidevs.h> 49 #include <dev/pci/agpvar.h> 50 #include <dev/pci/agpreg.h> 51 52 #include <machine/bus.h> 53 54 struct agp_intel_softc { 55 u_int32_t initial_aperture; 56 /* aperture size at startup */ 57 struct agp_gatt *gatt; 58 struct pci_attach_args vga_pa; 59 u_int aperture_mask; 60 int chiptype; /* Chip type */ 61 #define CHIP_INTEL 0x0 62 #define CHIP_I443 0x1 63 #define CHIP_I840 0x2 64 #define CHIP_I845 0x3 65 #define CHIP_I850 0x4 66 }; 67 68 static u_int32_t agp_intel_get_aperture(struct agp_softc *); 69 static int agp_intel_set_aperture(struct agp_softc *, u_int32_t); 70 static int agp_intel_bind_page(struct agp_softc *, off_t, bus_addr_t); 71 static int agp_intel_unbind_page(struct agp_softc *, off_t); 72 static void agp_intel_flush_tlb(struct agp_softc *); 73 74 struct agp_methods agp_intel_methods = { 75 agp_intel_get_aperture, 76 agp_intel_set_aperture, 77 agp_intel_bind_page, 78 agp_intel_unbind_page, 79 agp_intel_flush_tlb, 80 agp_generic_enable, 81 agp_generic_alloc_memory, 82 agp_generic_free_memory, 83 agp_generic_bind_memory, 84 agp_generic_unbind_memory, 85 }; 86 87 static int 88 agp_intel_vgamatch(struct pci_attach_args *pa) 89 { 90 switch (PCI_PRODUCT(pa->pa_id)) { 91 case PCI_PRODUCT_INTEL_82855PM_AGP: 92 case PCI_PRODUCT_INTEL_82443LX_AGP: 93 case PCI_PRODUCT_INTEL_82443BX_AGP: 94 case PCI_PRODUCT_INTEL_82443GX_AGP: 95 case PCI_PRODUCT_INTEL_82850_AGP: /* i850/i860 */ 96 case PCI_PRODUCT_INTEL_82845_AGP: 97 case PCI_PRODUCT_INTEL_82840_AGP: 98 return (1); 99 } 100 101 return (0); 102 } 103 104 int 105 agp_intel_attach(struct device *parent, struct device *self, void *aux) 106 { 107 struct agp_softc *sc = (struct agp_softc *)self; 108 struct pci_attach_args *pa= aux; 109 struct agp_intel_softc *isc; 110 struct agp_gatt *gatt; 111 pcireg_t reg; 112 u_int32_t value; 113 114 isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO); 115 if (isc == NULL) { 116 aprint_error(": can't allocate chipset-specific softc\n"); 117 return ENOMEM; 118 } 119 120 sc->as_methods = &agp_intel_methods; 121 sc->as_chipc = isc; 122 123 if (pci_find_device(&isc->vga_pa, agp_intel_vgamatch) == 0) { 124 aprint_normal(": using generic initialization for Intel AGP\n"); 125 isc->chiptype = CHIP_INTEL; 126 } 127 128 pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, &sc->as_capoff, 129 NULL); 130 131 if (agp_map_aperture(pa, sc) != 0) { 132 aprint_error(": can't map aperture\n"); 133 free(isc, M_AGP); 134 sc->as_chipc = NULL; 135 return ENXIO; 136 } 137 138 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) { 139 case PCI_PRODUCT_INTEL_82855PM_AGP: 140 case PCI_PRODUCT_INTEL_82845_AGP: 141 isc->chiptype = CHIP_I845; 142 break; 143 case PCI_PRODUCT_INTEL_82840_AGP: 144 isc->chiptype = CHIP_I840; 145 break; 146 case PCI_PRODUCT_INTEL_82850_AGP: 147 isc->chiptype = CHIP_I850; 148 break; 149 case PCI_PRODUCT_INTEL_82443LX_AGP: 150 case PCI_PRODUCT_INTEL_82443BX_AGP: 151 case PCI_PRODUCT_INTEL_82443GX_AGP: 152 isc->chiptype = CHIP_I443; 153 break; 154 } 155 156 /* Determine maximum supported aperture size. */ 157 value = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE); 158 pci_conf_write(sc->as_pc, sc->as_tag, 159 AGP_INTEL_APSIZE, APSIZE_MASK); 160 isc->aperture_mask = pci_conf_read(sc->as_pc, sc->as_tag, 161 AGP_INTEL_APSIZE) & APSIZE_MASK; 162 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE, value); 163 isc->initial_aperture = AGP_GET_APERTURE(sc); 164 165 for (;;) { 166 gatt = agp_alloc_gatt(sc); 167 if (gatt) 168 break; 169 170 /* 171 * Probably contigmalloc failure. Try reducing the 172 * aperture so that the gatt size reduces. 173 */ 174 if (AGP_SET_APERTURE(sc, AGP_GET_APERTURE(sc) / 2)) { 175 agp_generic_detach(sc); 176 aprint_error(": failed to set aperture\n"); 177 return ENOMEM; 178 } 179 } 180 isc->gatt = gatt; 181 182 /* Install the gatt. */ 183 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 184 gatt->ag_physical); 185 186 /* Enable the GLTB and setup the control register. */ 187 switch (isc->chiptype) { 188 case CHIP_I443: 189 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 190 AGPCTRL_AGPRSE | AGPCTRL_GTLB); 191 192 default: 193 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 194 pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL) 195 | AGPCTRL_GTLB); 196 } 197 198 /* Enable things, clear errors etc. */ 199 switch (isc->chiptype) { 200 case CHIP_I845: 201 { 202 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD, 203 AGPCMD_SBA | AGPCMD_AGPEN | AGPCMD_RATE_4X); 204 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I845_AGPMISC, AGPMISC_AAGN); 205 break; 206 } 207 case CHIP_I840: 208 case CHIP_I850: 209 { 210 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD); 211 reg |= AGPCMD_AGPEN; 212 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD, 213 reg); 214 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG); 215 reg |= MCHCFG_AAGN; 216 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG, 217 reg); 218 break; 219 } 220 default: 221 { 222 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG); 223 reg &= ~NBXCFG_APAE; 224 reg |= NBXCFG_AAGN; 225 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg); 226 } 227 } 228 229 /* Clear Error status */ 230 switch (isc->chiptype) { 231 case CHIP_I840: 232 pci_conf_write(sc->as_pc, sc->as_tag, 233 AGP_INTEL_I8XX_ERRSTS, 0xc000); 234 break; 235 236 case CHIP_I850: 237 case CHIP_I845: 238 pci_conf_write(sc->as_pc, sc->as_tag, 239 AGP_INTEL_I8XX_ERRSTS, 0x00ff); 240 break; 241 242 default: 243 pci_conf_write(sc->as_pc, sc->as_tag, 244 AGP_INTEL_ERRSTS, 0x70); 245 } 246 247 return (0); 248 } 249 250 #if 0 251 static int 252 agp_intel_detach(struct agp_softc *sc) 253 { 254 int error; 255 pcireg_t reg; 256 struct agp_intel_softc *isc = sc->as_chipc; 257 258 error = agp_generic_detach(sc); 259 if (error) 260 return error; 261 262 /* XXX i845/i855PM/i840/i850E */ 263 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG); 264 reg &= ~(1 << 9); 265 printf("%s: set NBXCFG to %x\n", __FUNCTION__, reg); 266 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg); 267 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 0); 268 AGP_SET_APERTURE(sc, isc->initial_aperture); 269 agp_free_gatt(sc, isc->gatt); 270 271 return 0; 272 } 273 #endif 274 275 static u_int32_t 276 agp_intel_get_aperture(struct agp_softc *sc) 277 { 278 struct agp_intel_softc *isc = sc->as_chipc; 279 u_int32_t apsize; 280 281 apsize = pci_conf_read(sc->as_pc, sc->as_tag, 282 AGP_INTEL_APSIZE) & isc->aperture_mask; 283 284 /* 285 * The size is determined by the number of low bits of 286 * register APBASE which are forced to zero. The low 22 bits 287 * are always forced to zero and each zero bit in the apsize 288 * field just read forces the corresponding bit in the 27:22 289 * to be zero. We calculate the aperture size accordingly. 290 */ 291 return (((apsize ^ isc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1; 292 } 293 294 static int 295 agp_intel_set_aperture(struct agp_softc *sc, u_int32_t aperture) 296 { 297 struct agp_intel_softc *isc = sc->as_chipc; 298 u_int32_t apsize; 299 300 /* 301 * Reverse the magic from get_aperture. 302 */ 303 apsize = ((aperture - 1) >> 22) ^ isc->aperture_mask; 304 305 /* 306 * Double check for sanity. 307 */ 308 if ((((apsize ^ isc->aperture_mask) << 22) | 309 ((1 << 22) - 1)) + 1 != aperture) 310 return EINVAL; 311 312 pci_conf_write(sc->as_pc, sc->as_tag, 313 AGP_INTEL_APSIZE, apsize); 314 315 return 0; 316 } 317 318 static int 319 agp_intel_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical) 320 { 321 struct agp_intel_softc *isc = sc->as_chipc; 322 323 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 324 return EINVAL; 325 326 isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 327 return 0; 328 } 329 330 static int 331 agp_intel_unbind_page(struct agp_softc *sc, off_t offset) 332 { 333 struct agp_intel_softc *isc = sc->as_chipc; 334 335 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 336 return EINVAL; 337 338 isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 339 return 0; 340 } 341 342 static void 343 agp_intel_flush_tlb(struct agp_softc *sc) 344 { 345 struct agp_intel_softc *isc = sc->as_chipc; 346 pcireg_t reg; 347 348 switch (isc->chiptype) { 349 case CHIP_I850: 350 case CHIP_I845: 351 case CHIP_I840: 352 case CHIP_I443: 353 { 354 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL); 355 reg &= ~AGPCTRL_GTLB; 356 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 357 reg); 358 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 359 reg | AGPCTRL_GTLB); 360 break; 361 } 362 default: /* XXX */ 363 { 364 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 365 0x2200); 366 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL, 367 0x2280); 368 } 369 } 370 } 371
Indexes created Thu Oct 02 01:09:59 GMT 2025